KR19990061048A - High voltage generator - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage generator for generating a high voltage higher than a power supply voltage using a pump principle in a semiconductor memory device. In particular, the present invention relates to first and second precharging of an internal power supply voltage to first and second precharge nodes. A current path switching for activating two current paths alternately according to a potential level of each pre-charge unit and each control signal for varying the potentials of the first and second precharge nodes to transfer a predetermined potential to the bootstrap node. A high voltage output unit which bootstraps the bootstrap node to a high voltage by a bootstrapping means and outputs the output to the output terminal, and a latch-up which transmits an external power supply voltage to a high voltage output node to prevent latch-up of the high voltage output unit. With the prevention part, even when the operating voltage is high, the latch-up phenomenon does not occur and the pumping efficiency is high. It relates to a high voltage generator.

Description

High voltage generator

The present invention relates to a high voltage generator that generates a high voltage higher than a power supply voltage using a pump principle in a semiconductor memory device. In particular, a high voltage generator which does not generate a latch-up phenomenon even with a high operating voltage and has a high pumping efficiency. It is about.

In general, a high voltage generator (hereinafter referred to as 'Vpp') is a device that supplies a constant high voltage to a circuit in a chip that requires a voltage higher than the first power supply voltage Vcc in a semiconductor device, and detects a Vpp potential level. The Vpp pumping circuit is controlled by a level detector for outputting a signal, a ring oscillator for generating pulses for periodic charge pumping, a Vpp pumping circuit for pumping Vpp charges, and an output pulse from the ring oscillator It consists of a pump control circuit.

FIG. 1 is a circuit diagram showing a first embodiment of a conventional high voltage generator, and includes a plurality of N-channel MOS transistors MN1 to MN4 to clamp a pre-charged external power supply voltage Vext to a predetermined level. 10) and precharge units C1 and C3 for precharge nodes N1 and N3 to maintain a predetermined level of precharge according to the potential levels of the control signals a and c, and the control signals a and c. To the first transmission units MN5 and MN6 for selectively transmitting the output signal of the clamp unit 10 to the bootstrap nodes N2 and N4, and the bootstrap nodes N2 and N4 according to the potential level of Pumping capacitors C3 and C4 that occupy a high voltage, and second transfer parts MP1 and MP2 that finally output the pumped voltages of the bootstrap nodes N2 and N4 to the high voltage applying terminal Vpp. do.

In the operation of the conventional high voltage generator having the above configuration, first, when the control signal c transitions from 'high' to 'low', the sixth N-channel MOS transistor MN6 is turned off to be the fourth of the bootstrap node. The path between the node N4 and the external power supply voltage Vext is cut off. After that, when the control signal d transitions from 'low' to 'high', the fourth node N4 precharged with Vd (transition voltage of the d signal) becomes 'Vd + Vext'. In this state, when the control signal b transitions from 'high' to 'low', the second P-channel MOS transistor MP2 is turned on so that the charge Vd + Vext of the fourth node N4 is Vpp. Is output.

After the charge is sufficiently output to the Vpp output terminal, when the control signal a transitions from 'low' to 'high', the first node N1, which is one side of the precharge node, becomes 'Vext + Vt (the threshold voltage of MN2)'. When the threshold voltage Vt2 of the second N-channel MOS transistor MN2 is greater than the threshold voltage Vt5 of the fifth N-channel MOS transistor MN5, the fifth N-channel MOS transistor MN5 is turned on. By doing so, the second node N2 is precharged to Vb, which is the transition voltage of the control signal b. Then, when the control signal a transitions from 'high' to 'low' again, the path between the second node N2 and the external power supply voltage Vext is cut off. In this state, when the control signal b transitions from 'low' to 'high', the second node N2 bootstrap and becomes 'Vb + Vext', and the control signal d becomes 'high' to 'high'. When the signal transitions to the low ', the first P-channel MOS transistor MP1 is turned on to output the charge Vb + Vext bootstraped to the second node N2 to the Vpp output terminal.

After sufficient charge is transferred to the Vpp output terminal, when the control signal c transitions from 'low' to 'high', the third node N3 becomes 'Vext + Vt3 (threshold voltage of MN3)' to form the third N-channel. When the threshold voltage Vt3 of the MOS transistor MN3 is greater than the threshold voltage Vt6 of the sixth N-channel MOS transistor MN6, the fourth node N4 is turned on by turning on the sixth N-channel MOS transistor MN6. ) Is precharged to Vd, the transition voltage of the control signal d, and the subsequent operation is performed in the same manner as the above process.

However, when the charge of the fourth node N4 is output at Vpp in the operation, when the external power supply voltage Vext is high, not only charge transfer from the fourth node N4 to Vpp, but also the second P-channel MOS transistor. The PN diode between the source and the bulk terminal of (MP2) is turned on, causing a latch-up phenomenon in which excessive current flows.

FIG. 2 is a circuit diagram illustrating a second embodiment of a conventional high voltage generator, wherein the precharge voltage of the pumping circuit is changed from Vpp-Vt to prevent a latch-up phenomenon, which is a problem of the high voltage generator shown in FIG. It is characterized by limiting.

The configuration is not directly connected to the source terminal of the fifth and sixth N-channel MOS transistors to the clamp terminal 10 of the high voltage generator shown in FIG. Vext) further includes a seventh N-channel MOS transistor to which Vpp is commonly applied as a gate between the applying end and the common source connection node of the fifth and sixth N-channel MOS transistors.

3 illustrates an operation timing diagram of the high voltage generator illustrated in FIG. 2, wherein each of the precharge nodes N1 and N3 and the bootstrap node according to the potential change of the control signals a, b, c, and d is shown. The potential change of (N2, N4) is shown, which will be apparent from the operation description below.

The operation of the high voltage generator having the above configuration will now be described by way of example.

If the external supply voltage is 7V and the voltage down converter (VDC) is 3.3V, the initial Vpp voltage is 3.3V-Vt. First, when the control signal c transitions from 'low' to 'high', the first node N1 becomes Vext + Vt, and the second node N2 is precharged to Vpp-Vt, and the control signal b When transitioning from low to high, the second node N2 is bootstrapd.

Looking at the opposite operation, when the control signal d transitions from 'low' to 'high' similar to the first and second nodes, the third node N3 also becomes Vext + Vt and the fourth node N4. ) Is precharged to Vpp-Vt. In this case, when the control signal b transitions from 'logic low' to 'logic high' again, when the first node N1 transitions from 'high' to 'low' when the second node N2 bootstrap. In the normal operation, the first P-channel MOS transistor MP1 is turned on so that all the charges of the second node N2 must be transferred to the Vpp output terminal through the first P-channel MOS transistor MP1, but the first P-channel MOS transistor MP1 is turned on. In addition to the current path to the transistor MP1, the voltages of the first and third nodes N1 and N3 are Vext-Vt and Vext + Vt, respectively, and are higher than the precharge voltage of the second node N2. A current path to the fourth node N4 is also formed through the 6 N-channel MOS transistors MN3 and MN6.

That is, when the control signal b transitions from 'low' to 'high', the fourth node N2 bootstrap and is precharged to Vpp -Vt through the first P-channel MOS transistor MP1. Exit to node N4.

Therefore, the pumping operation is continued, but since charge transfer to Vpp is not performed, a normal Vpp voltage cannot be obtained.

As a result, the high voltage generator shown in FIG. 2 may precharge the bootstrap nodes N2 and N4 to a limited value of Vpp-Vt to prevent the latch-up phenomenon from occurring during the pumping operation. → N2 → MN5 → MN7) due to the formation of a reduction in pumping efficiency is a problem that is caused.

FIG. 4 is an operation timing diagram illustrating a leakage current path of the high voltage generator illustrated in FIG. 2, wherein the second node N2 does not completely transfer charge to the Vpp output terminal during bootstrap, and the fourth node may be formed by the leakage current. It is equal to the voltage of N4).

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to configure the bootstrap node precharge voltage to a constant potential to prevent the occurrence of latch-up even when operating at a high external power supply voltage, In addition, by separating the precharge transistors of the two precharge nodes to reduce the leakage current path to provide a high voltage generator with improved pumping efficiency.

1 is a circuit diagram showing a first embodiment of a conventional high voltage generator

2 is a circuit diagram showing a second embodiment of a conventional high voltage generator

3 is an operation timing diagram of FIG. 2.

4 is an operation timing diagram illustrating the leakage current path of FIG. 2;

5 is a circuit diagram of a high voltage generator according to the present invention.

6 is an operation timing diagram of FIG. 5.

7 is an operation timing diagram illustrating the leakage current path elimination of FIG. 5.

Explanation of symbols for main parts of the drawings

10, 11: clamp portion 20, 21: precharge portion

30: current path switching unit 40: high voltage output unit

50: latch-up prevention part

In order to achieve the above object, the high voltage generator according to the present invention includes first and second precharge units for initially precharging an internal power supply voltage to first and second precharge nodes, and the first and second precharge units. A current path switching unit for alternately activating the two current paths according to the potential level of each control signal for varying the potential of the node and transferring a predetermined potential to the bootstrap node; A high voltage output unit bootstrap and outputs to the output terminal, and a latch-up prevention unit for transmitting an external power supply voltage to the high voltage output node to prevent the latch-up of the high voltage output unit.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a circuit diagram of a high voltage generator according to an embodiment of the present invention, and includes a first N-channel MOS transistors MN5 and MN6 connected between an internal power supply voltage Vint and a precharge node N1 or N3 on both sides. And activates only one current path among the plurality of current paths according to the potential levels of the second precharge units 20 and 21 and the control signals a and c for varying the potentials of the precharge nodes N1 and N3. Between the current path switching unit 30 which transfers a predetermined potential (external power voltage-high voltage) to the bootstrap nodes N2 and N4, and between the bootstrap nodes N2 and N4 and the high potential output node Vpp. A high voltage output unit 40 connected to each other and having the bootstrap nodes N2 and N4 connected to the respective gates in a cross-coupled structure, and the high voltage output unit 40 of the high voltage output unit 40. Power-Up Gateed to Prevent Latch-Up Consists of up preventing portions 50 - Ho N-channel MOS transistor (MN9), the latch comprising passing an external supply voltage (Vext) by (/ pwrup) to the output node (Vpp).

The plurality of current paths refer to a first path from the Vext applying stage to the MN1 → MN7 → N2 → MP1 → Vpp output stage and a second path from the Vext applying stage → MN2 → MN8 → N4 → Vpp output stage.

In the current path switching unit 30, the external power voltage Vext is applied to each source, and the gates of the first and second N-channel MOS transistors MN1 and MN2 are commonly connected to a high voltage applying terminal Vpp. ) And the seventh and eighth N-channel MOS transistors MN7 connected to drains of the first and second N-channel MOS transistors MN1 and MN2, respectively, and the gates thereof are respectively connected to the precharge nodes N1 and N3. , MN8, between the connection node of the first N-channel MOS transistor MN1 and the seventh N-channel MOS transistor MN7 and the precharge node N1, and the second N-channel MOS transistor MN2 Third and fourth N connected between the connection node and the precharge node N3 of the eighth N-channel MOS transistor MN8, respectively, and the two precharge nodes N1 and N3 are connected to each gate in a cross-coupled structure. It consists of channel MOS transistors MN3 and MN4.

Hereinafter, the operation of the present invention having the above configuration will be described with reference to the drawings.

FIG. 6 shows an overall operation timing diagram of the high voltage generator shown in FIG. 5 and will be apparent from the operation description below.

First, when the external power supply voltage Vext is applied, the third node N3 is precharged by Vint −Vt, and the first node N1 boots when the control signal c transitions from 'low' to 'high'. When strapped, the fourth N-channel MOS transistor MN4 is turned on so that the third node N3 is precharged from Vint -Vt to Vint. At this time, when the control signal d transitions from 0V to the external power supply voltage Vext, the potential of the third node N3 is bootstrapd to Vint + Vext and precharges the fourth node N4 to Vext -Vpp. Let's do it.

When the control signal d is changed from Vext to 0V, the third node N3 is changed to Vint and the eighth N-channel MOS transistor MN8 is turned off.

In this state, when the external power supply voltage Vext is applied to the control signal a, the fourth node N4 is bootstrapd to Vext-Vpp + Vext, and when the control signal b is changed from Vext to 0V, The second P-channel MOS transistor MP2 is turned on so that the potential of the fourth node N4 is transferred to the high voltage output terminal Vpp through the second P-channel MOS transistor MP2.

However, when the control signal c changes from 0V to Vext, the seventh N-channel MOS transistor MN7 is turned off. At this time, when the control signal b transitions from 0V to Vext, the second node N2 Bootstrapped from Vext to Vpp + Vext, the control signal a changes from Vext to 0V and the first P-channel MOS transistor MP1 is turned on to charge the second node N2 to the high voltage output terminal Vpp. Will be delivered.

Then, as the control signal d changes from 0V to Vext again, the third node N3 is bootstraped to Vint + Vext. At this time, the third N-channel MOS transistor MN3 is turned on to turn on the first node N1. Fully precharged to Vint, the eighth N-channel MOS transistor MN8 is turned on to precharge the fourth node N4 back to Vext −Vpp. When the control signal d changes from Vext to 0V again, the third node N3 changes from Vint + Vext to Vint, and thus the eighth N-channel MOS transistor MN8 is turned off.

When the control signal a is changed from 0V to Vext, the fourth node N4 is bootstrap from Vext-Vpp to Vext-Vpp + Vext.

The above operation is repeated until the output voltage high voltage Vpp reaches the target value.

FIG. 7 is an operation timing diagram in which the leakage current path of the high voltage generator according to the present invention shown in FIG. 5 is removed. Compared to the waveform of FIG. 4, two bootstrap nodes N2 and N4 have a constant potential difference at the same time period. It is maintained.

This is configured by separating the first and second N-channel MOS transistors MN1 and MN2 to which the high voltage Vpp is applied to the gate, so that the fourth node N4 when the control signal a transitions from 0V to Vext. This means that a more stable operation can be obtained by removing a leakage current path through which bootstrap-charged charges are transferred to the second node N2.

As described above, the high voltage generator according to the present invention eliminates unnecessary current consumption by preventing latch-up generated at a high external power voltage when implementing a high voltage pumping operation, and is always stable regardless of the ramp-up speed of the power voltage. There is a very good effect of obtaining a high voltage.

In addition, there is a very excellent effect that can prevent the formation of the leakage current path to increase the high voltage pumping efficiency.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (5)

First and second precharge units for initially precharging internal power supply voltages to the first and second precharge nodes; A current path switching unit for alternately activating two current paths according to the potential levels of the respective control signals varying the potentials of the first and second precharge nodes to transfer a predetermined potential to the bootstrap node; A high voltage output unit configured to bootstrap the bootstrap node to a high voltage by a bootstrapping means and output the same to an output terminal; And a latch-up prevention unit configured to transfer an external power supply voltage to a high-voltage output node to prevent latch-up of the high-voltage output unit. The method of claim 1, And the first and second precharge parts comprise N-channel MOS transistors. The method of claim 1, The current path switching unit may be branched into a plurality of current paths by a high voltage applying stage, and pass first and second switching devices to pass an external power supply voltage when the high voltage is applied; Third and fourth switching elements connected to the output terminals of the first and second switching elements, respectively, and selectively turned on according to the control signal potential level to transfer an external power supply voltage to the high voltage output unit; A fifth connected between a connection node of the first and third switching elements and a connection node of the second and fourth switching elements, respectively, and each control terminal is cross-coupled to the first and second precharge nodes; And a sixth switching element. The method of claim 1, The first to sixth switching element is a high voltage generator, characterized in that consisting of N-channel MOS transistor. The method of claim 1, And the latch-up prevention part is formed of an N-channel MOS transistor whose operation is controlled by a power-up signal.