KR19990060906A - Method of manufacturing transistor of semiconductor device - Google Patents

Abstract

The present invention relates to annealing in a metal-polycide gate structure transistor under a nitrogen (N ₂ ) atmosphere before an oxidation process for forming a spacer oxide layer for forming a lightly doped drain (LDD) structure. ) To increase the resistance uniformity of the metal silicide layer by suppressing the formation of the compound by abnormal reaction of the metal-silicide sidewall, which is the upper layer, during the oxidation process for forming the spacer oxide film. The present invention relates to a method of fabricating a transistor of a semiconductor device capable of increasing the accuracy of ion implantation concentration distribution and increasing the contact margin when forming a DI structure.

Description

Method of manufacturing transistor of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly, to an oxide process for forming a spacer oxide layer for forming a lightly doped drain (LDD) structure in a transistor having a metal-polycide gate structure. The present invention relates to a method for manufacturing a transistor of a semiconductor device, which can suppress the formation of a compound by an abnormal reaction of a metal silicide sidewall, which is a top layer, and can improve electrical characteristics of the device.

In general, gates are formed using metal-polysides instead of polysilicon in order to improve signal processing speeds due to high integration of devices. Tungsten silicide (WSix) is widely used as the metal-silicide.

1 (a) to 1 (c) are cross-sectional views of a device for explaining a transistor manufacturing method having a tungsten-polyside gate structure of a conventional semiconductor device.

Referring to FIG. 1A, after the gate oxide film 2, the polysilicon layer 3, and the tungsten silicide layer 4 are sequentially formed on the semiconductor substrate 1, the tungsten silicide layer 4 and the poly The silicon layer 3 is sequentially patterned by a plasma etching process to form a gate 5 having a tungsten-polyside structure.

The chemical equivalence ratio x of silicon (Si) in the tungsten silicide layer 4 is required to be in the range of 2 to 2.8 in order to improve the oxidation characteristics and increase the adhesive strength with the lower polysilicon layer 3. In the transient silicon in the tungsten silicide layer 4, unstable crystal defects are segregated on the sidewall of the tungsten silicide layer 4 during gate patterning by the plasma etching process. 2 to 4, which is a high resolution transmission electron micrograph after the gate patterning process, and FIG. 3 shows an electron diffraction pattern of the central portion C of the tungsten silicide layer 3 shown in FIG. 2. 4 is a photograph showing an electron diffraction pattern of the edge portion E of the tungsten silicide layer 3 shown in FIG. 2. As shown in FIG. 3, the central portion C which is not damaged by the tungsten silicide layer 3 has a normal crystal structure, and as shown in FIG. 4, the etching damage of the tungsten silicide layer 3 is shown. Received edge portion (E) is changed to an amorphous structure. This results in an unstable state in which the sidewalls of the tungsten silicide layer 3 contain a large number of defects due to the transfer of momentum of the plasma constituent ions to the etching surface during the gate patterning process.

Referring to FIG. 1B, the LED region 6 is formed by the low concentration impurity ion implantation process, the spacer oxide film 7 is formed on the sidewall of the gate 5, and then the source and the drain are formed by the high concentration impurity ion implantation process. The junction 8 is formed, whereby the LED area 6 is determined. The transistor is completed by the above process.

In the oxidation process for forming the spacer oxide film 7, crystal defects are segregated toward the side wall of the tungsten silicide layer 3, and the segregated crystal defects are reacted with the remaining oxygen in the initial stage of the oxidation process to react with the remaining sidewalls of the tungsten silicide layer 3. Since the tungsten-silicon-oxygen (W-Si-O) ternary compound 9 is formed at the side, the tungsten silicide layer 3 sidewall is deformed outward. FIG. 5 is a high resolution transmission electron micrograph showing a state in which compound (9) is formed, and FIG. 6 is a component analysis graph of micro-EDS (energy dispersive spectrometry) for compound (9). In particular, in order to reduce the hot carrier effect and to improve the electrical characteristics of the source and drain junctions, the LED region 6 is formed. The LED region 6 is formed on the sidewall of the tungsten silicide layer 3. Due to the formed compound (9), the topology of the spacer oxide film (7) is abnormally deformed to change the ion implantation concentration distribution portion in the LED area (6). In other words, the intersection 10 of the LED region 6 and the junction 8 is formed to be outward from the desired portion.

Referring to FIG. 1C, after forming the interlayer insulating film 11 on the entire structure including the transistor, the contact hole 12 exposing the junction 8 is formed by etching the selected portion of the interlayer insulating film 11. do. Due to the compound 9 formed on the sidewalls of the tungsten silicide layer 3 when the contact hole 12 is formed, the profile of the contact hole 12 is degraded.

Therefore, the present invention removes crystal defects generated during the etching process for forming the gate of the metal-polyside structure, and thus an abnormal reaction of the metal silicide sidewall, which is an upper layer, during the oxidation process for forming the spacer oxide layer for forming the LED structure. It is an object of the present invention to provide a method for manufacturing a transistor of a semiconductor device capable of suppressing the formation of a compound.

The transistor manufacturing method of the present invention for achieving this object comprises the steps of forming a gate of a tungsten-polyside structure of a polysilicon layer and a tungsten silicide layer laminated on a semiconductor substrate; Performing a low concentration impurity ion implantation process; Heat treatment process to recover crystal defects of the tungsten silicide layer and to form a conductive tungsten-silicon-nitrogen (W-Si-N) coating layer to suppress the production of tungsten-silicon-oxygen (W-Si-O) compounds Performing; Forming a spacer oxide layer on the sidewalls of the gate through an oxidation process and a spacer etching process; And performing a high concentration impurity ion implantation process to form a junction having an LED area.

1 (a) to 1 (c) are cross-sectional views of a device for explaining a transistor manufacturing method having a tungsten-polyside gate structure of a conventional semiconductor device.

2 is a high resolution transmission electron micrograph after a gate patterning process.

3 is a photograph showing an electron diffraction pattern of a central portion of the tungsten silicide layer shown in FIG. 2.

4 is a photograph showing an electron diffraction pattern of the edge portion of the tungsten silicide layer shown in FIG.

5 is a high resolution transmission electron micrograph showing a state in which a W-Si-O compound is formed.

6 is a component analysis graph of micro-EDS for W-Si-O compound.

7 (a) to 7 (c) are cross-sectional views of a device for explaining a transistor manufacturing method having a tungsten-polyside gate structure of a semiconductor device according to an embodiment of the present invention.

8 is a heat treatment and oxidation process diagram for suppressing deformation of the tungsten silicide layer of the present invention.

9 and 10 are transmission electron micrographs showing deformation suppression of a tungsten silicide layer by nitrogen-heat treatment of the present invention.

Explanation of symbols for the main parts of the drawings

1 and 21: semiconductor substrate 2 and 22: gate oxide film

3 and 23: polysilicon layer 4 and 24: tungsten silicide layer

5 and 25: gates 6 and 26: LED regions

7 and 27: spacer oxide films 8 and 28: source and drain junctions

9: W-Si-O Compound 29: W-Si-N Conductive Coating Layer

10: intersection 11 and 31: interlayer insulating film

12 and 32: contact holes

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

7 (a) to 7 (c) are cross-sectional views of devices for explaining a transistor manufacturing method having a tungsten-polyside gate structure of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 7A, after the gate oxide film 22, the polysilicon layer 23, and the tungsten silicide layer 24 are sequentially formed on the semiconductor substrate 21, the tungsten silicide layer 24 and the poly The silicon layer 23 is sequentially patterned by a plasma etching process to form a gate 25 having a tungsten-polyside structure.

As described with reference to FIGS. 1A and 2 to 4, unstable crystal defects are segregated on the sidewalls of the tungsten silicide layer 24 during gate patterning by the plasma etching process.

Referring to FIG. 7B, the LED region 26 is formed by a low concentration impurity ion implantation process. After performing an annealing process under a nitrogen (N ₂ ) atmosphere, a spacer oxide layer 27 is formed on the sidewall of the gate 25 through an oxidation process and a spacer etching process. Thereafter, the source and drain junctions 28 are formed by a high concentration impurity ion implantation process, thereby determining the LED region 26. The transistor is completed by the above process.

The heat treatment process carried out under a nitrogen atmosphere is carried out at the time of the oxidation process for forming the spacer oxide film 27, at the time of patterning the gate 25 at the side wall of the tungsten silicide layer 3 as described with reference to FIGS. 1 (b) and 5. To recover the structural defects formed and to form a tungsten-silicon-nitrogen (W-Si-N) coating layer to prevent the formation of the tertiary compound (9) of tungsten-silicon-oxygen (W-Si-O); to be.

The heat treatment process and the oxidation process for forming the spacer oxide film 27 will be described with reference to FIG. 8 as follows.

The wafer on which the gate 25 is formed is loaded into a chamber maintained at a temperature of 300 to 500 ° C., and the first ramp up process is performed until the nitrogen-heat treatment temperature is 600 to 800 ° C. Conduct. Nitrogen-heat treatment is performed at a temperature of 600 to 800 ° C. for about 15 to 30 minutes to recover unstable crystal defects of the tungsten silicide layer 23, which is a compound generating factor, and to the tungsten silicide layer 23 on the sidewall of the tungsten silicide layer 23. The conductive coating layer 29 of (W-Si-N) is formed to a thickness of 10 to 30 kPa. After the nitrogen-heat treatment, the second ramp-up process is carried out until the oxidation process temperature reaches a temperature of 700 to 850 ° C. An oxidation process for forming the spacer oxide film 27 is performed at a temperature of 700 to 850 ° C. Thereafter, ramp down and unloading processes are performed.

9 and 10 are transmission electron micrographs showing suppression of deformation of the tungsten silicide layer 23 by nitrogen-heat treatment. FIG. 9 is a nitrogen-heat treatment for 15 minutes, and FIG. 10 is a nitrogen-heat treatment for 30 minutes. The state after carrying out an oxidation process afterwards is shown.

Referring to FIG. 7C, after forming the interlayer insulating film 31 over the entire structure including the transistor, the selected portion of the interlayer insulating film 31 is etched to expose the junction 28 having a good shape. ) Is formed.

As described above, in the transistor of the metal-polyside gate structure, the spacer oxide film is formed by performing a heat treatment process under a nitrogen (N ₂ ) atmosphere before the oxidation process for forming the spacer oxide film for forming the LED structure. To suppress the formation of the compound by the abnormal reaction of the upper side of the metal silicide sidewall during the oxidation process, thereby increasing the uniformity of resistance of the metal silicide layer, increasing the accuracy of the ion implantation concentration distribution when forming the LED structure, contact Margins can be increased to improve the device's electrical characteristics and reliability.

Claims (5)

Forming a gate of a tungsten-polyside structure in which a polysilicon layer and a tungsten silicide layer are stacked on a semiconductor substrate; Performing a low concentration impurity ion implantation process; Heat treatment process to recover crystal defects of the tungsten silicide layer and to form a conductive tungsten-silicon-nitrogen (W-Si-N) coating layer to suppress the production of tungsten-silicon-oxygen (W-Si-O) compounds Performing; Forming a spacer oxide layer on the sidewalls of the gate through an oxidation process and a spacer etching process; And A method for manufacturing a transistor of a semiconductor device, comprising: forming a junction having an LED area by performing a high concentration impurity ion implantation process. The method of claim 1, Wherein said heat treatment step and said oxidation step are performed continuously in one chamber. The method according to claim 1 or 2, 15 to 30 minutes in a nitrogen atmosphere at the heat treatment step 600 to 800 ℃ temperature, the transistor manufacturing method of a semiconductor device. The method according to claim 1 or 2, The oxidation process is a transistor manufacturing method of a semiconductor device, characterized in that carried out at a temperature of 700 to 850 ℃. The method of claim 1, The heat treatment process is carried out in a nitrogen atmosphere, the semiconductor device, characterized in that the conductive coating layer of tungsten-silicon-nitrogen (W-Si-N) is formed on the sidewall of the silicide layer to a thickness of 10 ~ 30Å. Transistor manufacturing method.