KR19990060796A - Digital TV receiving decoder device - Google Patents

Abstract

The present invention relates to a video decoder device of a digital TV receiver for compressing and transmitting a video signal and decoding the transmitted compressed video signal in a decoder of a receiver for display

The digital TV receiving decoder apparatus of the present invention divides input block data into a first group of data and a second group of data excluding the first group of data and performs a first downsampling on the first group of data, Second downsampling means for performing second downsampling different from the first downsampling size for the second group of data, motion compensation processing means for performing motion compensation on the downsampled image data, A storage means for storing and outputting the downsampled and motion compensated data; and an output means for outputting the downsampled data of the first group and the data of the second group, By performing different downsampling by dividing information that is not so, it is possible to perform high definition (HD) While reducing the memory at the same time was to ensure a high quality when the reception.

Description

Digital TV receiving decoder device

The present invention relates to a video decoder device of a digital TV receiver for compressing and transmitting a video signal and decoding the transmitted compressed video signal in a decoder of a receiver for display

As a preferred embodiment of the present invention, there is provided a digital TV decoder for receiving an MPEG video signal and decoding the received video signal, the decoder device for receiving an HD class video using an SDTV receiver, And to maintain the picture quality at the best.

The digital TV receiver decodes a video signal compressed and transmitted in MPEG2 in a decoder and displays it on the screen.

Generally, digital TV receivers are divided into HDTV class and SDTV class depending on the number of pixels (pel = picture element) considering factors influencing sharpness / image reproduction performance (picture quality). In the case of HDTV, It has a maximum performance of 1920pels / 1080lines, and for SDTV it has 640pels / 480lines, for example.

FIG. 1 shows an example of a decoder in a digital TV receiver. In FIG. 1, one pixel is represented by 8 bits, one macro block is stored in a data structure of 16 * 16 pixels or pixels, Bit stream. ≪ / RTI >

1, a Variable Length Decoder (VLD) 1 performs variable length decoding on input bitstream data, an IDCT 2 performs Inverse Discrete Cosine Transform on variable length decoded data, The adder 3 stores the reconstructed image in the decoded data by using the motion compensated information of the motion weight information 4 in the frame memory 5 and outputs the reconstructed original image signal to the display means Video out).

Since the HDTV receiver receives and decodes HD-level data, it does not suffer from any problem in receiving and decoding SD-level data.

Since the SDTV receiver receives and decodes the SD-level data, it does not suffer from any problem in receiving and decoding the SD-level data, but it must be able to receive (process) (decode / display) the HD-level data from the viewpoint of compatibility.

For this purpose, the decoder device of the SD class TV receiver performs 'data processing' for SD class reception of HD class data.

We process this data through downsampling, ie filtering / decimation.

FIG. 2 shows a simple example of a down-sampling method of a decoder device for receiving, decoding, and displaying HD-level data in a conventional SD class TV receiver.

2 is a technique for reducing 8 * 8 size data to 4 * 4 size.

The IDCT / downsampler 22 performs inverse discrete cosine transform of the 8 * 8 size data block 21 and downsamples both in the horizontal and vertical directions to reduce it to 4 * 4 size.

As shown in FIG. 4, the image block 401 is subsampled 402 in the horizontal direction to reduce it in the horizontal direction by 1/2, and the image block 401 is again vertically Sampling 404 in the horizontal direction and half in the vertical direction to obtain the downsampled image block 405. [

In FIG. 2, 16 pixels are selected from the upper end of the data block 21 as indicated by a black dot, and rearranged into 4 * 4 to obtain downsampled image data.

The discarded pel except for the selected pel is indicated by a white dot (blank).

Here, the number of selected pixels does not necessarily have to be 16, and there are various other methods for selecting pixels.

The image data down-sampled by 4 * 4 is stored (or may be field memory) in the frame memory 24 via the adder 23.

The image data in the frame memory 24 is upsampled to 8x8 by the upsampler 25 for motion vector processing to adapt the downsampled image data and the upsampled image Data is subjected to motion compensation processing by a motion vector in a motion compensation predictor 26. Since the compensated information is 8 * 8 in size, downsampling in a horizontal / vertical direction is performed again in a 4 * 4 size in the downsampler 27 , And the 4 * 4 downsampling motion processing information is applied to the adder 23 so that finally -8 * 8 is downsampled to 4 * 4-image and outputs it.

The decoder of the conventional digital TV receiver has the following problems.

The downsampling of the HD-level data into the SD-level data is inevitable.

This is because MPEG2 downsamples in horizontal and vertical directions without considering I, P, and B pictures.

That is, uniform downsampling is performed in the horizontal and vertical directions without considering a picture having a large influence on the picture quality of the reproduced picture and a picture not having a large influence on the picture.

Down-sampling in the horizontal and vertical directions causes a total decoding process on the noise components, causing a problem called so-called error drifting.

The I picture or the P picture having the greatest influence on the image reproduction is downsampled with the same specific weight and the chominance and the luminance signal are downsampled with the same specific weight.

The present invention proposes a digital-TV receiving decoder device that downsamples signals of different sizes in consideration of both color signals and luminance signals together with I, P, and B pictures as factors affecting the quality of a reproduced image.

The present invention achieves a higher picture quality improvement in SDTV than in the conventional art by performing downsampling in different sizes in consideration of a picture and a color signal / luminance signal.

The present invention performs downsampling in different sizes in consideration of a picture, a color signal / luminance signal, and bit reduction encoding considering correlation between adjacent pixels for storing downsampled image data, Ensures high image quality while reducing memory size.

1 is a block diagram of a digital television receiver decoder

Figure 2 shows a conventional down-sampling technique in a digital TV receiver decoder

Fig. 3 is a block diagram of the digital TV receiving decoder apparatus of the present invention

4 is a diagram illustrating a sub-sampling method of 2D image data

5 is a diagram showing a vertical / horizontal filtering / decimation method

6 is a diagram illustrating a vertical filtering / decimation method of interlaced scanning image data

7 is a diagram illustrating a filtering / decimation method that does not distinguish between a top field and a bottom field

8 is a diagram showing a filtering / decimation method in the case of distinguishing a top field and a bottom field

The digital TV receiving decoder apparatus of the present invention divides input block data into a first group of data and a second group of data excluding the first group of data and performs a first downsampling on the first group of data, Second downsampling means for performing second downsampling different from the first downsampling size for the second group of data, motion compensation processing means for performing motion compensation on the downsampled image data, Storage means for storing and outputting the downsampled and motion compensated data; and output means for outputting the downsampled data of the first group and data of the second group.

The digital television receiving decoder apparatus according to the present invention comprises first processing means for performing first downsampling on a first group of data selected from data inputted in units of blocks, which is smaller than a second downsampling size, A first storage means for storing data downsampled by a first downsampling size by a processing means; and a second storage means for upsampling and performing motion compensation on original data for motion compensation of the data processed by the first downsampling size First motion vector processing means for down-sampling to a first downsampling size and outputting data compensated for motion of the first downsampled data;

Second processing means for performing a second downsampling on a second group of data other than the first group selected from the data of the input block unit, the second downsampling being larger than a first downsampling size; A first downsampling unit for performing upsampling and motion compensation on original data for motion compensation of data processed by the second downsampling size, and a second downsampling unit for performing downsampling on the downsampled data, A second motion vector processing means for outputting data compensated for the motion of the second downsampled data;

And output means for outputting the motion-compensated final data as decoded data.

At this time, the processing is separated by the first data group processing and the second data group processing.

It will be readily apparent to those skilled in the art that it is possible to have one processing route in the signal processing process without departing from the scope of the present invention.

In the present invention, the first downsampling is M * N, the second downsampling is K * L, where M * N K * L.

In the present invention, the first data group and the second data group are considered as follows for the luminance signal (Y), the color signal (C), and the I, P, and B pictures.

If the first data group is Y, the second data group is C.

If the first data group is IY, PY, the second data group is IC, PC, BY, BC.

FIG. 3 is an embodiment of the digital TV receiving decoder apparatus of the present invention, downsampling the luminance signal I and P pictures to 8 * 4, and downsampling the luminance signal B picture and color signals to 4 * 4.

Hereinafter, the operation of the digital TV receiving decoder device of the present invention will be described with reference to embodiments.

The configuration will be described first.

A first IDCT / downsampling means 31 for performing an IDCT and an 8 * 4 downsampling in the horizontal direction with respect to the IY and PY 32 with the DCT coefficient 30 as an input, A first coder 34 for performing bit reduction encoding of 8 * 4 data output from the first adding means 33, and a second coder 34 for outputting the first coder output A first decoder 36 for decoding the output of the first frame memory 35 and a second decoder 36 for decoding the output of the first decoder 36 into motion vector information 40 A first upsampling means 37 for upsampling in a horizontal direction in consideration of the motion vector information 40 and outputting it as 8 * 8 data; A first motion compensator 38 for processing the output of the first motion compensator 38, First downsampling means (39) for inputting motion compensation information to the motion compensation processing unit (33);

Second IDCT / down-sampling means 41 for performing IDCT and 4 * 4 down-sampling in the vertical and horizontal directions with respect to the BY, IC, PC, BC 42 with the DCT coefficient 30 as input, A second encoder 44 for performing bit reduction encoding of 4 * 4 data output from the second addition means 43, and a second encoder 44 for performing bit reduction encoding of 4 * 4 data output from the second addition means 43, A second decoder 46 for decoding the output of the second frame memory 45; a second decoder 46 for decoding the output of the second decoder 46; A second upsampling means 47 for horizontally / vertically upsampling in consideration of the motion vector information 40 and outputting the resultant as 8 * 8 data, and a second upsampling means 47 for outputting the output of the second upsampling means 47 as motion vector information A second motion compensator 48 for performing motion compensation prediction processing in consideration of the motion vector of the second motion compensator 48, Operating sampled by the second down sampling means (49) for inputting a motion compensation processing information to said adder (43) and;

A third downsampling means 50 for vertically downsampling the 8x4 output of the first decoder 36 to 4x4 and a second downsampling means 50 for outputting the output of the second downsampling means 50 to the second decoder A multiplexer 51 for outputting an output of the video decoder 46 as a final decoded video signal;

.

Hereinafter, the operation of the present invention will be described with reference to Figs. 3 to 8. Fig.

The first IDCT / downsampling means 31 performs inverse discrete cosine transform on the input DCT coefficients 30 and downsamples in the horizontal direction to reduce the size of 8 * 8 to 8 * 4.

Here, downsampling is performed on the luminance I picture IY and the luminance P picture PY, and the 8 * 4 data is input to the first adder 33.

There are many ways to downsample to M * N.

FIG. 4 shows a process of generating a 4 * 4 image block by downsampling the 8 * 8 image block in the horizontal direction and then downsampling the 8 * 8 image block in the vertical direction as described above.

FIG. 5 is a diagram illustrating a process of filtering neighboring pixels among the vertical direction components 5a and 5b of an original macro block to produce eight pixels 5c, which are filtered / Sampling macroblock 5d of the down-sampling macroblock 5d (the same applies to the horizontal direction).

FIG. 6 shows a process of performing downsampling in the vertical direction in the case of interlaced scanning data.

The field DCT macro block 6a is reconstructed (6b) by a top field (black point) and a bottom field (white point) Sampling is performed (at this time, the top field considers an extended pixel), and downsampling is performed through vertical filtering / decimation by reconstructing this into two fields (6e).

7 shows a case where the frame DCT macroblock 7a is reconstructed into two fields after reconstructing a macroblock 7b filtered / decimated without distinguishing the top / bottom fields. FIG. 8 shows a case where a frame DCT macro block 8a is divided into a top field and a bottom field and is reconstructed into two fields (8b).

In addition to the methods described in FIGS. 4 to 8, horizontal down-sampling, vertical down-sampling, and horizontal / vertical down-sampling can be performed in consideration of horizontal direction or vertical direction, or both directions, Or DCT macroblocks in units of fields, and can correspond to whether the top field and the bottom field are distinguished from each other.

The result of performing 8 * 4 horizontal down-sampling on the 8 * 8 IY, PY macroblocks as described above is applied to the first adder 33. [

The output of the first adder 33 is input to the first encoder 34 that performs bit reduction encoding to reduce the amount of bits using the correlation of adjacent pixels in consideration of the capacity limitation of the first frame memory 35.

The amount of bits is reduced to 14 bits by removing 2 samples in consideration of the correlation of adjacent pixels in a horizontal (or vertical) direction on the basis of 8 * 4.

One example of a method for reducing the number of bits is DPCM.

The downsampling data is coded by values of x1 and x2-x1 for horizontal (or vertical) pixels x1 and x2. X1 is an 8-bit value and x2-x1 is a 6 bit value. With an 8-bit value, x2-x1 is encoded with a 6-bit non-uniformly quantized value.

This process can be performed for the second encoder 44 in the same manner.

The data reduced by the DPCM technique is stored in the first frame memory 35 and is decoded by the first decoder 36 through the inverse process of the decoding for image reconstruction (reproduction).

The decoded 8x4 data is upsampled in the horizontal direction by the first sampling means 37 that receives the motion vector information 40 for motion compensation and is output as 8x8 data.

The upsampled 8x8 data is input to the first motion compensator 38 and motion compensated by the motion vector information 40 and the motion compensated information is supplied to the first downsampling means 39 in the size of 8x8 .

The first downsampling means 39 horizontally downsamples the input 8x8 motion compensation information to 8x4 and supplies the resultant to the first adder 33 so that the first IDCT / 4, and outputs the motion compensated I and P picture luminance signals corresponding to the IY and PY data (size) down-sampled by 4.

The 8 × 4 data bit-decoded from the first frame memory 35 is subjected to vertical downsampling to a 4 × 4 size while passing through the third downsampling means 50, (To match BY, IC, PC, and BC down sampled to 4 * 4).

The second IDCT / downsampling means 41 performs inverse discrete cosine transform of the input DCT coefficient 40 and downsamples in the horizontal / vertical direction to reduce the size of 8 * 8 to 4 * 4.

The downsampling is performed on the luminance B picture BY and the color signals IC, PC and BC, and the 4 * 4 data is input to the second adder 43.

The method of downsampling to K * L is shown in FIGS. 4 to 8 above.

The result of performing 4 * 4 horizontal and vertical downsampling on the 8 * 8 BY, IC, PC, and BC macroblocks is applied to the second adder 43 as described above.

The output of the second adder 43 is input to a second encoder 44 that performs bit-reduction encoding by the DPCM technique and takes into account the capacity limitation of the second frame memory 45, Reduce.

The bit reduced data by the DPCM technique is stored in the second frame memory 45 and is decoded by the second decoder 46 through the inverse process of the decoding for image reconstruction (reproduction).

The decoded 4 * 4 data is upsampled in the horizontal / vertical direction by the second sampling means 47 which receives the motion vector information 40 for motion compensation and is output as 8 * 8 data.

The upsampled 8x8 data is input to the second motion compensator 48 and motion compensated by the motion vector information 40 and the motion compensated information is supplied to the second downsampling means 49 in the size of 8x8 .

The second downsampling means 49 horizontally / vertically downsamples the input 8 * 8 motion compensation information to 4 * 4 and supplies it to the second adder 43 so that the second IDCT / downsampling means 41 IC, PC, and BC data corresponding to the data (size) down-sampled by 4 * 4.

The 4 * 4 data bit-decoded from the second frame memory 45 is input to the multiplexer 51, and the third downsampling means 50, and outputs the video signal as a 4 * 4 video signal which is finally downsampled (video out).

According to the present invention, when an HDTV image is received and processed in an SDTV receiver using MPEG2, downsampling can be performed so as to include more information than a picture having a high importance, which affects the quality of a reproduced image, High-quality images can be reproduced.

In addition, by introducing the bit reduction technique, it is possible to provide the SDTV with improved image quality while reducing the size of the memory.

Claims (8)

First downsampling means for performing first downsampling on data of the first group by dividing data of the input block into data of the first group and data of the second group excluding the data of the first group, Second downsampling means for performing a second downsampling different from the first downsampling size for the downsampled image data, motion compensation processing means for performing motion compensation on the downsampled image data, And a storage unit for storing and outputting the digital audio signal. 2. The digital video receiving decoder device according to claim 1, wherein the first downsampling size is M * N and the second downsampling size is K * L, M * N K * L. 2. The digital video receiver decoder of claim 1, wherein the first and second downsampling means are selectively performed by one downsampling means. 3. The digital video reception decoder apparatus according to claim 2, wherein 8 * 4 downsampling is performed on the data of the first group and 4 * 4 downsampling is performed on the data of the second group. The digital TV receiving decoder apparatus according to any one of claims 1 to 4, wherein the first group of data is a luminance signal and the second group of data is a color signal. The method according to any one of claims 1 to 4, characterized in that the data of the first group is the luminance signal of the I and P pictures, and the data of the second group is the luminance signal and the color signal of the color signals of the I and P pictures and the B picture And outputs the received digital audio signal. The digital television receiver according to any one of claims 1 to 4, characterized in that the data of the first group is the luminance and color signals of the I and P pictures, and the data of the second group is the luminance and chrominance signals of the B picture. Device. The apparatus of claim 1, further comprising a bit reduction encoder for reducing the number of bits by considering the correlation of adjacent pixels before storing the motion compensated data in the storage means, and a bit decoder corresponding to bit reduction coding at thrust from the storage means And a decoder for decoding the received digital audio signal.