KR100359824B1 - Apparatus for decoding video and method for the same - Google Patents

Abstract

The present invention relates to a video decoding apparatus and method for reducing external memory of an MPEG-2 decoding chip, which is a standard for digital video transmission. With just enough memory, it is possible to display two or more HD-quality images and various kinds of various SD-quality images simultaneously on one screen. In addition, two HD video signals can be displayed at 1/2 resolution horizontally on one screen without any additional hardware burden. In particular, full resolution motion compensation through up-sampling and down-sampling matrices ensures a very low picture quality.

Description

Apparatus for decoding video and method for the same}

The present invention relates to the field of application of digital television (DTV) or digital video conferencing system, and more particularly, to a video decoding apparatus and method for reducing external memory of an MPEG-2 decoding chip which is a standard in the field of digital video transmission. will be.

Recently, interest in DTV broadcasting is increasing, and efforts are being made to compress and transmit video data so that a high definition clear screen can be viewed by a TV receiver at home. MPEG-2 is mainly used as an algorithm used to compress a video signal.

Thanks to these algorithms, research is being carried out to transmit high-quality digital data, which was previously difficult to handle, to the general broadcasting channel and enjoy it at home. Accordingly, a digital TV receiver needs an MPEG-2 video decoder that must restore the compressed and received data to original high definition video data.

FIG. 1 is a block diagram illustrating a conventional MPEG decoding system. The transport decoder 100 selects a desired program from a plurality of programs included in one channel and separates the packetized audio and video bitstreams. The separated video bit stream is output to the variable length decoder (VLD) 102 through the buffer 101. The VLD 102 decodes the video bitstream by variable length to separate the motion vector, the quantization value, and the discrete cosine transform (DCT) coefficients, and then outputs the motion vector (MV) to the motion compensation unit 106. The DCT coefficients are output to the inverse quantizer (IQ) unit 103. At this time, since the DCT coefficients are coded by a zigzag scan method or an alternate scan method, the IQ unit 103 reverse-scans them by a raster scan method and then quantizes the descanned DCT coefficients. Inverse quantization according to the value is output to the Inverse Discrete Cosine Transform (IDCT) unit 104. The IDCT unit 104 IDCTs the dequantized DCT coefficients in 8x8 block units according to MPEG-2 video syntax and outputs them to the adder 105.

Meanwhile, the motion vector output from the VLD 102 is output to the motion compensator 106, and the motion compensator 106 uses a current pixel value by using the motion vector and the previous frame stored in the memory 108. After performing the motion compensation for the output to the adder 105.

The adder 105 adds the IDCT value and the motion compensated value to reconstruct a complete image which is the final pixel value and outputs the result to a video display processor (VDP) 109. The VDP 109 rearranges and outputs the data according to the picture type or outputs it as it is.

In the case of intra-picture (I-picture), the result of IQ / IDCT is immediately stored in the memory 108, and in the case of predictive picture (P-picture) or bidirectional picture (B-picture), motion compensated data And the IDCT result are added to the adder 105 and then stored in the memory 108.

That is, a video decoder system based on MPEG-2 uses an external memory 108, which consists of a buffer for temporarily storing a bit stream and two or more frame memories. In addition, the frame memory typically uses dynamic RAM (DRAM). In particular, in the case of a video decoder, the role of the external memory 108 may be divided into write and read bit streams for video decoding, read data necessary for motion compensation, write decoded data, and read data to be displayed. And exchange data through the memory interface 107.

However, in order to decode the video data of MPEG-2 MP @ HL, the size of the memory used and the data transfer speed must be increased accordingly. In addition, in the MPEG-2 standard, in order to support the MP @ HL mode, a bit-buffer size of about 10 Mbits is required, and the maximum allowable bit rate reaches about 80 Mbit / s. As a result, the MPEG-2 video decoder based on the existing 16Mbits DRAM requires about 96-128Mbits of external memory. This means higher prices for memory.

Therefore, in order to be competitive in products and consumer applications, there is a need to maintain high image quality while reducing high price memory. In addition, in view of the trend of providing various On Screen Display (OSD) and various services, an additional memory increase is inevitable in the future.

For example, recently, in a video decompression system such as MPEG-2, various types of video signals are decoded and displayed simultaneously, thereby providing various services. In this case, it is necessary to be able to decode several video signals in a limited memory.

After all, considering the limitations of memory, price, and bandwidth of data bus, there is a need for an effective memory reduction device that minimizes the loss of high-definition video signals in video decoding chips. .

In other words, the memory reduction algorithms inherent in the existing video decoding chip suggest an ADPCM (Adaptive Differential Pulse Coded Modulation) method with 50% reduction rate, or VQ (Vector Quantization) with 75% reduction rate. We propose ways to eliminate spatial redundancy. In addition, a compression scheme using filtering / down-sampling schemes in the DCT frequency domain is also proposed.

However, in the case of the ADPCM method described above, since the compressed code is stored in the memory, display using the video display device is difficult. In other words, an apparatus for restoring the compressed code again must be added.

On the other hand, as a method for simultaneously displaying HD signals inputted to a decoder of one chip, using a down conversion algorithm, displaying two HD images on one screen or displaying several SD images on one HD image. I need a way. This requires algorithms and hardware (H / W) design with good image quality and fast throughput.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video decoding apparatus and method for displaying a plurality of HD and SD classes on one screen while reducing memory and maintaining good image quality.

1 is a block diagram of a general video decoding apparatus

2 is a block diagram illustrating a video decoding apparatus according to the present invention.

3 is a detailed block diagram of FIG.

4 is a diagram illustrating a processing process of an 8x4 IDCT unit of FIG. 3;

FIG. 5 is a block diagram illustrating a motion compensation process through up / down sampling of FIG. 2.

6 illustrates a downsampling and IDCT process of the present invention.

7 illustrates an upsampling and IDCT process of the present invention.

8 is a diagram illustrating a pixel structure in motion compensation through upsampling according to the present invention.

9A and 9B show examples of various display modes.

Explanation of symbols for main parts of the drawings

201: Buffer 202: VLD

203: IQ part 204: IDCT part

205: Adder 206: Upsampling unit

207: motion compensation unit 208: down sampling unit

209: memory interface 210: memory

211: horizontal up sample filter 212: video display processor

In the video decoding apparatus according to the present invention for achieving the above object, in the compression mode to reduce the input bitstream again, 8xM (M = M) after removing high frequency components by 1 / L in the horizontal direction with respect to dequantized data. 8 / L) an IDCT unit for performing IDCT, a memory for storing the addition result of the IDCT data or the IDCT data and the motion compensated data, and a horizontal upsampling of the reference picture read from the memory in a horizontal direction. A motion compensator for performing motion compensation using an up-sampling unit, a full resolution motion vector output from the VLD for a picture up-sampled in the horizontal direction from the horizontal up-sampling unit, and a motion compensation unit in the motion compensating unit. Horizontal down sampling down-sampling data in the horizontal direction and then storing it back in memory in addition to the IDCT data It characterized in that the lead to the data stored in the memory in accordance with a ring portion and a display mode comprises a video display processing section to output to the display device.

The horizontal down sampling unit converts an 8x8 block into an 8x4 block using a matrix of DCT bases.

The horizontal up sampling unit converts an 8x4 block into an 8x8 block by using a matrix of DCT bases.

The video display processing unit may further include an upsampling filter for performing upsampling filtering in a horizontal direction with respect to data read from the memory when the video display processor wants to increase the reduced image back to a desired resolution.

In the video decoding method according to the present invention, in the compression mode for reducing the input bitstream again, the high frequency component is removed in the horizontal direction with respect to the inversely quantized 8x8 DCT coefficient and 8x4 IDCT is performed. When using a resolution motion vector, horizontal upsampling is performed before motion compensation and horizontal downsampling is performed after motion compensation.

The present invention displays two or more HD video signals encoded in high definition or HD and several SD video signals on a screen using only a limited memory and one video decoding chip.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating an MPEG-2 video decoder having a 50% memory reduction down conversion according to the present invention, wherein an IDCT unit 204 and a motion compensator 207 that perform 8x4 IDCT in the compression mode. A horizontal up sampling unit 206 configured to upsample the data read from the memory 210 in the horizontal direction, and a horizontal down sampling unit which down-samples the motion-compensated data in the horizontal direction and outputs it to the adder 205 ( 208 is further included in FIG. 1 described above.

FIG. 3 is a block diagram illustrating the down-conversion part of FIG. 2 in more detail, and operates in a compression mode and a normal mode. This operation is performed by the control signal COMP switching the switching of each switching unit 204-1, 206-2, 208-1.

That is, in the normal mode (COMP = 0), the 8x8 IDCT unit 204-2 is selected through the switching unit 204-1, and the data stored in the memory 210 moves through the switching unit 206-2. The motion compensation data is directly output to the compensator 207, and the motion compensated data is directly output to the adder 205 through the switching unit 208-1.

On the other hand, in the compression mode (COMP = 1), the 8x4 IDCT unit 204-3 is selected through the switching unit 204-1, and the data stored in the memory 210 is uploaded by the up sampling unit 206-1. After sampling, the output is output to the motion compensator 207 through the switching unit 206-2, and the motion compensated data is input to the down sampling unit 208-2 through the switching unit 208-1 and down sampled. It is then output to the adder 205.

Here, for convenience of description, a case in which the inputted bitstream is reduced again to display two or more HD-quality images or multiple HD- and SD-level images simultaneously on one screen is referred to as a compression mode. The case where only the inputted bitstream is decoded for normal display is called normal mode.

In this case, referring to the operation of the 8x4 IDCT unit 204-3, in the compression mode (COMP = 1), DCT coefficients X (IJ) corresponding to high frequency components in the horizontal direction among the 8x8 IDCT coefficients as shown in FIG. IDCT only for the remaining 8x4 DCT coefficients with I = 1, ..., 8, J = 5, ..., 8) removed. As a result, only the low frequency components are restored, which loses the information about the sharpness in the image, that is, the detail edge or the text of the image. In general, however, natural images are mostly aggregated with signals for a low frequency region, so that the image quality is not significantly impaired. Therefore, the result of 8x4 IDCT shows the effect of using a low frequency band filter on the image, and the size of the image stored in the external memory 210 is reduced in half. In the end, you get a 50% reduction in memory.

In the normal mode (COMP = 0), the full resolution video is decoded like the conventional MPEG-2 video decoder of FIG. 1. That is, the 8x8 IDCT 204-2 performs 8x8 IDCT on the 8x8 IDCT coefficients.

Meanwhile, in the case of the MPEG-2 video decoder, the video encoder reproduces a block of the current frame from the previous frame using a full resolution motion vector (MV) to obtain a motion compensated frame.

Therefore, the present invention uses a full resolution motion vector rather than scaling down the horizontal motion vector in order to improve image quality at the time of motion compensation.

In the compression mode, since the picture having the 1/2 resolution in the horizontal direction is stored in the memory 210, an upsampling process is required to increase the picture to the original resolution. In addition, a down sampling process is required to reduce the original resolution obtained after motion compensation back to half resolution. That is, in the compression mode, the data stored in the memory 210 is upsampled in the horizontal direction by the upsampling unit 206-1 and then output to the motion compensation unit 207 through the switching unit 206-2, and the motion compensation is performed. The data is again input to the down sampling unit 208-2 through the switching unit 208-1, downsampled in the horizontal direction, and then output to the adder 205.

5 shows a motion compensation scheme operating in the compression mode. That is, the address generator 500 generates a read address of the reference memory 210 according to the motion vector and the field selection signal to read the reference frame necessary for motion compensation from the memory 307. The horizontal upsampling filter of the horizontal upsampling unit 206 reads the reference pixels of the read address from the memory 210, upsamples them in the horizontal direction, and outputs them to the motion compensator 207 for half pel interpolation. -pel interpolation). The half pel interpolated data is input to the down sampling filter of the horizontal down sampling unit 208 and down sampled in the horizontal direction.

At this time, the image quality greatly depends on the properties of the up sampling filter of the horizontal up sampling unit 206 and the down sampling filter of the horizontal down sampling unit 208.

The up sampling / down sampling filter scheme used in the present invention uses matrices composed of DCT basis.

Before describing the matrices, the nature of the DCT is described first.

That is, an 8x8 2-D (Dimension) DCT case is represented by Equation 1 below.

Here, f denotes an 8x8 image block, F denotes a coefficient block DCTed to f, and C ₈ denotes an 8x8 DCT base matrix.

The 8x8 2-D IDCT case is represented by Equation 2 below.

The 8x4 2-D IDCT case is represented by Equation 3 below.

here, And C ₄ represents a 4 × 4 DCT base matrix.

In this case, when Equation 1 is added to Equation 3 and solved, Equation 4 is as follows.

Where P ₄ = Defines an 8x4 dimension as a downsampling matrix and converts an 8x8 block into an 8x4 block. 6 shows a down sampling process in the DCT region.

On the other hand, the up-sampling method converts an 8x4 block into an 8x8 block by the inverse transform using the following equation. The process in the DCT region is shown in FIG. 7.

That is, 8x4 2-D DCT can be obtained from Equation 3 as shown in Equation 5 below.

The result of 8x8 2-D IDCT using Equation 2 can be obtained as shown in Equation 6 below.

As a result, Equation 6 is expressed by the following equation.

In addition, Equation 7 may be obtained as in Equation 8 below from the inverse transform of Equation 4.

Where Q ₄ is a pseudo-inverse transformation of P ₄ , to be.

At this time,

Using the relation, the equation (8) satisfies the following equation (9).

Equation 7 shows a process of up-sampling a 1/2 resolution image stored in the memory 210 in units of blocks in the horizontal up sampling unit 206.

That is, the horizontal up sampling unit 206 obtains a motion compensation block after reproducing the macro block corresponding to the original resolution by using the up sampling matrix. At this time, if there is half-pel interpolation in the horizontal direction or the full-resolution motion vector (MV) does not fall by a multiple of 8, as shown in FIG. Get blocks. N represents the length of the vertical direction of the block to be motion compensated. If half-pel precision is used in the vertical direction, a block of (N + 1) × 4 units is taken from the memory 210. Then, for the three blocks, the full resolution block is reconstructed using the up-sampling matrix as derived from Equation 7 above. After that, the motion compensation unit 207 performs half pel interpolation on the region corresponding to the full resolution motion vector to obtain a motion compensated block that we want.

The motion-compensated Nx16 block is down-sampled again by the horizontal down sampling unit 208 to add to the result of 8x4 IDCT as shown in FIG. 3. That is, Nx16 blocks are converted into Nx8 blocks using the down sampling matrix of Equation 4. The block thus obtained is stored in the memory 210 again through the MB adder 205 of FIG.

Reduced-resolution pictures of the memory 210 are displayed on the screen via the VDP 212 according to various display modes. In particular, two or more HD signals can be obtained even with limited memory when multi-decoding multiple video sources. In addition, various types of screens may be configured as shown in FIG. 9 by combining with HD / SD level signals input through an external input. In this case, if the reduced image is to be restored to full resolution again, the horizontal upsample filter 211 performs upsampling filtering in the horizontal direction and then outputs it to the VDP 212. Here, the size of the restored screen may vary depending on the degree of upsampling filtering.

In addition, the number of HD and SD screens that may be displayed on one screen may vary depending on the capacity of the memory 210.

In addition, when the above-described down sampling and up sampling processes are applied to the vertical direction, the effect of the 75% memory reduction rate can be obtained. In this case, the number of HD and SD screens that can be displayed on one screen is further increased.

On the other hand, the upsampling filter 211 for obtaining a full resolution picture from the reduced resolution picture is different from the horizontal upsampling unit 206 used in the motion compensation scheme in various forms such as an n-tap FIR filter or an IIR filter. It can be implemented. At this time, the use of a high-performance filter can increase the sharpness of the image quality.

As described above, the present invention can be applied to MPEG-2 HDTV MP @ HL decoder chip, which is an essential technology for application fields such as digital TV or video video conferencing, and can be applied to multiple decoding or multiple screens. The high-performance video decoder that can receive and screen video, and strengthen the technological competitiveness of other companies' digital TV.

As described above, according to the video decoding apparatus and method according to the present invention, a 50% memory reduction rate is obtained by using a down conversion algorithm, and two or more HD video and It is possible to display various kinds of SD-quality images on one screen at the same time. In addition, two HD video signals can be displayed at 1/2 resolution horizontally on one screen without any additional hardware burden. In particular, full resolution motion compensation through up-sampling and down-sampling matrices ensures a very low picture quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (10)

A video decoding apparatus which reconstructs an input video bitstream to a pixel value of an original screen through variable length decoding (VLD) and then through inverse quantization (IQ), inverse discrete cosine transform (IDCT), and motion compensation (MC). To An IDCT unit for performing 8x4 IDCT after removing 1/2 of the high frequency component in the horizontal direction with respect to the dequantized data in the compression mode for reducing the input bitstream again; A memory for storing an addition result of the IDCT data or the IDCT data and motion compensated data; A horizontal upsampling unit configured to upsample a reference picture read from the memory in a horizontal direction; A motion compensation unit for performing motion compensation on the picture up-sampled in the horizontal direction by the horizontal up sampling unit by using a motion vector having a full resolution output from the VLD; A horizontal down sampling unit which down-samples the motion compensated data by the motion compensation unit in a horizontal direction and stores the motion compensated data in the memory in addition to the IDCT data; And And a video display processor for reading data stored in the memory and outputting the data stored in the memory to a display device according to a display mode. The method of claim 1, wherein the horizontal down sampling unit And a 8x8 block is converted into an 8x4 block using a matrix of DCT basis. The method of claim 1, wherein the horizontal up sampling unit And a 8x4 block is converted into an 8x8 block using a matrix of DCT basis. The method of claim 1, wherein the horizontal up sampling unit If there is half pel interpolation in the horizontal direction or the full resolution motion vector does not fall by multiples of eight, then three blocks of Nx4 units in the horizontal direction (where N is the vertical length of the motion compensated block) are read from the memory. A video decoding apparatus characterized by using for motion compensation after upsampling in a horizontal direction. The method of claim 1, wherein the horizontal up sampling unit When half pel precision is used in the vertical direction, a block of (N + 1) × 4 units (where N is the length of the vertical direction of the block to be compensated for) is read from the memory, upsampled in the horizontal direction, and used for motion compensation. A video decoding device. The display apparatus of claim 1, wherein the video display processor is used. And an upsampling filter for horizontally upsampling and filtering the data read from the memory when the reduced image is again increased to a desired resolution. In the video decoding method of reconstructing the input video bitstream to the pixel value of the original screen through a variable length decoding (VLD) and then through an inverse quantization (IQ) process, an inverse discrete cosine DCT process, and a motion compensation (MC) process , Performing 8x4 IDCT after removing the high frequency component in the horizontal direction with respect to the dequantized data in the compression mode of reducing the input bitstream again; Storing an addition result of the IDCT data or the IDCT data and motion compensated data in a memory; Upsampling a reference picture read from the memory in a horizontal direction; Performing motion compensation on the upsampled picture in the horizontal direction using a full-resolution motion vector that is variable-length decoded and output; Down-sampling the motion-compensated data in the horizontal direction and storing the motion-compensated data in the memory in addition to the IDCT data; And And reading the data stored in the memory according to a display mode and outputting the data to a display device. delete The method of claim 7, wherein the horizontal down sampling process A video decoding method characterized by converting an 8x8 block into an 8x4 block by applying the following matrix. Where P ₄ = Defines an 8x4 dimension as the downsampling matrix, f denotes an 8x8 image block, C ₈ denotes an 8x8 DCT basis matrix, And C ₄ represents a 4x4 DCT base matrix. The method of claim 7, wherein the horizontal upsampling process A video decoding method characterized by converting an 8x4 block into an 8x8 block by applying the following matrix. Where Q ₄ is the pseudo-inverse transformation of P ₄ .