KR100734549B1 - Apparatus and method for fast decoding for multi-channel digital video recorder - Google Patents

Abstract

Disclosed are a high speed decoding apparatus for a multichannel DVR system, and a method thereof. The variable length decoding unit decodes the input quantized DCT transform coefficients and outputs the decoded bitstream. The inverse quantization unit inverse quantizes and outputs a variable length decoded bitstream. The inverse discrete cosine transform scaler selects a block of the second size of the low frequency region corresponding to the predetermined resolution conversion ratio in the DCT region of the adjacent first size block inputted from the inverse quantization unit, and selects a block of the selected second size block. Inverse discrete cosine transform is performed to convert the resolution. According to the present invention, lower complexity can be achieved while maintaining almost the same image quality as compared with the case of performing the resolution conversion based on the DCT area based on the pixel area based resolution conversion.

Description

High speed decoding apparatus and method for multichannel DVB system {Apparatus and method for fast decoding for multi-channel digital video recorder}

1 is a view showing the structure of a general DVR system,

Figure 2a is a block diagram showing the configuration of the monitoring image generating apparatus in the conventional DVR system, Figure 2b is a block diagram showing the detailed configuration of the monitoring image generating apparatus for each channel shown in Figure 2a,

3 is a block diagram showing a detailed configuration of a preferred embodiment of a high speed decoding apparatus for a multi-channel DVR system according to the present invention;

4 is a diagram illustrating a principle of resolution conversion performed by the selective inverse discrete cosine transform unit 334.

5 is a diagram illustrating a motion compensation process for resolution conversion when one macroblock in a prediction frame is in 8 × 8 mode;

6 is a flowchart illustrating a preferred embodiment of a fast decoding method for a multi-channel DVR system according to the present invention when the input image is an intra frame;

7 is a flowchart illustrating a preferred embodiment of a fast decoding method for a multi-channel DVR system according to the present invention when the input image is a predictive frame;

FIG. 8 illustrates a case where the resolution is reduced to a size of 176 × 144 by bilinear method after decoding a hall monitor image having a CIF (352x288) size in a conventional video decoder and high-speed decoding for a multi-channel DVR system according to the present invention. A graph showing the CPU time consumed when the resolution is converted after decoding the video signal by the apparatus and method, and

9 and 10 are diagrams illustrating result images of an intra frame and a prediction frame, respectively.

The present invention relates to a high speed decoding apparatus and a method thereof, and more particularly, to a high speed decoding apparatus and method for a multi-channel DVR system.

DVR (Digital Video Recorder) system is a device that converts analog video signals of multiple channels input to surveillance cameras into digital video signals and then stores, plays back and retrieves digital video using video compression technology. The DVR system provides a function to remotely monitor and control necessary video using a network when a user needs it. The DVR system can store video signals semi-permanently in the storage device, manage the storage device easily, and enable users to receive streaming services in real time, thus speeding up the AVR (Analog Video Recorder). It's replacing with speed.

1 is a view showing the structure of a general DVR system.

Referring to FIG. 1, a general DVR system includes a plurality of video cameras 110-1 through 110-n, a video encoder 120, a video decoder 130, a video mux 140, a monitor 150, and a storage device ( 160). Video decoder 130, video mux 140, and monitor 150 configure monitoring system 170. The video cameras 110-1 to 110-n acquire an image and provide the image to the video encoder 120. The video encoder 120 encodes an image of each channel input from the video cameras 110-1 to 110-n and then transmits the image to the monitoring system 170 through the channel. The video decoder 130 decodes a bit string of each encoded channel received through the channel and provides the decoded bit string to the video mux 140. The video mux 140 multiplexes the decoded image input through each channel and outputs the multiplexed image to at least one of the monitor 150 and the storage device 160. The monitor 150 outputs the multiplexed image to the user in real time, and the storage device 160 stores the bit string received from the video mux 140.

In the conventional DVR system shown in FIG. 1, in order to monitor the decoded image of each channel through one screen, a multiplexing process is performed by the video mux 140. For this purpose, the input bit string of each channel is decoded. You must then convert the resolution of the image. In general, the complexity of the calculations applied for resolution conversion increases in proportion to the number of channels. At this time, the delayed phenomenon occurs in the display process of the image due to the increased complexity, which is an obstacle to real-time monitoring of the image.

FIG. 2A is a block diagram illustrating a configuration of a monitoring image generating apparatus in a conventional DVR system, and FIG. 2B is a block diagram illustrating a detailed configuration of the monitoring image generating apparatus for each channel shown in FIG. 2A.

2A and 2B, each video decoder 200-1 to 200-n decodes a bitstream input from a corresponding channel. In order to perform the resolution conversion based on the pixel area, the video decoders 200-1 to 200-n must first reconstruct an image of the discrete cosine transform area into an image of the pixel area. The video decoders 200-1 to 200-n include a variable length decoder 205, an inverse quantizer 210, an inverse discrete cosine converter 215, a frame memory 220, a motion compensator 225, and an adder 230. It is provided.

A variable length decoder (VLD) 205 performs entropy decoding on quantized DCT transform coefficients and outputs a decoded bitstream. An inverse quantizer (IQ) 210 inverse quantizes image data quantized by a quantizer of a video encoder (not shown). The inverse discrete cosine transformer 215 performs an inverse discrete cosine transform operation on the image data inversely quantized by the inverse quantizer 210. The video decoders 200-1 to 200-n should include an IDCT module for reconstructing a signal of a DCT region to obtain an image of one pixel region.

In general, MPEG-4 is widely used as a video standard of DVR system. Since IDCT is performed in 8x8 blocks and all blocks of one frame, the IDCT module occupies a high ratio in the complexity of the decoder. DCT in 8x8 block units is represented by the following equation.

Here, A is an 8x8 block to perform DCT, H _8x8 is a DCT matrix of size 8x8. A DCT 8x8 block of A in the pixel region may be represented by A ^* . Block A ^* DCT applied to Equation 1 in the video encoder undergoes an IDCT process in order to reconstruct the pixel region in the video decoders 200-1 to 200-n. IDCT performed in the video decoders 200-1 to 200-n is represented by the following equation.

Here, A ^* is an 8x8 block to perform IDCT, and H ^* _8x8 is an IDCT matrix of size 8x8. An IDCT 8x8 block of A ^* in the pixel region may be represented by A.

Block A, which has undergone the IDCT process, is information reconstructed into an image of a pixel region, and the inverse discrete cosine converter 215 performs ICDT on all 8x8 blocks in one image to reconstruct one image. The complexity of the video decoders 200-1 to 200-n for each channel of the DVR system is greatly affected by the IDCT process, which takes up a relatively high amount of computation.

The frame memory 220 stores image data inverse discrete cosine transformed by the inverse discrete cosine transformer 215 in units of frames. The motion compensator (MC) 225 performs motion compensation on a block basis with respect to the image data stored in the frame memory 220. The adder 230 adds and outputs the motion compensated image data by the motion compensator 225 and the inverse discrete cosine transformed image data by the inverse discrete cosine transformer 215. The frame memory 220, the motion compensator 225, and the adder 230 are provided when a video signal composed of predictive frames is input to the video decoders 200-2 to 200-n.

The pixel-based scalers 250-1 to 250-n are connected to the rear ends of the respective video decoders 200-1 to 200-n. The pixel-based scalers 250-1 to 250-n convert the resolution of the decoded bitstreams input from the image decoders 200-1 to 200-n corresponding to the pixel base. The pixel-based scalers 250-1 through 250-n include a low pass filter 255 and a scaler 260. The low pass filter 255 removes aliasing by preprocessing an image frame input from the video decoders 200-1 to 200-n, and the scaler 260 performs a bilinear method or a cubic, which is an interpolation method in the pixel region. The resolution of the image frame is converted and output by convolution. The video mux 270 multiplexes and outputs the bitstream whose resolution is converted by the pixel-based scalers 250-1 to 250-n. In this case, since a low pass filter 255, a scaler 260, and the like perform convolution operations for converting the resolution of an image, a large amount of computation is required. Consequently, these modules convert resolution in each channel. Much complexity is required. In addition, in the case of a DVR system using multiple channels, the complexity of the discrete cosine converter, the low pass filter, the scaler, and the like increases in proportion to the number of channels, thus increasing the complexity of the overall DVR system.

An object of the present invention is to provide an apparatus and method which can decode an image at high speed by reducing the complexity of resolution resolution of an image performed by a decoding apparatus applied to a multi-channel DVR system.

The technical problem to be solved by the present invention is to reduce the complexity of the resolution conversion of the image performed in the decoding apparatus applied to the multi-channel DVR system computer to record a program for executing a method to decode the image at high speed To provide a recording medium that can be read by.

In order to achieve the above technical problem, a high speed decoding apparatus for a multi-channel DVR system according to the present invention includes: a variable length decoding unit for decoding input quantized DCT transform coefficients and outputting a decoded bitstream; An inverse quantizer for inversely quantizing and outputting the variable length decoded bitstream; And selecting a second size block of a low frequency region corresponding to a predetermined resolution conversion ratio in a DCT region of an adjacent first size block inputted from the inverse quantization unit, and performing an inverse discrete cosine for the selected second size block. And an inverse discrete cosine transform scaler for performing the transform to convert the resolution.

According to another aspect of the present invention, there is provided a fast decoding method for a multi-channel DVR system, the method comprising: decoding a quantized DCT transform coefficients and outputting a decoded bitstream; Dequantizing the variable length decoded bitstream; Selecting a block of the second size of the low frequency region corresponding to a predetermined resolution conversion ratio in the DCT region of the dequantized adjacent first size block; And converting the resolution by performing an inverse discrete cosine transform on the selected block of the second size.

Thus, by converting the resolution in the pixel area based on the DCT area in the still image or video interworking module, it is possible to maintain the same image quality as the resolution conversion method based on the existing pixel area and obtain a gain in terms of complexity to implement an efficient DVR system. This is possible.

Hereinafter, exemplary embodiments of a high speed decoding apparatus and method for a multichannel DVR system according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing a detailed configuration of a preferred embodiment of a high speed decoding apparatus for a multi-channel DVR system according to the present invention.

Referring to FIG. 3, the fast decoding apparatus 300 for a multi-channel DVR system according to the present invention includes a variable length decoding unit 310, an inverse quantization unit 320, an inverse discrete cosine transform scaler 330, and a frame memory. The unit 340, the motion compensation unit 350 and the adder 360 is provided.

A variable length decoder (VLD) 310 performs entropy decoding on the quantized DCT transform coefficients and outputs a decoded bitstream. An inverse quantization unit (IQ) 320 inversely quantizes image data quantized by a quantizer of a video encoder (not shown). The inverse discrete cosine transform scaler 330 performs inverse discrete cosine transform and resolution transform on the image data dequantized by the inverse quantizer 320. The inverse discrete cosine transform scaler 330 performs a low pass filtering and a resolution conversion process in the DCT region instead of performing an operation for converting the resolution after completely restoring the image of the DCT region to the pixel region. Can reduce the complexity.

The inverse discrete cosine transform scaler 330 includes a block reconstruction unit (not shown) and an optional inverse discrete cosine transform unit (not shown). The block reconstruction unit (not shown) selects a 4x4 size block in the low frequency region from the DCT region of the adjacent 8x8 block and reconstructs it into one 8x8 block. When the resolution of the input image is reduced to ½, the block reconstruction unit (not shown) reconstructs four adjacent 8x8 blocks into one 8x8 block. An 8x8 block composed of DCT coefficients is defined by the following equation.

Here, A ^* ₁₁ , A ^* ₁₂ , A ^* ₂₁ , and A ^* ₂₂ are 4x4 size sub-matrixes of the DCT coefficient matrix A ^* of 8x8 block size. The equation applied to perform 4 × 4 IDCT only in the low frequency region without considering the high frequency region may be expressed as follows.

Where A _S is a 4 × 4 block in which 8 × 8 block A is reduced to ½ size, m is a normalization variable (eg, 2) according to the difference between the 4 × 4 DCT coefficient and the 8 × 8 DCT coefficient, and A ^* ₁₁ is an 8x8 size block in the DCT region and a DCT coefficient of a 4x4 size block located in the low frequency region of A ^* , and H _4x4 is a matrix for 4x4 IDCT.

The selective inverse discrete cosine transforming unit 334 considers only the 4 × 4 size of the low frequency region in the 8 × 8 DCT region to reduce the original resolution to 1/2 for the 4 × 4 block size region. Perform IDCT. 4 illustrates a principle of resolution conversion performed by the selective inverse discrete cosine transform unit 334. Referring to FIG. 4, due to the energy concentration principle of the low frequency path of the DCT, in each block 410 to 440, the average size of the low frequency signal is positioned at the first position 412 in the DCT region, and the remaining position 414. The magnitudes of the high frequency signals are located at. The selective inverse discrete cosine transforming unit 334 converts the image into the image signal on the pixel domain based on the average size of the low frequency signals constituting each 8x8 block existing on the DCT domain by equation (4). This method is similar to applying the low pass filter in the existing pixel region by ignoring the high frequency region and considering only the low frequency region. In addition, by applying 4 × 4 IDCT, it is possible to construct a 4 × 4 pixel area image, and consequently, it is possible to effectively perform resolution conversion on the input image at ½.

Meanwhile, when a prediction frame is input to the high speed decoding apparatus 300 for a multi-channel DVR system according to the present invention, a motion compensation process is performed on the input prediction frame. To this end, the high speed decoding apparatus 300 for a multi-channel DVR system according to the present invention includes a frame memory unit 340, a motion compensator 350, and an adder 360.

The frame memory unit 340 stores the image data inverse discrete cosine transformed and resolution-converted by the inverse discrete cosine transform scaler 330 in units of frames. The motion compensator (MC) 350 performs motion compensation on a block basis with respect to the image data stored in the frame memory unit 340. In this case, the motion compensator 350 selectively performs IDCT on blocks of 4x4 size in the low frequency region corresponding to the resolution conversion ratio (that is, ½) in an 8x8 size error signal composed of adjacent DCT coefficients. After performing the motion compensation, the motion compensation is performed by adding the adjacent 4 × 4 reference blocks extracted from the image data corresponding to the block to which the resolution conversion is performed among the decoded image data stored in the frame memory unit 340.

The adder 360 adds and outputs the image data motion-compensated by the motion compensator 350 and the image data inverse discrete cosine transformed and resolution-converted by the inverse discrete cosine transform scaler 330. Motion compensation is performed by a method of adding an error signal obtained through IDCT to a reference block in a reference frame obtained by using the decoded motion vector. The motion compensation process can be represented by the following equation.

Here, P is an 8x8 block generated after the motion compensation process, R is a reference block obtained using a motion vector, and E ^* is an 8x8 error signal composed of DCT coefficients.

In this case, the same inverse discrete cosine transform scaling method used in the intra frame is applied to efficiently convert the magnitude of the error signal E ^* of the prediction frame to ½. Since the reference frame, which is just the frame on the time axis, is a half-size image from which a low frequency region is removed, it may be assumed that motion compensation is easily performed for resolution conversion in the same manner. Therefore, E ^* corresponding to the error signal obtained by Equation 5 can be represented by the following equation having the same form as Equation 3.

Here, E ^* ₁₁ , E ^* ₁₂ , E ^* ₂₁ , and E ^* ₂₂ are 4x4 size sub-matrix of the DCT coefficient matrix E ^* of 8x8 block size. Equation (5) applied to recover the error signal E _S of the pixel region converted into the ½ size of the error signal E ^* represented by Equation 6 may be represented by the following equation having the same form as Equation (4).

Here, E _S is a 4 × 4 block in which 8 × 8 block A is reduced to ½ size, m is a normalization variable (eg, 2) according to the difference between the 4 × 4 DCT coefficient and the 8 × 8 DCT coefficient, and E ^* ₁₁ is an 8x8 block in the DCT region and is a DCT coefficient of a 4x4 block located in the low frequency region of E ^* .

In addition, in order to obtain the reference block, since the resolution of the reference frame is converted to ½ size, the size of the motion vector must be reduced. For example, assuming that the decoded motion vector for the original resolution is MV _O , the motion vector MV _S for the resolution converted to ½ size can be expressed by the following equation.

The motion prediction of one macro block in the MPEG-4 encoder is determined as an advantageous mode among 16x16 mode and 8x8 mode. This is one of the ways in which the MPEG-4 encoder can increase the compression rate in the encoding process. Corresponding to this coding scheme in macroblock units for MPEG-4, the motion compensation process in the decoder should be made in units of 16x16 blocks or 8x8 blocks. Therefore, considering that the resolution of the reference frame has been converted to ½, the motion compensation unit 350 included in the fast decoding apparatus for the multi-channel DVR system according to the present invention is 16 × using MV _S obtained by Equation (8). In the 16 mode, the motion compensation is performed in 8 × 8 size, and in the 8 × 8 mode, the motion compensation is performed in 4 × 4 block units. For example, if a reference block of 4x4 size obtained by MV _S is R _S , the motion compensation process may be finally expressed by the following equations (5) and (7).

Here, P _S is a 4 × 4 size block generated after the motion compensation process.

FIG. 5 is a diagram illustrating a motion compensation process for resolution conversion performed by the above-described method when one macroblock in a prediction frame is in 8 × 8 mode. If one macro block is in 16 × 16 mode, ¹ MV _S = ² MV _S = ³ MV _S = ⁴ MV _S and other processes are applied in the same manner as when one macro block is in 8 × 8 mode.

6 is a flowchart illustrating a preferred embodiment of a fast decoding method for a multi-channel DVR system according to the present invention when the input image is an intra frame.

Referring to FIG. 6, the variable length decoding unit 310 performs entropy decoding on input quantized DCT transform coefficients and outputs a decoded bitstream (S600). The inverse quantization unit 320 inversely quantizes the bitstream input from the variable length decoding unit 310 (S610). The block reconstruction unit 332 selects a 4x4 size block in the low frequency region from the DCT region of the adjacent 8x8 block and reconstructs it into one 8x8 block (S620). In order to reduce the original resolution to 1/2, the selective inverse discrete cosine transform unit 334 selectively performs IDCT on the 4 × 4 blocks of the low frequency region in the 8 × 8 DCT region (S630). .

7 is a flowchart illustrating a preferred embodiment of a fast decoding method for a multi-channel DVR system according to the present invention when the input image is a predictive frame.

Referring to FIG. 7, the variable length decoding unit 310 performs entropy decoding on input quantized DCT transform coefficients and outputs a decoded bitstream (S700). The inverse quantization unit 320 inversely quantizes the bitstream input from the variable length decoding unit 310 (S710). The block reconstruction unit 332 selects a 4x4 size block in the low frequency region from the DCT region of the adjacent 8x8 block and reconstructs it into one 8x8 block (S720). In order to reduce the original resolution to 1/2, the selective inverse discrete cosine transform unit 334 selectively performs IDCT on 4 × 4 blocks of a low frequency region in an 8 × 8 DCT region (S730). . The motion compensator 350 selectively performs IDCT on 4 × 4 blocks of a low frequency region in an 8 × 8 size error signal composed of adjacent DCT coefficients, and then decodes the data stored in the frame memory unit 340. The motion compensation is performed by adding the adjacent 4x4 sized reference blocks (S740).

The resolution converter method based on the existing pixel region restores the image signal on the pixel region through IDCT in the decoder and performs the resolution conversion on the image signal in the pixel region. When the conventional resolution conversion method is applied to a multi-channel DVR system, the complexity of the system increases greatly. On the contrary, the high speed decoding apparatus and the resolution converting method applied to the method for the multi-channel DVR system according to the present invention completely apply the resolution conversion algorithm in the pixel region having a large amount of computation after completely recovering the signal of the DCT region to the pixel region. The computation amount can be greatly reduced in that resolution conversion can be performed in the DCT region without the need. In addition, when the resolution is converted by applying the resolution converter method in the DCT region, an image having almost the same image quality as the image obtained by converting the resolution by the bilinear method may be obtained. This is because the high speed decoding apparatus for the multi-channel DVR system and the resolution converter method applied to the method according to the present invention perform a performance similar to that for the resolution conversion in the pixel region in the DCT region to restore the image. For this reason, when the resolution converter method applied to the present invention is applied to a multi-channel DVR system, it may exhibit higher efficiency in terms of complexity and image quality than processing in a conventional pixel area.

FIG. 8 illustrates a case where the resolution is reduced to a size of 176 × 144 by a bilinear method after decoding a Hall monitor image having a CIF (352x288) size in a conventional video decoder and high-speed decoding for a multi-channel DVR system according to the present invention. It is a graph showing the CPU time consumed when the resolution is converted after decoding the video signal by the apparatus and method.

Referring to FIG. 8, the case where the resolution is changed by the high speed decoding apparatus and method for the multi-channel DVR system according to the present invention is less than that when the resolution is converted in the pixel region after decoding the image by a conventional video decoder. 2 times faster operation speed This is because the conventional decoding method performs 8 × 8 DCT operation, while the decoding method by the fast decoding apparatus and method for the multi-channel DVR system according to the present invention performs 4 × 4 DCT operation and performs resolution conversion in the pixel region. This is because the operation is not performed separately. In addition, assuming that the experimental result shown in FIG. 7 is a complexity when the resolution conversion is applied after decoding in one channel, in the conventional pixel area when the resolution converter method according to the present invention is applied to a multi-channel DVR system, It can be seen that a significant gain in complexity can be obtained by applying the resolution conversion technique of.

9 and 10 are diagrams illustrating result images of an intra frame and a prediction frame, respectively. 9 and 10 are decoded by a resolution converter applied to a decoded image without resolution conversion, a decoded image by the bilinear method, and a high speed decoding apparatus for a multi-channel DVR system according to the present invention. It is a video. As can be seen from each result image, when the fast decoding apparatus and method according to the present invention are used for resolution conversion of intra frame and prediction frame, the performance is similar to that of applying the bilinear method, which is a resolution conversion technique, in the pixel region. It can be seen. As a result, when the high speed decoding apparatus and method according to the present invention is applied to a multi-channel DVR system, it can be seen that the complexity of the system can be greatly reduced without reducing image quality.

The present invention can also be embodied as computer readable code on a computer readable recording medium and implemented as a chip. In particular, when implemented as a chip, there is an advantage of maintaining the computational consistency compared to other fast motion estimation algorithms. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage device, and also carrier waves (for example, transmission over the Internet). It also includes the implementation in the form of. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

Although the preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific preferred embodiments described above, and the present invention belongs to the present invention without departing from the gist of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such changes are within the scope of the claims.

According to the fast decoding apparatus and method for a multi-channel DVR system according to the present invention, by performing a resolution conversion in the DCT region without performing a resolution conversion in the pixel region, the difference between the image and the image quality obtained by the conventional bilinear method While few images can be obtained, the complexity of the system can be greatly reduced, resulting in an efficient DVR system.

Claims (9)

A variable length decoding unit to decode input quantized DCT transform coefficients and output a decoded bitstream; An inverse quantizer for inversely quantizing and outputting the variable length decoded bitstream; And In the DCT region of the adjacent first sized block input from the inverse quantizer, a second sized block of the low frequency region corresponding to a predetermined resolution conversion ratio is selected, and an inverse discrete cosine transform is performed on the selected second sized block. Includes; an inverse discrete cosine transform scaler for converting the resolution; The inverse discrete cosine transform scaler performs a resolution conversion on each of adjacent blocks of a second size by the following equation:

Here, A _S is a block obtained by converting the block A of the first size to a second size corresponding to the resolution conversion ratio, m is a normalization variable according to the difference between the DCT coefficient of the second size and the DCT coefficient of the first size, A ^* ₁₁ is the DCT coefficient of the block of the second size located in the low frequency region of the block of the first size of the DCT region, and H _4x4 is a matrix for the IDCT of the second size. delete A variable length decoding unit to decode input quantized DCT transform coefficients and output a decoded bitstream; An inverse quantizer for inversely quantizing and outputting the variable length decoded bitstream; In the DCT region of the adjacent first sized block input from the inverse quantizer, a second sized block of the low frequency region corresponding to a predetermined resolution conversion ratio is selected, and an inverse discrete cosine transform is performed on the selected second sized block. An inverse discrete cosine transform scaler for converting the resolution by performing a transform; A frame memory unit for storing the decoded image data in units of frames; And In the decoded image data stored in the frame memory unit after IDCT is selectively performed on the second sized blocks of the low frequency region corresponding to the resolution conversion ratio in the error signal of the first size composed of adjacent DCT coefficients. And a motion compensator configured to perform motion compensation by summing with the adjacent second size reference blocks extracted from the image data corresponding to the blocks of the second size. The motion compensation unit for a high speed decoding apparatus for a multi-channel DVR system, characterized in that for performing the motion compensation for the block of the second size by the following equation:

, Here, P _S is a block of the second size generated after motion compensation, R _S is a reference block of the second size, m is a normalization variable according to the difference between the DCT coefficient of the second size and the DCT coefficient of the first size, E ^* ₁₁ is a DCT coefficient of the error signal of the second magnitude located in the low frequency region of the error signal of the first magnitude in the DCT region, and H _4x4 is a matrix for IDCT of the second magnitude. A variable length decoding unit to decode input quantized DCT transform coefficients and output a decoded bitstream; An inverse quantizer for inversely quantizing and outputting the variable length decoded bitstream; In the DCT region of the adjacent first sized block input from the inverse quantizer, a second sized block of the low frequency region corresponding to a predetermined resolution conversion ratio is selected, and an inverse discrete cosine transform is performed on the selected second sized block. An inverse discrete cosine transform scaler for converting the resolution by performing a transform; A frame memory unit for storing the decoded image data in units of frames; And In the decoded image data stored in the frame memory unit after IDCT is selectively performed on the second sized blocks of the low frequency region corresponding to the resolution conversion ratio in the error signal of the first size composed of adjacent DCT coefficients. And a motion compensator configured to perform motion compensation by summing with the adjacent second size reference blocks extracted from the image data corresponding to the blocks of the second size. The inverse discrete cosine transform scaler performs a resolution conversion on each of adjacent blocks of a second size by the following equation:

, Here, A _S is a block obtained by converting the block A of the first size to a second size corresponding to the resolution conversion ratio, m is a normalization variable according to the difference between the DCT coefficient of the second size and the DCT coefficient of the first size, A ^* ₁₁ is the second size located in the low frequency region of the first size block of the DCT region. The DCT coefficients of the block, and H _{4 × 4,} are matrices for the IDCT of the second size. Decoding the input quantized DCT transform coefficients and outputting a decoded bitstream; Dequantizing the variable length decoded bitstream; Selecting a block of the second size of the low frequency region corresponding to a predetermined resolution conversion ratio in the DCT region of the dequantized adjacent first size block; And Converting the resolution by performing an inverse discrete cosine transform on the selected block of the second size; The resolution conversion step is a high-speed decoding method for a multi-channel DVR system, characterized in that for performing the resolution conversion for each of the adjacent blocks of the second size by the following equation:

Here, A _S is a block obtained by converting the block A of the first size to a second size corresponding to the resolution conversion ratio, m is a normalization variable according to the difference between the DCT coefficient of the second size and the DCT coefficient of the first size, A ^* ₁₁ is the DCT coefficient of the block of the second size located in the low frequency region of the block of the first size of the DCT region, and H _4x4 is a matrix for the IDCT of the second size. delete Decoding the input quantized DCT transform coefficients and outputting a decoded bitstream; Dequantizing the variable length decoded bitstream; Selecting a block of the second size of the low frequency region corresponding to a predetermined resolution conversion ratio in the DCT region of the dequantized adjacent first size block; Converting the resolution by performing an inverse discrete cosine transform on the selected block of the second size; Storing the decoded image data in units of frames; And After the IDCT is selectively performed on the second sized blocks of the low frequency region corresponding to the resolution conversion ratio in the error signal of the first size composed of adjacent DCT coefficients, the second size among the stored decoded image data. And performing motion compensation by summing with the adjacent second sized reference blocks extracted from the image data corresponding to the blocks of? The motion compensation step is a high speed decoding method for a multi-channel DVR system, characterized in that for performing the motion compensation for the block of the second size by the following equation:

, Here, P _S is a block of the second size generated after motion compensation, R _S is a reference block of the second size, m is a normalization variable according to the difference between the DCT coefficient of the second size and the DCT coefficient of the first size, E ^* ₁₁ is a DCT coefficient of the error signal of the second magnitude located in the low frequency region of the error signal of the first magnitude in the DCT region, and H _4x4 is a matrix for IDCT of the second magnitude. Decoding the input quantized DCT transform coefficients and outputting a decoded bitstream; Dequantizing the variable length decoded bitstream; Selecting a block of the second size of the low frequency region corresponding to a predetermined resolution conversion ratio in the DCT region of the dequantized adjacent first size block; Converting the resolution by performing an inverse discrete cosine transform on the selected block of the second size; Storing the decoded image data in units of frames; And After the IDCT is selectively performed on the second sized blocks of the low frequency region corresponding to the resolution conversion ratio in the error signal of the first size composed of adjacent DCT coefficients, the second size among the stored decoded image data. And performing motion compensation by summing with the adjacent second sized reference blocks extracted from the image data corresponding to the blocks of? The resolution conversion step is a high-speed decoding method for a multi-channel DVR system, characterized in that for performing the resolution conversion for each of the adjacent blocks of the second size by the following equation:

, Here, A _S is a block obtained by converting the block A of the first size to a second size corresponding to the resolution conversion ratio, m is a normalization variable according to the difference between the DCT coefficient of the second size and the DCT coefficient of the first size, A ^* ₁₁ is the second size located in the low frequency region of the first size block of the DCT region. The DCT coefficients of the block, and H _{4 × 4,} are matrices for the IDCT of the second size. A computer-readable recording medium having recorded thereon a program for executing a high speed decoding method for a multi-channel DVR system according to any one of claims 5, 7 and 8.

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