KR100323676B1 - Apparatus for receiving digital moving picture - Google Patents

Abstract

The present invention relates to a digital video receiver for downconversion of an interlaced scanning sequence in a digital television (DTV) or digital video conferencing system application. In particular, if the received DCT block is a field DCT coded block, the sample is down sampled as it is, and the frame DCT coded block is used. By converting to a field DCT coded block, down-sampling it, storing it in memory, and compensating for motion prediction, the video decoder has a down converter for HD interlaced scanning sequences. You can get SD screen with good image quality.

Description

Digital video receiving device {Apparatus for receiving digital moving picture}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital television (DTV) or digital videoconferencing system applications, and more particularly to an apparatus for receiving digital video for downconversion of interlaced sequences.

Recently, interest in DTV broadcasting is increasing, and efforts are being made to compress and transmit video data so that a high definition clear screen can be viewed by a TV receiver at home. MPEG-2 is mainly used as an algorithm used to compress a video signal.

Thanks to these algorithms, research is being carried out to transmit high-quality digital data, which was previously difficult to handle, to the general broadcasting channel and enjoy it at home. Therefore, the digital TV receiver must restore the compressed and received data to the original high definition video data, and an MPEG-2 video decoder is required for this purpose.

As illustrated in FIG. 1, the digital TV receiver employing the MPEG-2 video decoder, when an audio / video (A / V) multiplexed bitstream is input, the transport demultiplexer 101. Separates the multiplexed audio and video bitstreams. The separated audio bitstream and the video bitstream are output to the audio decoder 102 and the video decoder 104 for decoding. Herein, the audio bitstream and the video bitstream are packetized elementary streams (PES).

At this time, the audio decoder 102 restores the input audio bitstream to an original signal using an MPEG algorithm or an audio coding (AC) -3 algorithm or the like, and uses a digital / analog converter (DAC) ( 103 converts it into an analog form and outputs it to a speaker.

In addition, the video decoder 104 removes overhead (various header information, start codes, etc.) from the input video bitstream, decodes the pure data information by variable length, and then performs inverse quantization and inverse discrete cosine conversion. The pixel value of the original screen is restored, and the video display processor 105 converts it to a display format and outputs it to the display device.

FIG. 2 is a detailed block diagram of the MPEG video decoder 104 in which the video bit stream separated by the transport demultiplexer 101 is a variable length decoder (VLD) 202 through a buffer 201. ) Is entered. The VLD 202 variably decodes the video bitstream to separate the motion vector, the quantization value, and the discrete cosine transform (DCT) coefficients, and then outputs the motion vector (MV) to the motion compensator 206. The DCT coefficient is output to the inverse quantizer (IQ) unit 203. In this case, since the DCT coefficients are coded by a zig-zag scan method or an alternate scan method, the IQ unit 203 performs a reverse scan on the raster scan method and then quantizes the descanned DCT coefficients. Inverse quantization according to the value is output to the inverse discrete cosine transform (IDCT) unit 204. The IDCT unit 204 IDCTs the inverse quantized DCT coefficients in 8x8 block units according to MPEG-2 video syntax and outputs them to the adder 205.

Meanwhile, the motion vector output from the VLD 202 is output to the motion compensator 206, and the motion compensator 206 uses a current pixel value by using the motion vector and a previous frame stored in the memory 208. After performing the motion compensation for the output to the adder (205).

The adder 205 adds the IDCT value and the motion compensated value to reconstruct the complete image which is the final pixel value and outputs the result to the video display processor 209. The VDP 209 rearranges the data according to the picture type and outputs the data as it is.

In the case of intra-picture (I-picture), the result of IQ / IDCT is immediately stored in the memory 208, and motion-compensated data in the case of predictive picture (P-picture) or bidirectional picture (B-picture). And the IDCT result are added in the adder 205 and then stored in the memory 208.

That is, a video decoder system based on MPEG-2 uses an external memory 208, which is composed of a buffer for temporarily storing a bit stream and two or more frame memories. In addition, the frame memory typically uses dynamic RAM (DRAM). In particular, in the case of a video decoder, the role of the external memory 208 can be divided into write and read bit streams for video decoding, read data necessary for motion compensation, write decoded data, and read data to be displayed. And exchange data through the memory interface 207.

However, in order to decode the video data of MPEG-2 MP @ HL, the size of the memory used and the data transfer speed must be increased accordingly. In addition, in the MPEG-2 standard, in order to support the MP @ HL mode, a bit-buffer size of about 10 Mbits is required, and the maximum allowable bit rate reaches about 80 Mbit / s. As a result, the MPEG-2 video decoder based on the existing 16Mbits DRAM requires about 96-128Mbits of external memory. This means higher prices for memory.

Therefore, in order to be competitive in products and consumer applications, there is a need to maintain high image quality while reducing high price memory. In addition, in view of the trend of providing various On Screen Display (OSD) and various services, an additional memory increase is inevitable in the future.

For example, recently, in a video decompression system such as MPEG-2, various types of video signals are decoded and displayed simultaneously, thereby providing various services. In this case, it should be possible to decode several video signals in limited memory.

After all, considering the limitations of memory, price, and bandwidth of data bus, there is a need for an effective memory reduction device that minimizes the loss of high-definition video signals in video decoding chips. .

In other words, the memory reduction algorithms inherent in the existing video decoding chip suggest an ADPCM (Adaptive Differential Pulse Coded Modulation) method with 50% reduction rate, or VQ (Vector Quantization) with 75% reduction rate. We propose ways to eliminate spatial redundancy. In addition, a compression scheme using filtering / down-sampling schemes in the DCT frequency domain is also proposed.

However, in the case of the ADPCM method, since the compressed code is stored in the memory, display using the video display device is difficult. In other words, an apparatus for restoring the compressed code again must be added. In addition, the 75% reduction in ADPCM results in a significant loss of quality, which is not suitable for video decoders.

On the other hand, HD (high definition) signals input to the video decoder of the one chip using a down conversion algorithm can simultaneously display several HD-quality images or several SD-quality images on one screen. These methods can maintain some good image quality despite the large amount of memory savings. In addition, the present invention can be applied to a low-cost decoder for a low resolution display device. This requires down conversion algorithms and hardware (H / W) designs with good image quality and low memory.

On the other hand, in general, the MPEG encoder encodes progressive or interlaced sequences. Here, the sequence of images obtained by sequential scanning is called a sequential scanning sequence, and the sequence of images obtained by interlaced scanning is called an interlaced scanning sequence.

In this case, the interlaced picture is encoded as a field picture or a frame picture. In other words, a field picture is separated into fields and encoded in a field unit, and a frame picture is encoded in a frame unit.

In the case of the field picture, one picture consists of odd lines of scan lines, the other picture consists of even lines of scan lines, and the operation of all encoders and decoders is performed in units of fields. Therefore, 8x8 DCT (discrete cosine transform) blocks are composed of only odd field (odd fidld) or even field (even field). This is called a field DCT coded block.

In contrast, in the case of interlaced frame pictures, each picture is formed by combining odd lines and even lines of a scanning line. Therefore, macro blocks of a frame picture have both odd fields and even fields.

At this time, the macro blocks of the frame picture may be coded in two different ways. Four 8x8 DCT transformed blocks in a macro block (i.e. 16x16) are frame DCT coded blocks, each having odd and even lines, the other two blocks in the macro block consist of only the odd lines of the macro block, and the other two The dog block is a field DCT coded block consisting of only even lines. That is, the frame DCT coded block divides the macro block into four blocks as shown in FIG. 3A, and then performs DCT for each 8x8 block. The field DCT coded block is divided into two fields after dividing into two fields for each field as shown in FIG. 3B. To DCT.

In addition, the macroblocks of the field picture are all coded with field DCT, and motion compensation prediction is performed from a reference field at the time of motion compensation. However, macro blocks of a frame picture are coded with frame DCT / field DCT, and motion compensation prediction can be performed in units of frames, or motion compensation prediction can be performed in units of fields. In the case of sequential scanning sequences, all pictures are coded with frame DCT and frame prediction is performed.

Since HDTV display devices are expensive and not many, there is a need to display high-definition HD-quality video sequences at a reduced resolution through existing NTSC TVs. At this time, viewers should be able to view HDTV signals without buying expensive HDTV display devices. Such a device is called a down converting decoder. The result is a much cheaper TV than a full HDTV resolution.

One such scheme is disclosed in US Pat. No. 5,262,854. The disclosed US patent has a down sampler that eliminates 48 high frequency DCT coefficients in an 8x8 block. The IDCT results of the remaining 4x4 blocks of the low frequency components are stored in the memory. Therefore, when the motion compensation prediction error is reduced by using the full resolution motion vector when the motion compensation is used, it is used based on the reduced resolution screen. As a result, an up-sampling method is used to make the reduced resolution a full resolution picture.

In addition, several efficient methods for reducing the motion compensation error by up-sampling downsampled pictures using 4x4 IDCT are proposed (R. Morky and D. Anastassiou, 'Minimul error drift in Frequency scalability for motion-compensated DCT coding, '' IEEE Trans.On Circuit and System for Video Tech., Vol. 4, August 1994. Johnson and Princen, 'Drift minimization in frequency scalable coders using block based filtering,' IEEE Workshop on Visual Signal Processing and Communication, September 1993.) It became.

The methods proposed above typically use two-dimensional filters with five or eight taps, depending on the predicted motion vector of the macroblock. At this time, the positions of the values of the 8-tap filter change according to the motion vector. Thus, one 8-tap filter increases 4 pixels to 8 pixels.

However, while the schemes described above are suitable for sequential scanning sequences with frame DCT coded blocks, problems with images mixed with frame / field DCT coded blocks are not addressed. As a result, in the case of interlaced sequences input to most MPEG-2 video decoders, there is a problem in the loss of upsampling and downsampling in the vertical direction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a digital video receiving apparatus for displaying an HD signal of the interlaced scanning sequence on a low-definition screen of SD class while maintaining memory reduction and good image quality. have.

1 is a block diagram of a general digital TV receiver

2 is a detailed block diagram of the MPEG video decoder of FIG.

3A and 3B show a frame DCT and a field DCT process

4 is a block diagram of an MPEG video decoder according to the present invention;

5 is a detailed block diagram of FIG.

6A and 6B illustrate pixel structures of a field-based reference picture and a frame-based reference picture after downsampling in a DCT region.

FIG. 7 is a detailed block diagram of the IDCT and down sampling unit of FIG. 4. FIG.

FIG. 8 is a block diagram showing a motion compensation process through up / down sampling of FIG.

9 is a block diagram showing an example of up / down sampling used for the motion compensation of FIG.

10 illustrates an example of vertical interpolation of a bottom field after downsampling in a DCT region.

Explanation of symbols for main parts of drawings

301: Buffer 302: VLD

303: IQ unit 304: adaptive IDCT unit

305: Adder 306: Upsampling unit

307: motion compensation unit 308: down sampling unit

309: memory interface 310: memory

311: video display processor

According to an aspect of the present invention, there is provided a digital video receiving apparatus comprising: a video bitstream extractor for separating and extracting a bitstream including a video signal; and the extracted video bitstream is an interlaced scanning sequence and a frame DCT. In the case of the coded block, it is down-converted while being converted to the field DCT coded block, and in the case of the field DCT coded block, it is down-converted as it is, and stored in a memory.

The video processor performs variable length decoding and inverse quantization on the input video bitstream, and if the inversely quantized DCT coefficient is field DCT data of an interlaced sequence, the video processor removes the DCT coefficient of the high frequency component in the horizontal / vertical direction and then performs 4x4 inverse discrete cosine. IDCT is performed, and if the data is frame DCT, DCT coefficients of high frequency components are removed in the horizontal direction, converted to field DCT data, and vertical downsampling is performed in the DCT conversion region.

The video processor performs upsampling filtering in the vertical / horizontal direction on the data read from the memory before motion compensation and downsampling in the vertical / horizontal direction after the motion compensation when the full resolution motion vector is used for the motion compensation. It is characterized by.

The digital video receiving apparatus according to the present invention removes the DCT coefficient of the high frequency component in the horizontal / vertical direction if the inverse quantized DCT coefficient is the field DCT data of the interlaced scan sequence, and if the DCT coefficient is the frame DCT data, the digital video receiver receives the 4x4 IDCT. An IDCT unit which removes the DCT coefficient of the component, converts it into a field DCT IDCT coefficient, and downsamples in the vertical direction in the DCT transform region, and stores an addition result of the IDCT data or the IDCT data and motion compensated data A vertical / horizontal upsampling unit for upsampling a reference picture read from the memory in the vertical / horizontal direction, and a vertical / horizontal upsampling unit for up-sampling the vertical / horizontal upsampling unit from the VLD A motion compensator for performing motion compensation using a full resolution motion vector, and the motion compensator A vertical / horizontal downsampling unit which down-samples the motion compensated data in the vertical / horizontal direction and stores the motion-compensated data in the memory in addition to the IDCT data, and outputs the data stored in the memory to the display device according to the display mode. And a video decoding unit comprising a video display processing unit.

The IDCT unit is a horizontal reduction unit for removing high frequency component DCT coefficients in the horizontal direction when the frame DCT coded block of the interlaced scan sequence, a frame / field converter for converting the frame DCT coded block into a field DCT coded block, and a vertical direction. The matrix multiplier outputs the IDCT coefficients of the down-sampled field structure, and the horizontal IDCT performs IDCT in the horizontal direction on the output data of the matrix multiplier.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, if the received DCT block is a field DCT coded block, it is downsampled, and if the frame DCT coded block is converted to a field DCT coded block, downsampled and stored in a memory and compensated for motion prediction.

FIG. 4 is a block diagram of an MPEG-2 video decoder having down conversion for 75% memory reduction proposed in the present invention, in which IDCT is performed differently according to whether a macro block to be input is a field DCT coded block or a frame DCT coded block. The up-sampler 306 provided in front of the IDCT and the down-sampler 304 and the motion compensator 307 to up-sample the data read from the memory 310 in the horizontal / vertical direction, and again the motion-compensated data. The down sampling unit 308 for down sampling in the vertical direction and outputting to the adder 305 is further included in FIG. 2.

That is, the bitstream parsed through the VLD 302 is stored in the external memory 310 via the IQ unit 303, the IDCT unit 304, and the motion compensation unit 307. The stored image is displayed on the screen via a video display processor (VDP) 312.

FIG. 5 is a block diagram illustrating the down-conversion portion of FIG. 4 in more detail, so that the memory has a field structure.

However, as shown in FIGS. 6A and 6B, the result of down sampling the frame DCT coded block and the field DCT coded block in the DCT conversion region has a different pixel structure.

In the present invention, a field-based reference picture is always set regardless of a received DCT type. To this end, when the frame DCT coded block is input, the field DCT coded block is converted to perform IDCT and down sampling.

That is, DCT coefficients parsed from the VLD 302 are input to the IQ unit 303, dequantized, and then transmitted to the IDCT unit 304.

In this case, the VLD 302 provides a dct_type (frame or field) and picture_structure (frame picture or field picture) together. In addition, the VLD 302 provides motion vectors (MVs), motion type (motion_type), and field selection signals (motion_vertical_ field_select) to the motion compensator 307.

On the other hand, the operation of the IDCT unit 304 is the same as FIG.

That is, in the case of the field DCT macroblock, DCT coefficients X (I, J) corresponding to high frequency components in the vertical / horizontal direction among the 8 × 8 IDCT coefficients (X (I, J), I = 5, ..., 8, J = 5,. Remove .., 8) and IDCT in the vertical / horizontal direction only for the remaining 4x4 DCT coefficients. This restores only low-frequency components, and loses sharpness, that is, information about the detail edges or text of an image. In general, most natural images are agglomerated with signals for the low frequency region, so that the image quality is not significantly impaired. Therefore, the result of 4x4 IDCT shows the effect of using the low frequency band filter on the image, and finally, the size of the image stored in the external memory 310 is reduced by 1/4. The result is a 75 percent reduction in memory.

In the case of a frame DCT block, first, the block is transformed into field DCT blocks, and then downsampled in the DCT transform to be IDCT. The output of the IDCT unit 304 always has a field-based vertical structure as shown in FIG. 6, and the output of the IDCT unit 304 is input to the macro block (MB) adder 305.

At this time, the IDCT unit 304 converts the frame DCT block into a field DCT block and IDCT in the vertical direction is expressed by Equation 1 below.

Here, [X] represents two vertical blocks having eight frame DCT coefficients.

In this case, the 8x8 DCT base matrix is represented by Equation 2 below.

That is, [T8] represents an 8x8 DCT base matrix of 8-point DCT bases.

At this time, the IDCTs for the two vertical blocks are represented by a matrix as shown in Equation 3 below.

As a result, the result of IDCT of [X] is expressed by the following expression (4).

Here, [x] represents two vertical blocks in pixel units.

The DCT matrix for converting a frame into a field is expressed by Equation 5 below.

here, Denotes the i th 8 point DCT basis vector.

In this case, Equation 5 rearranges the 8-point DCT basis vector in the column direction of the matrix of Equation 2 to the top / bottom to separate the top / bottom from the frame DCT block. That is, in the matrix of Equation 5, the upper side arranges one 8 point DCT basis vector one by one to the top, and the lower side arranges one eight point DCT basis vector one by one to the bottom.

Therefore, multiplying the frame DCT block by Equation 5 results in a DCT result in field units as shown in Equation 6 below. That is, it is the same as DCT of top / bottom separately.

Here, [x] is arranged in frame order, and [Xtb] represents two field DCT coded blocks for the top field and the bottom field.

Therefore, the frame DCT coefficients [X] are expressed by the following equations as the field DCT coefficients [Xtb] through the following operation.

[Xtb] = [T _f ] [x] = [T _f ] [IT8 ₂ ] [X]

As a result, the down sampling method of the DCT transform region is a result of IDCT after removing high frequency components in the vertical / horizontal direction of field DCT coefficients. Therefore, [Xtb] is 4x4 IDCT using the following operators.

First, suppose that a 4x4 DCT matrix made of a 4-point DCT basis similar to Equation 2 is [T4]. The downsampling process of IDCT after removing high frequency components in the horizontal and vertical directions is expressed by Equation 8 below.

Here, [P4] is expressed by the following equation (9).

The down-sampled IDCT coefficient for [Xtb] of Equation 7 is expressed as Equation 10 below.

Here, [IP4 ₂ ] is a down-sampling matrix of field DCT coded coefficients, and is represented by Equation 11 below.

Using the equations (7) and (10), the frame DCT coefficient [X] is converted into the field DCT coefficient and the pixels [ytb] in the unit of the down-sampled field are obtained as shown in Equation 12 below.

[ytb] = [Q] [X] = [IP4 ₂ ] [T _f ] [IT8 ₂ ] [X]

Where [Q] = [IP4 ₂ ] [T _f ] [IT8 ₂ ] operates only on vertical DCT coefficients in an 8x16 matrix.

Now let's look at the macroblock, that is, four 8x8 DCT blocks (X1, X2, X3, X4).

First, in the case of the field DCT in FIG. 7, 4x4 IDCT may be performed in the vertical and horizontal directions of blocks X1 ', X2', X3 ', and X4' from which high frequency components in the vertical and horizontal directions are removed. That is, the field DCT macro block is input to the first reduction unit 401, and the frame DCT macro block is input to the second reduction unit 405. In this case, the first reduction unit 401 may include DCT coefficients X (I, J) corresponding to high frequency components in the vertical / horizontal direction among 8 × 8 IDCT coefficients of the field DCT macroblocks X1, X2, X3, and X4. Vertical IDCT unit 402 only for the remaining 4x4 DCT coefficients (X1 ', X2', X3 ', X4') after removing), I = 5, ..., 8, J = 5, ..., 8) IDCT is performed in the vertical direction by inputting), and is output to the horizontal IDCT unit 404 through the selection unit 403 to perform IDCT in the horizontal direction.

Referring to the case of the frame DCT in FIG. 7, the second reduction unit 405 first includes DCT coefficients corresponding to high frequency components in the horizontal direction among 8x8 IDCT coefficients of the frame DCT macroblocks X1, X2, X3, and X4. After removing X (I, J), I = 1, ..., 8, J = 5, ..., 8, only the remaining 8x4 DCT coefficients (X1 ', X2', X3 ', X4') Output to converter 406. The field converter 406 converts the frame DCT block into a field DCT block having a top / bottom division as shown in Equation 7 and outputs the same to the matrix multiplier 407. The matrix multiplier 407 obtains IDCT coefficients down-sampled in the vertical direction, that is, blocks G1 ', G2', G3 ', and G4', which are downsampled in the vertical direction using the [Q] matrix of Equation 12. The blocks are temporarily stored and delayed by the storage and delay unit 408, and then input to the horizontal IDCT unit 404 through the selection unit 403 to be 4x4 IDCT in the horizontal direction. That is, the pixels x1 ', x2', x3 ', and x4' of the field-based vertical structure may be finally obtained with respect to the frame DCT block. Here, (x1 ', x2') represents a top field block, and (x3 ', x4') represents a bottom field block.

In this case, in the case of the intra (I) picture, the result of passing through the IDCT unit 304 is immediately stored in the memory 310. In the case of a P or B picture, motion prediction compensated blocks are added to the adder 305 and stored in the memory 310.

In general, a video encoder reproduces a block of a current frame from a previous frame using a full resolution motion vector (MV) to obtain a motion compensated frame.

Therefore, the present invention also uses a full-resolution motion vector rather than scaling down the vertical / horizontal motion vector in order to improve image quality in motion compensation.

At this time, in order to use the full resolution motion vector, an up-sampling process of restoring the reduced reference picture in the memory 310 to the original resolution is required. In addition, a down sampling process is required to reduce the original resolution obtained after motion compensation back to 1/4 resolution.

8 shows a motion compensation scheme operating during down-conversion.

As described above, the memory 310 stores pictures of a field-based vertical structure. In addition, the horizontal / vertical upsampling unit 306 selects a field corresponding to the motion vector during motion compensation, reads the field reference signals reduced from the memory 310, and then upsamples the respective fields in the horizontal / vertical direction. do.

In this case, as shown in FIG. 8, motion compensation may be divided into frame prediction and field prediction according to a motion type.

That is, during field prediction compensation, the address generator 501 reads the reference block of the corresponding field by sending a read address to the reference memory 310 using the motion vector and the respective motion_vertical_field_select signal. At this time, the horizontal / vertical up-sampler 502 and 503 upsample the blocks of each field in the vertical / horizontal direction, and the half pel interpolator 506 of the motion compensator 307 and 504 to the up-sampled blocks. Half pel interpolation constitutes a motion compensated block. The horizontal / vertical down sampling units 502 and 503 downsample the motion-compensated blocks for each field unit and output the down-sampled blocks to the macro block adder 305.

Meanwhile, in the case of frame prediction compensation, the address generator 501 sends a read address to the reference memory 310 using a motion vector and each motion_vertical_field_select signal to read a reference block in units of fields. In this case, the vertical / horizontal upsampling filters 502 and 503 upsample the top field and the bottom field in the vertical / horizontal direction, respectively, and then combine one frame block with one frame block from two fields. That is, the up-sampled blocks of each field constitute a reference block in frame units. The half pel interpolator 506 configures a motion-compensated block by half-pel interpolation on the frame predicted block and outputs the motion-compensated block to the field separator 507. The field separator 507 separates the motion compensated frame block into respective fields, and then down-samples the horizontal and vertical down sampling units 502 and 503 to output them to the macro block adder 305.

Here, the address generator 501 receives motion vectors (MVs), motion type (motion_type), and field selection signals (motion_vertical_ field_select) from the VLD 302, and provides corresponding signals where necessary, and provides a reference memory 310. Generates a read address. The data of the read address is read from the reference memory 310 and then input to the horizontal up sample / down sample filter 504 as a reference pixel for prediction.

At this time, the image quality greatly depends on the properties of the up / down sampling filters 502 and 503 of the up / down sampling units 306 and 308. The up sampling / down sampling filter scheme used in the present invention uses matrices composed of DCT basis.

9 is a block diagram for motion compensation of respective field signals from a field based memory. That is, since the top field data and the bottom field data are stored separately, the up field and the down field are respectively performed for the top field and the bottom field.

First, referring to the one-dimensional down-sampling process, Equation 2 and Equation 8 are used to express Equation 13 below.

Here, x represents 8x1 pixels, y represents downsampled 4x1 pixels, X represents a DCT coefficient block for x, and T ₈ represents an 8x8 DCT basis matrix. Also, And T ₄ represents the 4 × 4 DCT base matrix.

Therefore, Equation 13 is expressed by Equation 14 below.

here, Is defined as a 4x8 downsampling matrix and converts 8 pixels to 4 pixels.

In the up-sampling method, four pixels are converted into eight pixels by the inverse transformation of the above equation using the following equation. First, eight DCT coefficients are obtained from Equation (13).

The result of 8-point IDCT using Equation 15 can be obtained as shown in Equation 16 below.

As a result, equations (15) and (16) are expressed by the following equation.

Equation 17 shows a process of up-sampling a 1/2 resolution image stored in the memory 310 at the original resolution.

A motion compensation block is obtained after reproducing a macroblock that matches the original resolution in the vertical / horizontal direction using the upsampling matrix of Equation 17 above. That is, the upsampling filtering unit 601 reads the block of the top field from the memory 310 and performs upsampling to reproduce the macro block corresponding to the original resolution, and the upsampling filtering unit 602 reads from the memory 310. The block of the bottom field is read and upsampled to reproduce the macroblock corresponding to the original resolution, and then added by the adder 603 to obtain a motion compensation block.

In this case, when there is a half-pel interpolation in the horizontal direction or the full resolution motion vector (MV) does not fall by a multiple of 8, the upsampling filtering units 601 and 602 may surround 4x4 units in the vertical / horizontal direction. The blocks are read from memory 310. Then, for each of the blocks, the full-resolution block is reconstructed using the up-sampling matrix in each vertical / horizontal direction as derived from Equation 17 above. After that, the motion compensation unit 307 performs half pel interpolation on the region corresponding to the full resolution motion vector to obtain a motion compensated block that we want.

As shown in FIG. 5, the motion-compensated macroblock is subjected to down-sampling again to add to the result of 4 × 4 IDCT in the adder 305.

To this end, a macroblock having a size of 1/2 each in the horizontal and vertical directions is obtained by using the down sampling matrix of Equation 14 as shown in FIG. 9. That is, the down sampling filtering unit 604 performs down sampling on the top field, and the down sampling filtering unit 605 outputs a macro block each having a size of 1/2 in the horizontal / vertical direction.

The block thus obtained is stored in the memory 310 again through the MB adder 305 of FIG. 5, where blocks are added in units of fields.

As shown in FIG. 4, reduced-resolution pictures appear on the screen via VDP according to various display modes. At this time, as shown in (a) of FIG. 10, the bottom field position in the reduced-resolution picture stored in the memory 310 is not a field of a desired display position and should be corrected. For this purpose, a post-processing filter 311 is used in the vertical direction. In this case, as shown in FIG. 10, a simple average value or an FIR filter having about 4 taps is used.

In addition, some blocking artifacts may occur due to loss during downsampling after 4x4 IDCT or motion compensation. To compensate for this, improved image quality can be obtained by increasing the continuity of the interface through a 9-tap FIR filter in the horizontal direction during post-processing.

As described above, the present invention is used to display a plurality of HD class interlaced video signals encoded in high quality on one screen or to display a high resolution HD signal with an SD class low resolution screen device. 75% of the external memory is reduced. In particular, the present invention is advantageously applied to the MPEG-2 decoder chip which is a standard in the field of digital video transmission.

As described above, according to the digital video receiving apparatus according to the present invention, a 75% memory reduction efficiency and a variety of pictures in picture (PIP) or a low resolution display device are provided through a video decoder having a down converter for an HD interlaced sequence. You can get SD quality screen.

In addition, it is possible to display multiple HD quality videos and various kinds of various SD quality videos on one screen with only memory for processing a single HD quality video, and to display HD resolution video signals at low resolution without additional hardware burden. It can be connected to the display device to watch.

In particular, the present invention is an essential technology for application fields such as digital TV and video images, such as multi-decoding, a high-performance video decoder capable of receiving and processing multiple videos on one screen, and strengthening the technological competitiveness with other companies' digital TV. Can get a great effect.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (14)

Video bitstream extracting means for separating and extracting a bitstream including a video signal; And If the extracted video bitstream is an interlaced scan sequence and is a frame DCT coded block, the converted video bitstream is converted to a field DCT coded block while down-converting. Digital video receiving apparatus characterized in that it comprises a. The method of claim 1, wherein the video processor After variable-length decoding and inverse quantization of the input video bitstream, if the inversely quantized DCT coefficients are field DCT data of the interlaced sequence, 4x4 inverse discrete cosine transform (IDCT) after removing DCT coefficients of high frequency components in the horizontal / vertical direction The digital video receiving apparatus according to claim 1, wherein if the data is frame DCT, DCT coefficients of high frequency components are removed in the horizontal direction, converted to field DCT data, and vertical downsampling is performed in the converted DCT conversion region. . The method of claim 1, wherein the video processor When using a full resolution motion vector for motion compensation, up-sampling filtering is performed in the vertical / horizontal direction on the data read from the memory before motion compensation, and down-sampling filtering is performed in the vertical / horizontal direction after motion compensation. Digital video receiver. A video decoding apparatus which reconstructs an input video bitstream to a pixel value of an original screen through variable length decoding (VLD) and then through inverse quantization (IQ), inverse discrete cosine transform (IDCT), and motion compensation (MC). To If the inverse quantized DCT coefficient is the field DCT data of the interlaced scan sequence, the DCT coefficient of the high frequency component is removed in the horizontal / vertical direction and then 4x4 IDCT. If the DCT coefficient is the frame DCT data, the DCT coefficient of the high frequency component is removed in the horizontal direction. An IDCT unit for down-sampling in the vertical direction in the DCT conversion area after converting the DCT IDCT coefficients; A memory for storing an addition result of the IDCT data or the IDCT data and motion compensated data; A vertical / horizontal upsampling unit which upsamples the reference picture read from the memory in a vertical / horizontal direction; A motion compensation unit for performing motion compensation on the up-sampled up / down direction in the vertical / horizontal upsampling unit using a full resolution motion vector output from the VLD; A vertical / horizontal downsampling unit which down-samples the motion-compensated data in the vertical / horizontal direction after the motion compensation unit and stores the data again in memory in addition to the IDCT data; And And a video display processor for reading data stored in the memory and outputting the data stored in the memory to a display device according to a display mode. The method of claim 4, wherein the IDCT unit A horizontal reduction unit for removing high frequency component DCT coefficients in a horizontal direction in a frame DCT coded block of an interlaced scanning sequence; A frame / field converter for converting the frame DCT coded block into a field DCT coded block; A matrix multiplier for outputting IDCT coefficients of the field structure down-sampled in the vertical direction; And a horizontal IDCT for performing IDCT in a horizontal direction on the output data of the matrix multiplier. The method of claim 5, wherein the frame / field converter And converting two vertical blocks [X] having eight frame DCT coefficients into two field DCT coded blocks [Xtb] for the top field and the bottom field by applying the following matrix. [Xtb] = [T _f ] [IT8 ₂ ] [X] = here, [T8] represents an 8x8 DCT basis matrix of 8-point DCT basis, IDCT for two vertical blocks is represented by [IT8 ₂ ] matrix, Represents the i th 8 point DCT basis vector. 6. The matrix multiplier of claim 5 wherein the matrix multiplier A video decoding apparatus, characterized by outputting IDCT coefficients [ytb] of field units down-sampled in a horizontal / vertical direction by applying the following matrix. [ytb] = [Q] [X] = [IP4 ₂ ] [T _f ] [IT8 ₂ ] [X] = here, = Down-sampling matrix of field DCT coded coefficients, [T4] is a 4x4 DCT matrix built on a 4-point DCT basis, [T8] represents an 8x8 DCT basis matrix of 8-point DCT basis, IDCT for two vertical blocks is represented by [IT8 ₂ ] matrix, Denotes the i th 8 point DCT basis vector, [X] being two vertical blocks with 8 frame DCT coefficients. 8. The matrix of claim 7 wherein the matrix [Q] of the matrix multiplier is A video decoding apparatus, which operates only on vertical DCT coefficients as an 8x16 matrix. The method of claim 4, wherein the horizontal / vertical up sampling unit A video decoding apparatus comprising selecting a field corresponding to a motion vector during motion compensation, reading field reference blocks reduced in memory, and performing upsampling and filtering in each of the fields in the horizontal and vertical directions. The method of claim 4, wherein the motion compensation unit And half-pel interpolation on the upsampled blocks to construct a motion compensated block in field prediction compensation. The method of claim 4, wherein the motion compensation unit In the frame prediction compensation, video is characterized by constructing a reference block in a frame unit with up-sampled blocks of each field, and then half-pel interpolating a motion compensated block, and separating the motion compensated frame block into respective fields. Decoding device. The method of claim 4, wherein the horizontal / vertical down sampling unit A video decoding apparatus, characterized by converting eight pixels into four pixels by applying a down sampling matrix C _4x8 of the following 4x8 dimension. here, T ₈ is a matrix consisting of 8x8 DCT bases and T ₄ is a matrix consisting of 4x4 DCT bases. The method of claim 4, wherein the horizontal / vertical up sampling unit A video decoding apparatus, characterized by converting 4 pixels to 8 pixels by applying the following upsampling matrix. The display apparatus of claim 4, wherein the video display processor is further configured. And a post-processing filter for correcting the bottom field before displaying the reference pictures having the field-based vertical structure on the screen.