KR19990059172A - Oxide film planarization method of semiconductor device - Google Patents

Abstract

An oxide film planarization method applied to an isolation oxide film planarization process in shallow trench isolation or an oxide film planarization process between metal wiring layers in a semiconductor device manufacturing process is disclosed. The present invention includes the steps of depositing a nitride film having a thickness thinner than the oxide film on the oxide film formed on the isolation structure to have depressions between the structures to be isolated spaced apart on the semiconductor substrate; Performing a first chemical mechanical polishing process on the oxide film and the nitride film by using a polishing liquid having no difference in polishing rate for the oxide film and the nitride film, thereby leaving only the nitride film in the recessed portion; Performing a secondary chemical mechanical polishing process on the resultant of the primary chemical mechanical polishing process, using a polishing liquid having a lower polishing rate than that of an oxide film; And removing the nitride film remaining in the resultant product after the secondary chemical mechanical polishing process is completed. According to the present invention, a uniformly planarized oxide film can be obtained.

Description

Oxide film planarization method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oxide planarization method of a semiconductor device, and more particularly, to an oxide planarization method applied to an isolation oxide planarization process in shallow trench isolation or an oxide planarization process between metal wiring layers in a semiconductor device manufacturing process.

As the degree of integration of semiconductor integrated circuits increases and the multi-layer wiring process becomes practical, the importance of global planarization of interlayer insulating films has increased, and among these, chemical mechanical polishing has begun to attract attention as a new planarization technology. (Hereinafter referred to as "CMP").

CMP equipment chemically polishes the surface of a structure on a semiconductor substrate by a mechanical component using a polishing pad and an abrasive and a chemical component in a slurry solution. For this reason, in the beginning, although the cleanness problem and the practicality were also questioned, compared with the conventional method, the shape controllability of the vertical direction is excellent, and the expectation for practical use is increasing. In view of this situation, semiconductor equipment manufacturers are also accelerating the development of CMP equipment that can cope with the mass production stage of ultra-high-density semiconductor integrated circuits, and semiconductor process engineers are also trying to apply the CMP process to various manufacturing processes of semiconductor devices. I'm trying.

Among the various processes described above, the problem of the prior art will be described by taking a shallow trench isolation process (hereinafter referred to as "STI"). Since the STI process has many advantages, such as a reduction in bird's beak, compared to the conventional LOCal Oxidation of Silicon (LOCOS) process, it has been spotlighted as a new device isolation process. The CMP process, which is adopted as a method of planarizing the isolation oxide film in the STI process, functions not only to planarize the surface of the isolation oxide film but also to adjust its thickness.

1A to 1C are process cross-sectional views illustrating a process of planarizing the isolation oxide film of the STI.

First, the pad oxide film 20 is formed on the silicon substrate 10 with a thickness of 100 kPa, and the nitride film 30 is formed thereon with a relatively thin thickness of 1000 kPa (FIG. 1A).

Next, a trench is formed by a photolithography process using a field mask exposing the device isolation region. By the trench portion, the silicon substrate is turned into a trenched silicon substrate 11 having an active region. At this time, the silicon substrate is etched from the surface to a depth of about 5000 to 7000 Å. Then, an isolation oxide film 40 is deposited on the entire surface of the trenched silicon substrate by a chemical vapor deposition (CVD) process (FIG. 1B).

Then, the CMP process is applied to expose the nitride film 30 to obtain a planarized isolation oxide film 41 (FIG. 1C).

However, it is only an ideal to obtain the planarized isolation oxide film 41 as shown in FIG. 1C and there is a difficulty in controlling the thickness of the isolation oxide film for the following reasons.

Currently, the STI CMP process used is planarizing the isolation oxide film on the active region using one kind of polishing liquid on one polishing plate. However, the STI CMP process of this type is not only uniform in thickness of the nitride film remaining after polishing depending on the active region pattern of the substrate to be polished, but also has a large isolation oxide film having a depression in the center, as shown in FIG. It is difficult to control the thickness of the isolation oxide film because it is not possible to prevent dishing from being polished. This dishing phenomenon is a fatal weakness in the electrical insulation of the device, which is the purpose of the isolation process. As a result, the overall substrate planarization is achieved by the existing CMP process technology, but the dishing phenomenon that occurs when the isolation oxide film is wide can not be prevented. Severe problems arise.

Because of this problem, there is a demand in the semiconductor industry for a large difference in polishing rate between the isolation oxide film and the nitride film in order to control the STI CMP process, and recently, some of the companies that manufacture the polishing liquid satisfy this condition. The polishing liquid is supplied for mass production.

However, such a polishing liquid having a large difference in polishing rate between the isolation oxide film and the nitride film is expensive, and when polishing is performed using this, the polishing rate is changed every time the polishing is performed, thereby reducing the reliability of the process result.

Therefore, it is difficult to solve the change in thickness of the isolation oxide caused by dishing or pattern when the polishing liquid used for the oxide film CMP is used, and the polishing rate and the high polishing rate of the oxide film when the polishing liquid developed for the STI CMP is used. Problems such as process cost and reliability of polishing liquid should be preceded.

Accordingly, an object of the present invention is to provide an oxide film planarization method of a semiconductor device that does not cause dishing even when an isolation oxide film planarization step or shallow oxide planarization step between metal wiring layers in shallow trench isolation is performed.

Another technical problem of the present invention is to provide an oxide film planarization method of a semiconductor device which uses relatively little expensive polishing liquid having a large difference in polishing rate between an oxide film and a nitride film.

1A to 1C are process cross-sectional views illustrating a process of planarizing an isolation oxide film of STI;

2 is a cross-sectional view illustrating a dishing phenomenon in which a wide isolation oxide film is polished in a dish shape;

3A to 3E are cross-sectional views illustrating a process of planarizing an isolation oxide film of STI according to an embodiment of the present invention.

Explanation of Codes on Major Parts of Drawings

310. Nitride in the active area

410... Isolation oxide film

510... Nitride film

512... Protective Nitride

531. Abrasive Nitride

413. Planarized isolation oxide

In the oxide flattening method of the present invention for solving the above technical problems, a nitride film having a thickness thinner than that of the oxide film is formed on the oxide film formed on the isolation structure so as to have depressions between the structures to be isolated separated from the semiconductor substrate. Depositing; Performing a first chemical mechanical polishing process on the oxide film and the nitride film by using a polishing liquid having no difference in polishing rate for the oxide film and the nitride film, thereby leaving only the nitride film in the recessed portion; Performing a secondary chemical mechanical polishing process on the resultant of the primary chemical mechanical polishing process, using a polishing liquid having a lower polishing rate than that of an oxide film; And removing the nitride film remaining in the resultant product after the secondary chemical mechanical polishing process is completed.

In the present invention, the thickness of the oxide film is 1500 kPa or more, and the nitride film is preferably formed to a thickness of 250 ~ 350 kPa, wherein the primary chemical mechanical polishing process is the oxide film remaining on the structure to be isolated It is more preferable to carry out until it becomes 1000 Pa or less.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 3A is a cross-sectional view showing a state in which a structure similar to the result shown in FIG. 1B of the prior art is formed and a thin nitride film 510 of 300 kV is deposited thereon. The nitride film deposited here serves to protect the isolation oxide film in the trench region in a secondary polishing process described later.

Subsequently, the nitride film 510 on the isolation oxide film 410 is polished on the first polishing plate using a polishing liquid having no difference in polishing rate between the oxide film and the nitride film. In view of the cross section, the nitride film deposited on the protrusion of the oxide film is polished well, and the nitride film deposited on the depression is polished late. In this process, the isolation oxide film is first polished until the isolation oxide film on the nitride film 310 in the active region is less than 1000 mW, thereby obtaining the structure shown in Fig. 3B.

Next, as shown in FIG. 3C, the resultant of the first polishing completed on the second polishing plate is separated from the isolation oxide film remaining on the nitride film 310 in the active region using a polishing liquid having a large difference in polishing rate between the oxide film and the nitride film. Secondly polish. At this time, since the isolation oxide in the trench region is protected by the nitride film 512 deposited thereon, dishing does not occur. In other words, when secondary polishing is in progress, the isolation oxide film in the trench region is protected by the nitride film thereon, and the oxide film in the other portion is quickly polished.

FIG. 3D illustrates a state in which the secondary polishing is completed, and the remaining nitride film 513 serves as a polishing stopping layer during secondary polishing.

3E is a cross-sectional view illustrating a state in which a remaining nitride film is removed through a nitride strip process, which is a subsequent process of the STI CMP process. As can be seen from FIG. 3E, since the dishing phenomenon of the isolation oxide film does not occur, the planarized isolation oxide film 413 can be obtained. Therefore, the thickness difference of the isolation oxide film generated according to the chip pattern of the semiconductor device can be reduced.

Although the present invention has been described through the above embodiments, the present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea to which the present invention belongs.

Therefore, the application range of the present invention is not limited to the STI CMP process, which is the above embodiment, and can be applied even when the insulating film between the metal wiring lines is planarized. In this case, the portion corresponding to the trench area in the STI CMP process is naturally the space between the metal wiring lines. When applied to such applications, it is possible to reduce the nonuniformity of the insulating film due to the metal pattern.

The thickness difference of the isolation oxide film according to the dishing and pattern of the isolation oxide film generated when the STI CMP process is performed using only the conventional polishing liquid for oxide film CMP can be solved by the procedure of the process proposed by the present invention. In addition, it is possible to solve the problem of manufacturing cost increase when using only the STI CMP polishing liquid that is currently being developed or started to be commercially available, and may be caused by the reliability of the polishing liquid or colloidal stability. The difference in speed can be reduced by using two polishing liquids in sequence.

In addition, in view of the overall isolation process, the conventional technique of depositing and polishing a thick oxide film to remove dishing phenomenon is improved. By depositing a thin nitride film and performing a two-step CMP process, the thickness of the deposited oxide film is reduced. Can be. As such, when the thickness of the oxide film to be deposited is reduced, the thickness of the oxide film to be polished is also reduced, thereby reducing the time required for the deposition process and the unit process of the polishing process, thereby increasing productivity. In addition, reducing the amount to be polished in the polishing process means that the thickness uniformity of the oxide film remaining after polishing is improved, and thus, the polishing uniformity, which is a large object of the STI CMP process, is advantageous. Improved polishing uniformity broadens the process margin of subsequent processes.

Claims (3)

Depositing a nitride film having a thickness thinner than that of the oxide film on the oxide film formed on the isolation structure so as to have depressions between the structures to be separated spaced apart on the semiconductor substrate; Performing a first chemical mechanical polishing process on the oxide film and the nitride film by using a polishing liquid having no difference in polishing rate for the oxide film and the nitride film, thereby leaving only the nitride film in the recessed portion; Performing a secondary chemical mechanical polishing process on the resultant of the primary chemical mechanical polishing process, using a polishing liquid having a lower polishing rate than that of an oxide film; And And removing the nitride film remaining in the resultant product after the secondary chemical mechanical polishing process is completed. The method of claim 1, wherein the oxide film has a thickness of at least 1500 GPa and the nitride film is formed at a thickness of 250 to 350 GPa. 3. The method of claim 2, wherein the primary chemical mechanical polishing step is performed until the oxide film remaining on the structure to be isolated is 1000 kPa or less.