KR100695415B1 - Method for forming isolation layer in semiconductor device - Google Patents

Method for forming isolation layer in semiconductor device Download PDF

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KR100695415B1
KR100695415B1 KR1020000073107A KR20000073107A KR100695415B1 KR 100695415 B1 KR100695415 B1 KR 100695415B1 KR 1020000073107 A KR1020000073107 A KR 1020000073107A KR 20000073107 A KR20000073107 A KR 20000073107A KR 100695415 B1 KR100695415 B1 KR 100695415B1
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film
forming
trench
pad nitride
nitride film
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KR1020000073107A
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Korean (ko)
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KR20020043908A (en
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차용원
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

본 발명은 디싱을 방지하도록 한 소자 분리막의 형성 방법에 관한 것으로, 이를 위한 본 발명은 반도체기판 상에 패드질화막을 형성하는 단계; 상기 패드질화막과 상기 반도체기판을 선택적으로 식각하여 트렌치를 형성하는 단계; 상기 트렌치의 깊이를 매립하도록 상기 패드질화막 상에 절연막을 형성하는 단계; 상기 절연막상에 반사방지막을 형성하는 단계; 상기 반사방지막 상에 감광막을 도포하고 노광 및 현상으로 패터닝하는 단계; 상기 패터닝된 감광막을 마스크로 하여 상기 반사방지막을 식각하여 상기 트렌치 중심부의 상기 절연막상에만 디싱방지를 위한 반사방지막패턴을 형성하는 단계; 상기 감광막을 스트립하는 단계; 및 상기 패드질화막을 연마타겟으로 상기 절연막을 화학적기계적연마하되, 상기 반사방지막패턴까지 연마하여 상기 트렌치에 매립되는 소자분리막을 형성하는 단계를 포함한다.The present invention relates to a method for forming a device isolation layer for preventing dishing, and more particularly, to a method for forming a device isolation layer, the method comprising: forming a pad nitride film on a semiconductor substrate; Selectively etching the pad nitride film and the semiconductor substrate to form a trench; Forming an insulating film on the pad nitride film to fill a depth of the trench; Forming an anti-reflection film on the insulating film; Applying a photoresist film on the antireflection film, and patterning the photoresist film by exposure and development; Etching the antireflection film using the patterned photoresist as a mask to form an antireflection film pattern for preventing dishing only on the insulating film at the center of the trench; Stripping the photosensitive film; And chemically and mechanically polishing the insulating film with the pad nitride film as a polishing target to polish the anti-reflection film pattern to form a device isolation film to be buried in the trench.

본 발명은 트렌치 중심부 상부에만 패드질화막과 동일한 연마속도를 가지는 디싱방지패턴으로서 반사방지막패턴을 형성하여 후속 화학적기계적연마시 디싱 현상을 방지할 수 있다.The present invention can prevent the dishing phenomenon in the subsequent chemical mechanical polishing by forming an antireflection film pattern as a dishing prevention pattern having the same polishing rate as that of the pad nitride film only in the upper part of the central portion of the trench.

소자분리막, 패드질화막, 화학적기계적연마, 디싱Device isolation film, pad nitride film, chemical mechanical polishing, dishing

Description

반도체소자의 소자 분리막 형성 방법{METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE} TECHNICAL FIELD [0001] The present invention relates to a method of forming an isolation layer of a semiconductor device,             

도 1a 내지 도 1b는 종래기술에 따른 소자 분리막의 형성 방법을 도시한 도면,1A and 1B are diagrams illustrating a method of forming a device isolation layer according to the related art,

도 2a 내지 도 2d는 본 발명의 실시예에 따른 소자 분리막의 형성 방법을 도시한 도면.
2A to 2D are diagrams illustrating a method of forming an element isolation film according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

21 : 반도체기판 22 : 패드산화막21: semiconductor substrate 22: pad oxide film

23 : 패드질화막 24 : 트렌치23: pad nitride film 24: trench

25 : 고밀도 플라즈마 산화막 26 : 반사방지막25: high density plasma oxide film 26: antireflection film

27 : 감광막 28 : 디싱방지 패턴27: photosensitive film 28: anti-dishing pattern

29 : 소자분리막
29: Device isolation film

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 화학적기계적연마시 디싱을 방지하도록 한 반도체소자의 소자분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device that prevents dishing during chemical mechanical polishing.

일반적으로 반도체소자의 트랜지스터 제조시, 각각의 트랜지스터를 전기적으로 격리시키기 위해 ISO(Isolation) 공정을 적용하며, 최근에는 트렌치(Trench)를 이용한 STI(Shallow Trench Isolation) 공정을 주로 적용한다.Generally, an ISO (Isolation) process is applied to electrically isolate each transistor when manufacturing a transistor of a semiconductor device, and a STI (Shallow Trench Isolation) process using a trench is mainly applied.

도 1a 내지 도 1b는 종래기술에 따른 소자분리막의 제조 방법을 간략히 도시한 도면으로서, STI 공정을 도시하고 있다.FIGS. 1A to 1B are schematic views showing a conventional method for manufacturing an element isolation film, and show an STI process.

도 1a에 도시된 바와 같이, 반도체기판(11)상에 패드산화막(12), 패드질화막(13)을 순차적으로 형성한 다음, 패드질화막(13)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 소자 분리마스크를 형성한다. 계속해서, 소자분리마스크를 이용하여 패드질화막(13) 및 패드산화막(12)을 순차적으로 식각하여 반도체기판(11)의 소자분리영역을 노출시킨다.A pad oxide film 12 and a pad nitride film 13 are sequentially formed on a semiconductor substrate 11 and then a photoresist film is coated on the pad nitride film 13 and patterned by exposure and development Thereby forming an element isolation mask. Subsequently, the pad nitride film 13 and the pad oxide film 12 are sequentially etched by using an element isolation mask to expose the element isolation region of the semiconductor substrate 11.

계속해서, 노출된 반도체기판(11)의 소자분리영역을 소정 깊이로 식각하여 트렌치를 형성하고, 트렌치를 포함한 반도체기판(11)상에 트렌치 매립용으로 갭필(Gapfill) 특성이 우수한 HDP CVD(High Density Plasma Chemical Vapor Deposition)-산화막(이하 '고밀도 플라즈마 산화막'이라 약칭함)(14)을 증착한다. 이 때, 고밀도 플라즈마 산화막(14)은 패드질화막(13)의 상부로 소정 두께만큼 증착되어 하부의 트렌치를 충분히 매립시키며, 패드질화막(13)의 상부에는 고밀도 플라즈마 산화막의 고유 증착 특성으로 인해 산모양으로 증착된다. Subsequently, a trench is formed by etching the element isolation region of the exposed semiconductor substrate 11 to a predetermined depth, and a trench is formed on the semiconductor substrate 11 including the trench by HDP CVD (High Density Plasma Chemical Vapor Deposition) -rich oxide film 14 (hereinafter, referred to as 'high density plasma oxide film'). At this time, the high density plasma oxide film 14 is deposited to a predetermined thickness above the pad nitride film 13 to sufficiently fill the lower trench, and on top of the pad nitride film 13, .                         

도 1b에 도시된 바와 같이, 패드질화막(13)을 소정 두께만큼 잔류시키는 타겟으로 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 트렌치에 매립되는 소자분리막(15)을 형성한다. 이 때, 화학적기계적연마 후 패드질화막(13a)이 잔류한다.As shown in FIG. 1B, a chemical mechanical polishing (CMP) process is performed on the target to leave the pad nitride film 13 at a predetermined thickness to form a device isolation film 15 buried in the trench. At this time, the pad nitride film 13a remains after the chemical mechanical polishing.

그러나, 화학적기계적연마 공정 적용시, 고밀도플라즈마산화막(14)과 패드질화막(13)의 선택비의 차이에 의해 소자분리막(15)의 상측 부분이 밑으로 꺼지는 디싱(16)이 발생하며, 이러한 디싱(16)은 STI 특성을 악화시키며 반도체소자의 전기적 특성을 저하시키는 원인이 된다.
However, when the chemical mechanical polishing process is applied, a dishing 16 occurs in which the upper portion of the device isolation film 15 is turned downward due to a difference in selection ratio between the high density plasma oxide film 14 and the pad nitride film 13, (16) deteriorates the STI characteristics and deteriorates the electrical characteristics of the semiconductor device.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 트렌치를 이용한 소자분리막 형성시 화학적기계적연마 공정으로 초래되는 디싱 현상을 방지하는데 적합한 소자분리막의 형성 방법을 제공하는데 그 목적이 있다.
It is an object of the present invention to provide a method of forming a device isolation film which is suitable for preventing a dishing phenomenon caused by a chemical mechanical polishing process in forming an isolation film using a trench.

상기 목적을 달성하기 위한 본 발명의 소자 분리막의 형성 방법은 반도체기판 상에 패드질화막을 형성하는 단계; 상기 패드질화막과 상기 반도체기판을 선택적으로 식각하여 트렌치를 형성하는 단계; 상기 트렌치의 깊이를 매립하도록 상기 패드질화막 상에 절연막을 형성하는 단계; 상기 절연막상에 반사방지막을 형성하는 단계; 상기 반사방지막 상에 감광막을 도포하고 노광 및 현상으로 패터닝하는 단계; 상기 패터닝된 감광막을 마스크로 하여 상기 반사방지막을 식각하여 상기 트렌치 중심부의 상기 절연막상에만 디싱방지를 위한 반사방지막패턴을 형성하는 단계; 상기 감광막을 스트립하는 단계; 및 상기 패드질화막을 연마타겟으로 상기 절연막을 화학적기계적연마하되, 상기 반사방지막패턴까지 연마하여 상기 트렌치에 매립되는 소자분리막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a device isolation layer, including: forming a pad nitride layer on a semiconductor substrate; Selectively etching the pad nitride film and the semiconductor substrate to form a trench; Forming an insulating film on the pad nitride film to fill a depth of the trench; Forming an anti-reflection film on the insulating film; Applying a photoresist film on the antireflection film, and patterning the photoresist film by exposure and development; Etching the antireflection film using the patterned photoresist as a mask to form an antireflection film pattern for preventing dishing only on the insulating film at the center of the trench; Stripping the photosensitive film; And chemically and mechanically polishing the insulating film with the pad nitride film as a polishing target to polish the antireflection film pattern to form a device isolation film embedded in the trench.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 실시예에 따른 소자 분리막의 형성 방법을 도시한 도면이다.2A to 2D are views illustrating a method of forming an element isolation layer according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체기판(21)상에 패드산화막(22), 패드질화막(23)을 순차적으로 형성한 다음, 패드질화막(23)상에 감광막(도시 생략)을 도포하고 노광 및 현상으로 패터닝하여 소자분리마스크를 형성한다. 계속해서, 소자분리마스크를 이용하여 하부의 패드질화막(23), 패드산화막(22)을 순차적으로 식각한 다음, 패드산화막(22) 식각으로 노출된 반도체기판(21)을 소정 깊이만큼 식각하여 트렌치(24)를 형성한다.2A, a pad oxide film 22 and a pad nitride film 23 are sequentially formed on a semiconductor substrate 21, a photosensitive film (not shown) is coated on the pad nitride film 23, Thereby forming an element isolation mask. Subsequently, the lower pad nitride film 23 and the pad oxide film 22 are successively etched by using an element isolation mask, and then the semiconductor substrate 21 exposed by etching the pad oxide film 22 is etched by a predetermined depth, (24).

도 2b에 도시된 바와 같이, 트렌치(24)를 포함한 패드질화막(23) 상부에 고밀도 플라즈마 산화막(25)을 증착하는데, 트렌치(24)의 깊이만큼만 고밀도 플라즈마 산화막(25)을 증착한다. 이 때, 고밀도 플라즈마 산화막(25)의 증착 특성으로 인해 패드질화막(23) 상부에는 산모양으로 증착되며, 트렌치(24)를 매립시킬 때 패드질화막(23) 상부에 산모양이 형성되도록 고밀도 플라즈마 산화막(25)의 증착 두께를 조절한다.The high density plasma oxide film 25 is deposited only to the depth of the trench 24 in order to deposit the high density plasma oxide film 25 on the pad nitride film 23 including the trench 24 as shown in FIG. At this time, due to the deposition characteristics of the high-density plasma oxide film 25, the oxide film is deposited on the pad nitride film 23 in the form of an acid, and the oxide film is formed on the pad nitride film 23 when the trench 24 is buried. (25).

고밀도 플라즈마 산화막(25)상에 반사방지막(Anti Reflective Coating)(26) 을 형성한후, 반사방지막(26)상에 감광막(27)을 도포하고 노광 및 현상으로 패터닝하여 트렌치의 중심부 상부에만 감광막(27)을 잔류시키고 패드질화막(23) 상부에는 감광막을 잔류시키지 않는다.An antireflective coating 26 is formed on the high density plasma oxide film 25 and then a photoresist film 27 is coated on the antireflection film 26 and patterned by exposure and development to form a photoresist film 27 remain and the photoresist film is not left on the pad nitride film 23.

도 2c에 도시된 바와 같이, 잔류하는 감광막패턴(27)을 이용하여 하부의 반사방지막(26)을 식각하고 감광막(27)을 스트립하면, 트렌치(24)의 중심부 상부에만 반사방지막패턴(28)이 형성된다.2C, when the lower antireflection film 26 is etched using the remaining photoresist pattern 27 and the photoresist film 27 is stripped, the antireflection film pattern 28 is formed only on the central part of the trench 24, .

도 2d에 도시된 바와 같이, 패드질화막(23)을 소정 두께만큼 잔류시키는 타겟(A)으로 고밀도 플라즈마 산화막(25)을 화학적기계적연마하여 소자분리막(29)을 형성한다. 이 때, 트렌치(24)의 중심부 상부에 잔류하는 반사방지막패턴(28)은 패드질화막(23)과 동일한 연마속도를 가지므로 화학적기계적연마시 소자분리막(29)의 디싱을 방지하는 역할을 하며, 화학적기계적연마시 반사방지막패턴(28)까지 동시에 연마하여 모두 제거한다. 미설명 도면부호 23a는 잔류하는 패드질화막이다.The device isolation film 29 is formed by chemically and mechanically polishing the high density plasma oxide film 25 with the target A that leaves the pad nitride film 23 at a predetermined thickness, as shown in FIG. 2D. Since the antireflection film pattern 28 remaining on the central portion of the trench 24 has the same polishing rate as that of the pad nitride film 23, it functions to prevent dishing of the element isolation film 29 during chemical mechanical polishing, When chemically and mechanically polished, the antireflection film pattern 28 is simultaneously polished and removed. Reference numeral 23a denotes a remaining pad nitride film.

이와 같이 디싱방지 역할을 하는 디싱방지막으로서 트렌치의 중심부 상부에 패드질화막과 동일한 연마속도를 가지는 반사방지막패턴(28)을 형성하면, 패드질화막과 동일한 연마속도로 화학적기계적연마 공정이 진행되어 소자분리막 상부의 디싱을 방지한다.When the anti-reflection film pattern 28 having the same polishing rate as that of the pad nitride film is formed on the central portion of the trench as a dishing prevention film serving as a dishing prevention, the chemical mechanical polishing process proceeds at the same polishing rate as the pad nitride film, Thereby preventing the dishing of the substrate.

후속 공정으로 패드질화막(23a)과 패드산화막(22)을 제거한다.The pad nitride film 23a and the pad oxide film 22 are removed in a subsequent process.

본 발명의 실시예에서는 고밀도 플라즈마 산화막을 이용하여 트렌치를 매립시켰으나, 다른 갭필산화막으로서 PE-TEOS(Plasma Enhanced Tetra Etyl Ortho Silicate) 또는 BPSG(Boro Phospho Silicate Glass) 중 어느 하나를 이용하는 경우에 트렌치 중심부 상부에 디싱 방지용 반사방지막을 형성하여 화학적기계적연마로 인한 디싱을 방지할 수 있다.In the embodiment of the present invention, the trench is filled with the high density plasma oxide film. However, when any one of PE-TEOS (Plasma Enhanced Tetra Etyl Ortho Silicate) or BPSG (Boro Phospho Silicate Glass) It is possible to prevent the dishing caused by the chemical mechanical polishing.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명의 소자 분리막의 형성 방법은 고밀도 플라즈마 산화막 증착과 화학적기계적연마를 이용한 평탄화 공정시 발생하는 디싱을 구조적으로 방지하므로써 STI 특성을 향상시켜 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.The method of forming an isolation film of the present invention as described above structurally prevents dishing that occurs during a planarization process using a high-density plasma oxide film deposition and chemical mechanical polishing, thereby improving the reliability of a semiconductor device by improving STI characteristics have.

Claims (6)

트렌치 구조의 소자분리막 형성 방법에 있어서,In a trench-type device isolation film forming method, 반도체기판 상에 패드질화막을 형성하는 단계;Forming a pad nitride film on a semiconductor substrate; 상기 패드질화막과 상기 반도체기판을 선택적으로 식각하여 트렌치를 형성하는 단계;Selectively etching the pad nitride film and the semiconductor substrate to form a trench; 상기 트렌치의 깊이를 매립하도록 상기 패드질화막 상에 절연막을 형성하는 단계;Forming an insulating film on the pad nitride film to fill a depth of the trench; 상기 절연막상에 반사방지막을 형성하는 단계;Forming an anti-reflection film on the insulating film; 상기 반사방지막 상에 감광막을 도포하고 노광 및 현상으로 패터닝하는 단계; Applying a photoresist film on the antireflection film, and patterning the photoresist film by exposure and development; 상기 패터닝된 감광막을 마스크로 하여 상기 반사방지막을 식각하여 상기 트렌치 중심부의 상기 절연막상에만 디싱방지를 위한 반사방지막패턴을 형성하는 단계; Etching the antireflection film using the patterned photoresist as a mask to form an antireflection film pattern for preventing dishing only on the insulating film at the center of the trench; 상기 감광막을 스트립하는 단계; 및Stripping the photosensitive film; And 상기 패드질화막을 연마타겟으로 상기 절연막을 화학적기계적연마하되, 상기 반사방지막패턴까지 연마하여 상기 트렌치에 매립되는 소자분리막을 형성하는 단계Forming a device isolation film embedded in the trench by polishing the insulating film to the anti-reflection film pattern by chemically and mechanically polishing the pad nitride film to a polishing target 를 포함하는 소자 분리막의 형성 방법.And forming a second insulating film on the second insulating film. 삭제delete 제1항에 있어서,The method according to claim 1, 상기 절연막은 고밀도 플라즈마 산화막을 이용하는 것을 특징으로 하는 소자분리막의 형성 방법.Wherein the insulating film is a high-density plasma oxide film. 삭제delete 제 1 항에 있어서,The method according to claim 1, 상기 반사방지막패턴은 상기 패드질화막과 동일한 연마속도를 가지는 반사방지막을 이용하는 것을 특징으로 하는 소자 분리막의 형성 방법.Wherein the antireflection film pattern uses an antireflection film having the same polishing rate as the pad nitride film. 삭제delete
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KR19990059172A (en) * 1997-12-30 1999-07-26 김영환 Oxide film planarization method of semiconductor device

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