KR100815962B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to guarantee the margin of a CMP process by forming a planarization stop layer using a silicon nitride layer in a trench oxide layer region with a step in an STI process using reverse patterning. An oxide layer(202) and a plurality of first photoresist patterns separated from each other by a predetermined interval are formed on a semiconductor substrate(201). The oxide layer and the substrate are selectively etched to form a plurality of trenches by using the first photoresist pattern as an etch mask. A trench oxide layer(205) is filled in the trench. A planarization stop layer is formed on the trench oxide layer. A second photoresist pattern is formed on the planarization stop layer. The planarization stop layer is selectively etched by using the second photoresist pattern as an etch mask. The trench oxide layer is planarized by an etch-back process or a CMP process while the selectively etched planarization stop layer is removed. An ARC(anti-reflective coating) is formed on the planarized trench oxide layer. A plurality of third photoresist patterns are formed on the ARC. The ARC and the trench oxide layer are selectively etched to form an STI by using the third photoresist pattern as an etch mask.

Description

Manufacturing Method of Semiconductor Device

1A to 1B are cross-sectional views illustrating a STI manufacturing method of a semiconductor device according to the prior art.

2A to 2K are cross-sectional views illustrating a STI manufacturing method of a semiconductor device in accordance with an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

201: semiconductor substrate

202: oxide film

203: first photoresist pattern

204: trench

205: trench oxide film

206: planarization blocking film

207: second photoresist pattern

208: ARC (Anti Reflect Coating)

209: third photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the reliability of a planarization process during a process for forming shallow trench isolation (STI).

In order to realize high integration of the semiconductor device, it is necessary to form various semiconductor elements constituting the semiconductor device, for example, transistors, capacitors, and various wirings in a very narrow area. Therefore, since the distance between each component which comprises a semiconductor device is narrow, it is necessary to further strengthen the insulation between each component. Conventionally, a LOCOS field oxide film, which is formed by locally oxidizing a silicon substrate, has been widely used as a means for electrically separating semiconductor elements constituting a semiconductor device.

However, the locos type field oxide film interferes with high integration of the semiconductor device because the locus-type field oxide film partially invades the active region where the semiconductor devices are formed due to a bird's beak generated in the formation process. Therefore, a field oxide film having a small area and excellent insulating property was required. A representative example is a trench field oxide film, and a shallow trench isolation (STI) is particularly widely used. In the STI process, a semiconductor substrate region is selectively etched to form a trench for device isolation, and an insulating film is filled in the trench.

 In recent years, as semiconductor devices become more integrated and miniaturized, the size of each individual device is reduced, and the width of the trench for forming the device isolation layer in the substrate is decreased and the depth is also increased. As such, when the aspect ratio of the trench increases due to the decrease in the trench width and the increase in depth due to the high integration of the device, the step coverig is not good during the deposition of the trench oxide. A problem arises in that the inlet portion is blocked first, thereby degrading a gap fill capability in which the oxide layer is not completely filled in the trench.

1A to 1B are cross-sectional views for explaining a method of forming an STI capable of improving gap fill capability.

First, as shown in FIG. 1A, a plurality of trenches are formed by etching the semiconductor substrate 101 to form an STI, and then a trench oxide film 103 having a predetermined thickness to sufficiently fill the trench with respect to the entire surface of the substrate 101. E). At this time, in the process of embedding the trench oxide film 103 as described above on the active region of the substrate 101, an unnecessary additional film, for example, because the hard mask of the pad oxide film and the pad nitride film is not present on the substrate 101. The gap fill margin can be wider because the aspect ratio depth of the trench needs to be considered only as the depth of the actual trench.

However, as illustrated in FIG. 1B, planarization through chemical mechanical polishing (CMP) may be performed on the result of depositing the trench oxide film 103, and the pad used as an etch stop layer in the CMP process may be used. Since there is no nitride film, it is difficult to control the trench oxide film 103 to be uniformly flattened.

Therefore, as described above, in the CMP process for planarizing the trench oxide film 103, not only the process margin due to the absence of the pad nitride film is insufficient but also dishing according to the pattern density, as shown in FIG. 1B. The problem of aggravating (ishing) and erosion (A) adversely affects subsequent processes.

In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the reliability of the planarization process in the process for forming the STI.

In order to achieve the above object, the present invention comprises the steps of forming an oxide film and a plurality of first photoresist patterns spaced at predetermined intervals on a semiconductor substrate; Forming a plurality of trenches by selectively etching the oxide layer and the substrate using the first photoresist pattern as an etching mask; Embedding a trench oxide layer in the trench; Forming a planarization blocking film on the trench oxide film; Forming a second photoresist pattern on the planarization blocking film; Selectively etching the planarization blocking layer using the second photoresist pattern as an etching mask; Planarizing the trench oxide layer, but removing the selectively etched planarization barrier layer; Forming an anti reflect coating (ARC) film on the planarized trench oxide film; Forming a plurality of third photoresist patterns on the ARC (Anti Reflect Coating) film; And selectively etching the ARC and the trench oxide layer using the third photoresist pattern as an etching mask to form a shallow trench isolation (STI).

According to an embodiment of the present invention, the planarization blocking film is preferably a silicon nitride film (SiN).

According to an embodiment of the present invention, in the forming of the third photoresist pattern, the third photoresist pattern is preferably formed on the field region of the semiconductor substrate.

In addition, according to an embodiment of the present invention, the planarization may be performed through an etch back process or a chemical mechanical polishing process.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Descriptions of technical contents that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description.

First, as illustrated in FIG. 2A, an oxide film 202 is formed on a surface of a semiconductor substrate 201 using TEOS (Tetra Ethyl Ortho Silicate) material. Subsequently, after the first photoresist film is formed on the oxide film 202, the first photoresist film is patterned to expose a region where the device isolation film is to be formed on the substrate 201. That is, the first photoresist film formed on the substrate 201 is exposed to form a plurality of first photoresist patterns 203 spaced at predetermined intervals.

Next, as illustrated in FIG. 2B, the oxide film 202 is selectively etched using the first photoresist pattern 203 as an etching mask to form the trench 204 in the substrate 201.

Subsequently, the substrate 201 is selectively etched to a predetermined depth by dry etching including reactive ion etching (RIE) using the first photoresist pattern 203 and the etched oxide layer 202 as an etching mask. Multiple trenches 204 are formed. In this case, after the trench 204 is formed, a process of thinning the thermal diffusion with respect to the inner wall of the trench 204 may be included. This process can prevent impurities from penetrating into the silicon during the subsequent filling of the trench oxide film.

Subsequently, as illustrated in FIG. 2C, the first photoresist pattern 203 may be removed using an ashing process.

Next, as shown in 2d, a trench oxide film 205 having a predetermined thickness is deposited to sufficiently fill the trench 204 with respect to the entire surface of the semiconductor substrate 201 including the trench 204 formed by the above-described method. In this case, the trench oxide layer 205 may be formed using an oxide film having good gap fill characteristics, for example, SiO ₂ , and preferably by using high density plasma chemical vapor deposition (HDP CVD). In particular, when the trench oxide 205 is buried, an unnecessary additional film such as a pad oxide film and a pad nitride film hard mask does not exist on the substrate 201, so the aspect ratio depth of the trench 204 is actually a trench. The gap fill margin can be further widened by considering only the depth of 204.

Next, as shown in FIG. 2E, when the trench oxide film 205 is buried in the entire surface of the substrate 201 including the trench 204 as described above, the trench oxide film 205 embedded in the trench 204 region. May be deposited to dent so that a step may occur. Such a step may be overcome through a planarization process, in which case, problems of dishing and erosion may occur in the trench oxide layer 205. Accordingly, the planarization stopper layer 206 is deposited on the trench oxide layer 205 by using a silicon nitride film (SiN) to form a planarization stopper layer on the trench 204 region where the step is generated.

Next, as shown in FIG. 2F, a second photoresist film is applied on the trench oxide film 205 on which the planarization stop film 206 is deposited, and then, on the trench 204 region where the step occurs as described above. The second photoresist film is exposed to form the planarization stopper film 206 to form the second photoresist pattern 207.

Next, as illustrated in FIG. 2G, the planarization blocking layer 206 may be selectively etched using the second photoresist pattern 207 as an etching mask.

Next, as shown in FIG. 2H, planarization is performed through chemical mechanical polishing (CMP) on the result of depositing the trench oxide film 205. In this case, the planarization process may be performed on the trench oxide layer 205, and a process of removing the planarization blocking layer selectively etched may be performed. Therefore, as described above, in the planarization process of the trench oxide film 205, by partially forming the planarization stopper film 206, the CMP process margin for the trench oxide film 205 can be secured, as well as the pattern density. ) Can prevent dishing and erosion.

Next, as shown in FIG. 2I, an ARC (Anti Reflect Coating) film 208 and a third photoresist film are formed on the planarized trench oxide film 205.

The third photoresist film thus formed is then patterned to expose the active region in the substrate 201. That is, the third photoresist film formed on the substrate 201 including the ARC film 208 and the planarized trench oxide film 205 is exposed to expose a plurality of third photoresist patterns 209 on the field region of the substrate 201. Form. The process of forming the third photoresist pattern 209 is for use as a mask for forming a plurality of STIs.

Next, as shown in FIG. 2J, the ARC film 208 is selectively etched using the third photoresist pattern 209 as an etching mask.

Subsequently, using a third photoresist pattern 209 and an etched ARC film 208 as an etching mask again, trenches with a sufficient thickness using a dry etching method including a RIE method to expose the active region on the substrate 201. A trench oxide film 205 having 204 embedded therein is etched. In general, in the process of forming the STI, a sacrificial layer pattern and a photoresist pattern are formed on the active region of the substrate, and the STI is formed in the substrate using the pattern as an etching mask.

However, the STI forming method according to the present invention, in contrast to the above-described method, for example, is a method of forming an isolation layer using reverse patterning to form an active pattern of the substrate by forming a pattern of the same method as in the field region above the substrate. It is possible to form an STI by etching the exposed region. In the STI process using reverse patterning, when the trench oxide layer 205 is buried, an unnecessary additional layer, for example, an aspect ratio depth of the trench 204 is not present on the substrate 201 because hard masks of the pad oxide layer and the pad nitride layer do not exist on the substrate 201. Since the gap only needs to be considered as the depth of the actual trench 204, the gap fill margin can be further widened.

Next, as shown in FIG. 2K, an ashing process and a cleaning process are performed on the remaining third photoresist pattern 209. In this way, the STI process using reverse patterning formed according to the present invention can implement a profile of normal STI without using a hard mask.

Although specific embodiments of the present invention have been described with reference to the drawings, this is intended to be easily understood by those skilled in the art and is not intended to limit the technical scope of the present invention. Therefore, the technical scope of the present invention is determined by the matters described in the claims, and the embodiments described with reference to the drawings may be modified or modified as much as possible within the technical spirit and scope of the present invention.

As described above, according to the present invention, the margin of the CMP process can be secured by forming a planarization stoppage film using a silicon nitride film in the trench oxide film region in which the step is generated in the STI (Shallow Trench Isolation) process using reverse patterning. The reliability of the process can be improved.

Claims (4)

Forming an oxide film and a plurality of first photoresist patterns spaced at predetermined intervals on the semiconductor substrate; Forming a plurality of trenches by selectively etching the oxide layer and the substrate using the first photoresist pattern as an etching mask; Embedding a trench oxide layer in the trench; Forming a planarization blocking film on the trench oxide film; Forming a second photoresist pattern on the planarization blocking film; Selectively etching the planarization blocking layer using the second photoresist pattern as an etching mask; Planarizing the trench oxide layer, but removing the selectively etched planarization stop layer; Forming an anti reflect coating (ARC) film on the planarized trench oxide film; Forming a plurality of third photoresist patterns on the ARC (Anti Reflect Coating) film; And And selectively etching the ARC and the trench oxide layer using the third photoresist pattern as an etching mask to form a shallow trench isolation (STI). In claim 1, The planarization blocking film is a silicon nitride film (SiN) manufacturing method of a semiconductor device. In claim 1, In the forming of the third photoresist pattern, the third photoresist pattern is formed on the field region of the semiconductor substrate, characterized in that the manufacturing method. In claim 1, The planarization step is a semiconductor device manufacturing method characterized in that the progress through the etch back process or chemical mechanical polishing process.

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