KR19990058264A - Dual processor communication control logic - Google Patents

Abstract

The present invention relates to a communication control logic of a dual processor, in particular, when two processors simultaneously require access to a multi-processor communication control, efficiently controlling them to prevent a data collision.

Conventionally, since data communication is performed by a unique communication method supported by one processor itself, it is generally later than the method using DPRAM (Dual Port-RAM), its operation method is complicated, and it supports high speed communication. In the communication method using DPRAM, there is a problem that the reliability of data is deteriorated when there is an access request at the same time.

In order to solve the above problem, the present invention delays the access request signal by a half cycle when a plurality of processors simultaneously request data access, and simultaneously accesses the delayed signal and the busy signal generated by checking whether the other processor is accessed. By configuring the control logic that outputs the chip selection signal to prevent data collisions, it is possible to provide high-speed support and improve the reliability of the data while preventing data collisions due to simultaneous access.

Description

Dual processor communication control logic

The present invention relates to a communication control logic of a dual processor, in particular, in the communication control of multiple processors, when an access request signal is simultaneously received from a plurality of processors so as to efficiently control the data exchange and prevent data collisions. .

In general, as the controller of the system is digitalized, a multi-processing technique is gradually introduced and widely applied to the industry. Accordingly, data communication between processors is required, and various communication methods have been developed.

One of them is the unique communication technique supported by the processor itself, which performs data communication with each other. Even though it supports high-speed communication method, it is generally slower than the method using DPRAM (Dual Port-RAM). Complex.

And, secondly, dual port-RAM (DPRAM) is used for communication, which enables high-speed communication, but when two processors simultaneously access data, reliability of data is inferior.

As described above, in the related art, data communication between each other is performed by a unique communication method supported by one processor itself, but even though it supports high-speed communication, it is generally slower than the method using DPRAM and its operation method is complicated. Second, there is a problem that the dual port RAM to improve the speed, but at the same time, the data reliability decreases when accessed.

In order to solve the above problem, the present invention is to delay the access request signal by half a period to efficiently control when two processors simultaneously access the DPRAM, and logic the delayed signal and the busy signal generated according to the access of another processor. By processing the control logic to output the chip select signal to the DPRAM, it is possible to improve the reliability of the communication by preventing collision due to the simultaneous data demand of the processor.

1 is a block diagram showing a dual processor access control device of the present invention]

2 is a detailed circuit diagram of the control logic of the present invention.

3 is an operation waveform diagram of control logic by the present invention dual processor

The configuration of the communication control logic of the dual processor of the present invention is as shown in Figs.

First and second processors 10 and 20 for outputting access request signals REQ1 * and REQ2 * for data communication; Access is checked according to the access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20 to control simultaneous access and output corresponding chip select signals CS1 * and CS2 *, respectively. And a memory 40 for exchanging data with the first and second processors 10 and 20 according to the chip select signals CS1 * and CS2 * of the control logic 30. do.

And, the control logic 30, as shown in Figure 2,

A request signal delay unit 31 for outputting a new request signal by delaying the access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20 by a clock signal CLK, and Busy signal generator 32 for generating busy signals BUSY1 and BUSY2 by checking whether or not another processor is accessed according to the request signal delayed by the half-cycle by the request signal delay unit 31, and the busy signals BUSY1 and BUSY2. And OR gates 33 and 34 for logic processing the output of the request signal delay unit 31 and outputting the chip select signals CS1 * and CS2 * to the memory 40, respectively.

The request signal delay unit 31 includes the inverters 31A and 31B for inverting the clock signal CLK and the first processor 10 using the clock signal inverted by the inverter 31A as the clock CLK. The first flip-flop FF1 outputs the delayed access request signal REQ1 * by half a cycle and the clock signal inverted by the inverter 31B is used as a clock CLK to access the second processor 20. The second flip-flop FF2 outputs the request signal REQ2 * with a half cycle delay.

The busy signal generator 32 includes inverters 32A and 32B for inverting the access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20, and the inverted access request. The signal REQ1 is the clock CLK, the inverted access request signal REQ2 is input to the input terminal D3 and the clear terminal CLR, and is logic processed to output the busy signal BUSY2 to the output terminal Q3. 3 flip-flop FF3 and the inverted access request signal REQ2 are the clock CLK, and the inverted access request signal REQ1 is inputted to the input terminal D4 and the clear terminal CLR to be logically processed. The fourth flip-flop FF4 outputs the busy signal BUSY1 to the output terminal Q4.

The memory 40 is composed of DPRAM (Dual Port-RAM).

The communication control logic of the dual processor of the present invention configured as described above will be described with reference to FIGS. 1 to 3 as follows.

First, the first processor 10 access request signal REQ1 * as shown in FIG. 3B for a predetermined period T2-T3 at the falling edge of the clock signal CLK as shown in FIG. Will be output to the control logic 30.

The control logic 30 receives the access request signal REQ1 * of the first processor 10 to determine whether there is an access request signal REQ2 * of another processor, that is, the second processor 20, and performs simultaneous control. Prevent it,

Here, the second processor 20 outputs the access request signal REQ2 * as shown in FIG. 3C to the control logic 30 for a predetermined period T3-T5 at the falling edge of the clock signal CLK. Done.

In this case, the control logic 30 controls the access control signals REQ1 * and REQ2 * of the first and second processors 10 and 20 to simultaneously control the control period T3, thereby selecting the chip select signals CS1 * and CS2. Since *) is output to the memory 40, the memory 40 causes data to be exchanged with the first and second processors 10 and 20 according to the chip select signals CS1 * and CS2 *.

2 is a detailed configuration diagram of the control logic 30,

As shown in FIG. 3A, the clock signal CLK is inverted through the inverters 31A and 32B of the request signal delay unit 31 so that the first flip-flop FF1 and the second flip-flop FF2 are inverted. It is input to the clock stage CLK.

The first flip-flop FF1 receives the access request signal REQ1 * of the first processor 10 as an input terminal D1 and outputs the same to the output terminal Q1 by an inverted clock signal of the clock terminal CLK. The access request signal REQ1 * of the first processor 10 delayed by a half cycle as shown in (d) of FIG. 3 is output.

The inverted access request signal REQ1 is input to the preset PR terminal of the first flip-flop FF1 at the same time as the output of the half-cycle delayed access request signal REQ1 *, thereby receiving the first flip-flop FF1. Will be initialized.

The second flip-flop FF2 receives the access request signal REQ2 * of the second processor 20 to the input terminal D2 and outputs the same to the output terminal Q2 by the inverted clock signal of the clock terminal CLK. The access request signal REQ2 * of the second processor 20 as shown in FIG. 3 (difference) is delayed by half a period.

Subsequently, the inverted access request signal REQ2 is input to the preset terminal PR of the second flip-flop FF2 at the same time as the output of the half-cycle delayed access request signal REQ2 *. Will be initialized.

Meanwhile, the busy signal generator 32 receives the access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20 to receive the busy signal BUSY1 of another processor for preventing simultaneous access. Will output BUSY2.

The access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20 are inverted in the waveforms as shown in FIG. 3 (a) in the inverters 32A and 32B. .

The access request signal REQ1 inverted by the inverter 32A is input to the clock terminal CLK of the third flip flop FF3 and the input terminal D4 and the clear terminal CLR of the fourth flip flop FF4. The access request signal REQ2 inverted by the inverter 32B is input to the input terminal D3 and the clear terminal CLR of the third flip-flop FF3 and the clock terminal CLK of the fourth flip-flop FF4. Is entered.

The third flip-flop FF3 logic-processes the access request signal REQ2 input to the input terminal D3 at the rising edge of the inverted access request signal REQ1 input to the clock terminal CLK and outputs the output terminal Q3. As a result, the busy signal BUSY2 as shown in FIG.

The fourth flip-flop FF4 logically processes the inverted access request signal REQ1 input to the input terminal D4 at the rising edge of the inverted access request signal REQ2 input to the clock terminal CLK. The busy signal BUSY1 of the high signal High is output to the output terminal Q4 in the section T3 as shown in FIG. 3, and at this time, the access request signal is inputted to the clear terminal CLR to generate a predetermined period ( Clear the output in T2).

The oA gate 33 receives the first flip-flop FF1 output of the request signal delay unit 31 to one side and the third flip-flop FF3 output of the busy signal generator 32 to the other side. Logic processing outputs the chip select signal CS1 * of the first processor 10 as shown in FIG.

The oA gate 34 receives the output of the second flip-flop FF2 of the request signal delay unit 31 on one side and the output of the fourth flip-flop FF4 of the busy signal generator 32 on the other side. The logic process outputs the chip select signal CS2 * of the second processor 20 as shown in FIG.

As such, when the first processor 10 and the second processor 20 simultaneously request access, the access request signals REQ1 * and REQ2 * are delayed by a half cycle to check whether the other processor 10 or 20 is accessed. In addition, the signal generated by the processor 10 or 20 to detect the busy signals BUSY1 and BUSY2 of the other processor 10 or 20 is triggered by an access signal requested by the other processor 10 or 20 which is delayed by a half cycle. The signals BUSY1 and BUSY2 are detected.

The busy signals BUSY1 and BUSY2 and the half-cycle delayed access request signal are ORed together with the OR gates 33 and 34 to output the corresponding chip select signals CS1 * and CS2 * to the memory 40.

The memory 40 exchanges data with the first processor 10 by the chip select CS1 * of the control logic 30, and exchanges data with the second processor 20 by the chip select signal CS2 *. Will be

According to the present invention, when two processors simultaneously access an access request signal, the present invention effectively controls the access request signal, thereby preventing data collision, and improving data reliability. .

Claims (3)

First and second processors 10 and 20 for outputting access request signals REQ1 * and REQ2 * for data communication; The control logic 30 determines the access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20 to control simultaneous access and to output corresponding chip select signals CS1 * and CS2 *. And a memory 40 having a DPRAM for exchanging data with the corresponding processors 10 and 20 according to the chip select signals CS1 * and CS2 * of the control logic 30. Communication control logic of the processor. The control logic 30 of claim 1, wherein the control logic 30 outputs the access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20 by a half cycle delay by the clock signal CLK. The busy signal generator 32 generates the busy signals BUSY1 and BUSY2 by checking whether the other processor is accessed according to the request signal delay unit 31 and the request signal delayed by a half cycle from the request signal delay unit 31. OA gates 33 and 34 for logic processing the outputs of the busy signals BUSY1 and BUSY2 and the request signal delay unit 31 to output the chip select signals CS1 * and CS2 * to the memory 40. Communication control logic of a dual processor, characterized in that consisting of. 3. The clock signal generator of claim 2, wherein the request signal delay unit 31 includes a resonator 31A and 31B for inverting the clock signal CLK and a clock signal CLK inverted by the inverter 31A. A first flip-flop FF1 that is inputted to the CLK and receives the access request signal REQ1 * of the first processor 10 as an input terminal, and outputs the delayed half-cycle by outputting the logic request. A second flip-flop (FF2) which outputs the inverted clock signal CLK as the clock stage CLK and delays and outputs the access request signal REQ2 * of the second processor 20 by a half cycle. The busy signal generator 32 includes inverters 32A and 32B for inverting the access request signals REQ1 * and REQ2 * of the first and second processors 10 and 20, and the inverted request signal. The clock signal CLK and the inverted request signal REQ2 * are inputted to the input terminal D3 and the clear terminal CLR to perform logic processing to output the busy signal BUSY2 to the output terminal Q3. The third flip-flop FF3 and the inverted request signal REQ2 are the clock CLK, and the inverted request signal REQ1 is inputted to the input terminal D4 and the clear terminal CLR, and logically processed. And a fourth flip-flop FF4 for outputting the busy signal BUSY1 to Q4).