KR100586070B1 - Control circuit of semiconductor memory source - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a control circuit of a semiconductor memory device for optimizing the processing speed of a synchronous memory device having a programmable latency period and controlling the same. An apparatus for accessing a memory array portion designated by a column address, comprising: a column address buffer latch unit for latching and outputting a column address; a column address decoder for decoding and outputting a latched and output column address; A CAS latency delay unit for adjusting a column address latching time set by the internal clock iclk and the decoded signal ay01 of the first two addresses; a column address latching time adjustment signal b and a column of the CAS latency delay unit; Decoding Scene of Address Decoder 200 It is configured to include a column select signal processor for the latching, and the control for the column selected by the (a).

SDRAM, CAS Latency

Description

CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY SOURCE}             

1 is a block diagram illustrating a control circuit of a semiconductor memory device according to the present invention.

2 is a detailed block diagram of a CAS latency delay unit and a column select signal processor;

3A and 3B are operation timing diagrams of a control circuit according to the present invention.

-Explanation of symbols for the main parts of the drawing-

100. Column address buffer latch unit 200. Column address decoder

300. CAS latency delay unit 400. Column selection signal processing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a circuit optimization of a processing speed of a synchronous memory device having a programmable latency period and a control circuit of the semiconductor memory device for controlling the same.

Synchronous dynamic random access momory (SDRAM) is designed to operate in a synchronous memory system.

That is, the input and output signals, except for the clock enable while in the self-refresh mode and power off state, are synchronized to the edge of the system clock.

SDRAM offers an excellent advantage in dynamic memory operation performance.

The development of SDRAM also depends on how the data is synchronously bursted at high data rates, and SDRAM has programmable features such as READ latency periods.

Programmable READ latency typically has a configuration of one, two or three clocks.

The READ latency determines which cycle period is available regardless of clock transfer (tCLK) after the READ command is initiated.

Frequency-dependent data is made available at the output with one clock cycle less than the READ latency.

For example, if the read latency with one cycle period longer than the minimum access time (tAA) from the read command is two clock cycles, it will provide data immediately after the first clock cycle, but the data will be programmed READ. Since the latency is two clock cycles, it is valid until after the second clock cycle.

Programmable READ latency is effectively used in memory systems with SDRAM having different system clock frequencies.

For example, if tCK of SDRAM is 10ns (100Mhz) and the READ latency is 3 clock cycles, the first valid data is output between the second clock cycle (20ns) and the third clock cycle (30ns) after the READ command.

The data is valid until after the third clock cycle (30 ns). Also, if the CK latency for the memory system is set to 2 clocks with 15ns (66Mhz), the first valid data is obtained between the first clock cycle (15ns) and the second clock cycle (30ns) after the READ command. .

However, if the READ latency is programmed to 3, valid data will remain up to the third clock cycle (45ns), making time use inefficient.

In critical SDRAM, the two critical parameters are tRCD (active command-READ / WRITE command) and tAA (READ / WRITE command-data output), and the typical one assigns 3 system cycles to tRCD and tAA, At the clock frequency, each can be locked in two system clock cycles.

Their total memory access time is 6 clock cycles and 4 clock cycles, respectively.

Such a control apparatus of a semiconductor memory device of the prior art has the following problems.

There is always a need for minimizing the time for memory access time, and there is a demand for a method that can reduce the memory access time of the system without tRCD and tAA affecting the system operation. can not do.

That is, there is a problem that does not satisfy the requirement of optimizing the speed path for SDRAM with a programmable READ latency that minimizes the time requirement for memory access.

SUMMARY OF THE INVENTION The present invention is to solve such a problem of a control circuit of a semiconductor device of the prior art, which is a path optimization of a processing speed of a synchronous memory device having a programmable latency period and a control circuit of a semiconductor memory device for controlling the same. The purpose is to provide.

The control circuit of the semiconductor memory device according to the present invention for achieving the above object is operated in synchronization with the system clock and in the apparatus for accessing the portion of the memory array specified by the row address and column address (column address) A column address buffer latch unit for latching and outputting a column address; a column address decoder for decoding and outputting a latched and output column address; a decoded signal of the first two addresses among a latency signal, an internal clock (iclk), and a column address (ay01); A CAS latency delay unit for adjusting the column address latching timing set by (C); a column address latching timing adjustment signal (b) of the CAS latency delay unit and a decoding signal (a) of the column address decoder (200) for column selection Including a column select signal processor for latching and controlling Characterized in that made.

Hereinafter, a control circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a control circuit of a semiconductor memory device according to the present invention, and FIG. 2 is a detailed block diagram of a CAS latency delay unit and a column select signal processor.

The present invention is to optimize the speed path of an access operation in an SDRAM with a programmable latency period.

It is possible to adjust the available time after column address decoding to provide additional time for other time elements or parameters for memory access, such as row address decoding, which is assigned fewer clock cycles.

As shown in FIG. 1, the column address buffer latch unit 100 latches and outputs a column address, a column address decoder 200 which decodes and outputs a column address that is latched, and outputs a latency signal and an internal clock. (iclk) and the CAS latency delay adjusting the column address latching time set by the decoded signal ay01 by receiving the logic values of the first two addresses 0 and 1 among the column addresses output from the column address decoder 200. A column selection for latching and controlling for column selection by the unit 300, a column address latching timing adjustment signal b of the CAS latency delay unit 300, and a decoding signal a of the column address decoder 200. It is configured to include a signal processor 400.

The detailed configuration of the control circuit configured as described above is the same as in FIG.

First, the CAS latency delay unit 300 receives the logic values of the first two addresses 0 and 1 from the internal clock iclk and the column address, respectively, and performs a logic operation on the decoded signal ay01. And an inverter 20 for inverting the output signal of the first NAND gate 10, a second NAND gate 30 for calculating an inversion signal and a latency signal of the inverter 20, and the first and the second, respectively. It consists of a NOR gate 40 which calculates the output signal of the NAND gates 10 and 30 and outputs the column address latching timing adjustment signal b.

The column select signal processor 400 logics the first and second inverters 60 and 70 for latching the decoded column address signal a, the latched column address signal, and the column address latching timing adjustment signal b. Calculates the NAND gate 50 for calculating, the third inverter 80 for inverting the output signal of the NAND gate 50, the output signal of the NAND gate 50 and the output signal of the third inverter 80 And a NOR gate 90 for outputting the column select signal Yi.

The address latching time adjustment operation of the semiconductor memory device having the above configuration will be described below.

3A and 3B are operation timing diagrams of a control circuit according to the present invention.

The present invention reduces the clock cycles assigned to a particular time parameter during the clock cycles required for memory access and compensates for the excessive time allocated to other parameters through the same parameter.

In SDRAM, column address latching is always fixed by system specifications and the clock latency is varied by 1,2,3, cycles.

Therefore, the time of column address latching does not change, but may be changed as follows when the control circuit of the present invention is applied to optimize the total access time using the time after column address decoding.

That is, tRCD becomes an important time element when the time tRCD of row address latching and column address latching is reduced or optimized.

The optimization circuit of the present invention slows down the time after column decoding to provide additional time for this tRCD so that this time reduction is possible.

The present invention is to optimize the overall access time by controlling the timing of the column address selection signal in the SDRAM. First, the column address buffer latch unit 100 buffers and latches the column address to the column address decoder 200. A signal is generated to decode and select a column suitable for the decoding. At this time, the latency signal coming into the CAS latency delay unit 300 has information of a latency period, which is composed of how many system cycles.

The internal clock iclk is a pulse generated from an external clock and used internally. The decoded signal ay01 is a signal decoded by receiving the logic values of the first two addresses 0 and 1 among the column addresses.

If the specific latency signal is high (logical value 1) in the CAS latency delay unit 300, the CAS latency delay unit 300 is activated.

The internal clock iclk, the pre-decoded address 0 and the address 1 (ay01) are combined to delay the transition of the synchronized signal from Low to High.

At this time, the column select signal processing unit 400 latches the column select signal in the first and second inverters 60 and 70 which latch the decoded column address signal a, and when the " b " When the two inputs of 50) transition to the high state, the output goes to the low state. The input of the NOR gate 90 side of the third inverter 80 transitions to the high state again, so that the output of the NOR gate 90 becomes an appropriate pulse.

Therefore, when the internal clock iclk and the decoding signal ay01 of the CAS latency delay unit 300 are input to High, the signal is converted to a High signal through the inverter 20 so that another input of the NOR gate 40 is connected to the first NAND gate. The signal 10 is directly received and the output " b " signal is delayed while passing through the inverter 20, the second NAND gate 30, and the NOR gate 40 from the high state to the low state.

As shown in FIGS. 3A and 3B, when the system clock frequency is lowered and the READ latency is long, a more deterministic speed path (tRCD) using an internal clock, one predecoded signal, and a latency signal to match the frequency is used. You can reduce the overall access time by reducing or optimizing.

 Such a control circuit of a semiconductor memory device according to the present invention has the following effects.

The improved memory device delays the address decoded signal to compensate tRCD from the enable signal of column address latching and the available time up to tAA when tRCD, the time between row address latching and column address latching, is the critical parameter. Has the effect of compensating for the shortening.

Claims (3)

In a device that operates in synchronization with the system clock and accesses a portion of the memory array specified by row addresses and column addresses, A column address buffer latch unit for latching and outputting a column address; A column address decoder for decoding and outputting the latched and output column address; A CAS latency delay unit for adjusting the column address latching time set by the decoded signal ay01 of the first two addresses among the latency signal, the internal clock iclk, and the column address; And a column selection signal processing unit for latching and controlling column selection by the column address latching timing adjustment signal (b) of the CAS latency delay unit and the decoding signal (a) of the column address decoder 200. A control circuit of a semiconductor memory device. The method of claim 1, wherein the CAS latency delay unit comprises: a first NAND gate configured to logically operate on the decoded signal ay01 by receiving the logic values of the first two addresses 0 and 1 from the internal clock iclk and the column address; An inverter for inverting an output signal of the first NAND gate; A second NAND gate for calculating an inverted signal and a latency signal of the inverter; And a NOR gate for outputting the column address latching timing adjustment signal (b) by calculating the output signals of the first and second NAND gates. The method of claim 1, wherein the column select signal processor comprises: first and second inverters for latching the decoded column address signal (a); A NAND gate for logically operating the latched column address signal and the column address latching timing adjustment signal (b); A third inverter for inverting the output signal of the NAND gate; And a NOR gate configured to calculate an output signal of the NAND gate and an output signal of a third inverter to output a column select signal (Yi).

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