KR20080062707A - Data output circuit - Google Patents

Abstract

A data output circuit is provided to prevent distortion in data transmitted to a data pad(DQ pad), by preventing a rising clock and a falling clock from being enabled at the same time. A data clock control part(15) receives a first and a second clock signal and then controls pulse width of the first and the second clock signal. A data latch part(17) outputs data latched by being synchronized to the first and the second clock signal with controlled pulse width. The data clock control part decreases pulse width of the first and the second clock signal. The data clock control part includes a first delay part delaying the first clock signal and a first logic part performing NOR operation of the first clock signal and an output signal of the delay part.

Description

Data Output Circuit

1 shows a configuration of a data output circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a first embodiment of a data clock control unit included in FIG. 1.

3 is a circuit diagram of a second embodiment of the data clock control unit included in FIG. 2.

FIG. 4 is a circuit diagram of a first embodiment of a data latch unit included in FIG. 2.

FIG. 5 is a circuit diagram of a second embodiment of a data latch unit included in FIG. 2.

6 is an internal signal timing diagram of a data output circuit according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output circuit, and more particularly, to a data output circuit that can prevent distortion of data output during high frequency operation of a semiconductor device.

In general, a data output circuit of a DRAM includes a rising clock rclk made at the rising edge of the internal clock iCLK and a falling clock made at the falling edge of the internal clock iCLK. (fclk) is input, and the latched data iData is synchronized with the rising clock rclk and the falling clock fclk to transfer to the data pad DQ Pad. This operation is performed in the data latch unit included in the data output circuit. In the process of transmitting the rising clock rclk and the falling clock fclk to the data latch unit, the rising clock rclk and the falling clock fclk The waveform will change.

In particular, in a high frequency operation, an operation speed of a semiconductor device is determined according to how fast data iData can be transferred to a data pad DQ pad after a read command. Therefore, it is necessary to quickly adjust the rising clock rclk or the falling clock fclk input to the data latch unit, and one of the design methods used for this is a rising fast design method.

However, when designing in a rising fast manner, the falling time is shortened but the falling time is slowed down. As a result, the pulse widths of the rising clock rclk and the falling clock fclk are reduced. This lengthening phenomenon occurs. Particularly, when the pulse widths of the rising clock rclk and the falling clock fclk become larger than 1/2 tCK, there is a section in which the rising clock rclk and the falling clock fclk are simultaneously enabled, and thus the data pad DQ. Distortion occurs in the data transmitted to the pad).

Therefore, the technical problem to be achieved by the present invention is to adjust the pulse width of the rising clock (rclk) and falling clock (fclk) during the high frequency operation of the semiconductor device, the rising clock (rclk) and falling clock (fclk) is enabled at the same time The present invention provides a data output circuit capable of preventing distortion from occurring in data transmitted to a data pad (DQ Pad).

In order to achieve the above technical problem, the present invention includes a data clock control unit for receiving the first and second clock signal, and adjusts the pulse width of the first and second clock signal; And a data latch unit for outputting latched data in synchronization with the first and second clock signals having the pulse width adjusted.

In the present invention, it is preferable that the data clock control unit output the reduced pulse widths of the first and second clock signals.

In the present invention, the data clock control unit includes a first delay unit for delaying the first clock signal by a predetermined period; And a first logic unit configured to logically output the first clock signal and an output signal of the delay unit.

In the present invention, the data clock control unit includes a second delay unit for delaying the second clock signal by a predetermined period; And a second logic unit configured to logically output the second clock signal and an output signal of the delay unit.

In the present invention, it is preferable that the first and second delay units are inverter chains.

In the present invention, it is preferable that the first and second logic units perform a negative logical sum operation.

In the present invention, it is preferable that the first and second logic units perform an AND operation.

The data latch unit may include: a first buffer configured to buffer first data in response to the first clock signal; A second buffer buffering second data in response to the second clock signal; And a latch for latching output signals of the first and second buffers.

The data latch unit may include: a first transfer device configured to transfer first data in response to the first clock signal; And a second transfer element transferring second data in response to the second clock signal.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

1 shows a configuration of a data output circuit according to an embodiment of the present invention.

As shown, the data output circuit according to an embodiment of the present invention receives the external commands (CLK, CKE, CSB, RASB, CASB, WEB) through the input terminal 10, decodes the read command ( A command decoder 11 (Command Decorder) for generating Read Command and Write Command; A mode register 13 which receives an address signal Address through an input terminal 12 and generates BL and CL commands; A rising clock rclk generated in synchronization with a rising edge of the clock signal ICLK by receiving an internal clock ICLK, a read command and a write command, and a BL and CL command first and second clock signals; And a clock control block 14 that generates a falling clock fclk generated in synchronization with the falling edge of the clock signal ICLK.

In addition, the data output circuit according to an embodiment of the present invention receives the rising clock (rclk) and falling clock (fclk), the data for generating the rising clock (rclk) and falling clock (fclk) of the pulse width is adjusted A clock controller 15 (Data Colck Control) and; The data iData stored in the DRAM core 16 area is latched, and the latched data rData and fData are output as an output signal out in synchronization with the rising clock rclk and the falling clock rclk. And a data latch 17 for transmitting the data to the data output terminal 19 (DQ Pad) via a driver 18.

Hereinafter, the configuration and operation of the data clock control unit 15 of the present embodiment will be described in detail with reference to FIGS. 2 and 3. 2 is a circuit diagram of a first embodiment of the data clock control unit 15, and FIG. 3 is a circuit diagram of a second embodiment of the data clock control unit 15. As shown in FIG.

As shown in FIG. 2, the data clock control unit 15 delays and outputs the inverter IV20 buffering the first rising clock rclk and the output signal of the inverter IV20 during the first delay period. The delay unit 22 and the NOR gate NR20 for receiving the output signal of the inverter IV20 and the output signal of the delay unit 22 to perform a negative logic sum operation to generate a second rising clock rclk_p. .

In addition, the data clock control unit 15 includes an inverter IV22 buffering the first falling clock fclk, a delay unit 24 for delaying and outputting the output signal of the inverter IV22 during the second delay period, The NOR gate NR22 is configured to receive the output signal of the inverter IV22 and the output signal of the delay unit 24 to perform a negative logic sum operation to generate a second falling clock fclk_p.

As described above, the second rising clock rclk_p generated by the configured data clock controller 15 is delayed by the first delay period when the second rising clock rclk_p transitions from the low level to the high level. Therefore, the pulse width of the second rising clock rclk_p is reduced by the first delay period than the first rising clock rclk. Looking at this in detail. When the first rising clock rclk is at a low level, a high level is input to one end of the NOR gate NR20, and the second rising clock rclk_p is at a low level. Thereafter, when the first rising clock rclk transitions to a high level, a low level is input to one end of the NOR gate NR20 during the first delay period, but an output signal of the delay unit 22 is input to the other end of the NOR gate NR20. That is, since the high level is input, the second rising clock rclk_p maintains the low level. When the first delay period passes after the first rising clock rclk transitions to the high level, the output signal of the delay unit 22 also transitions to the low level, so the second rising clock rclk_p transitions to the high level. Thereafter, when the first rising clock rclk transitions to a low level, the second rising clock rclk_p immediately transitions to a low level.

Similarly, the second falling clock fclk_p generated by the clock controller 15 is delayed from the low level to the high level compared to the first falling clock fclk by the second delay period of the delay unit 24. do. Therefore, the pulse width of the second falling clock fclk_p is reduced by a second delay period than the first falling clock fclk.

As shown in FIG. 3, the data clock control unit 15 includes a delay unit 32 for delaying and outputting the first rising clock rclk during the third delay period, and a first rising clock rclk and the delay unit. And a NAND gate ND30 and an inverter IV30 configured to receive the output signal 30 and perform an AND operation.

In addition, the data clock control unit 15 delays the first falling clock fclk during the fourth delay period and outputs the delayed signal 34, and output signals of the first falling clock fclk and the delayed 34. And a NAND gate ND32 and an inverter IV32 configured to perform an AND operation.

As described above, the second rising clock rclk_p generated by the configured data clock control unit 15 is delayed by the third delay period when the second rising clock rclk_p transitions from the low level to the high level. Therefore, the pulse width of the second rising clock rclk_p is reduced by a third delay period than the first rising clock rclk. Looking at this in detail. When the first rising clock rclk is at a low level, a low level is input to one end of the logic unit 32, and the second rising clock rclk_p is at a low level. Subsequently, when the first rising clock rclk transitions to a high level, a high level is input to one end of the NAND gate ND30 during the third delay period, but is output from the delay unit 32 at the other end of the NAND gate ND30. Since the low level is input, the second rising clock rclk_p maintains the low level. When the first delay period elapses after the first rising clock rclk transitions to the high level, the output signal of the delay unit 32 also transitions to the high level, so the second rising clock rclk_p transitions to the high level. Thereafter, when the first rising clock rclk transitions to a low level, the second rising clock rclk_p immediately transitions to a low level.

Similarly, the second falling clock fclk_p generated by the clock controller 15 is delayed from the low level to the high level compared to the first falling clock fclk by the fourth delay period of the delay unit 34. do. Therefore, the pulse width of the second falling clock fclk_p is reduced by a fourth delay period than the first falling clock fclk.

Hereinafter, the configuration and operation of the data latch unit 17 of the present embodiment will be described in detail with reference to FIGS. 4 and 5. 4 is a circuit diagram of the first embodiment of the data latch unit 17, and FIG. 5 is a circuit diagram of the second embodiment of the data latch unit 17. As shown in FIG.

The data latch unit 17 according to the present exemplary embodiment receives a data iData stored in a DRAM core 16 (DRAM CORE) area and latches the latch by dividing it into first data rData and second data fData. And an output unit configured to output the first data rData and the second data fData in synchronization with the second rising clock rclk_p and the second falling clock fclk_p, respectively.

As shown in FIG. 4, the NMOS and PMOS transistors P40 and NMOS enable the buffer 40 in synchronization with the buffer 40 for buffering the first data rData and the second rising clock rclk_p. A transistor N42 is provided. In addition, the output unit includes a buffer 42 for buffering the second data fData, a PMOS transistor P44 for enabling the buffer 42 in synchronization with the second falling clock fclk_p, and an NMOS transistor N46. . The output section includes a buffer 44 and a latch 44 for latching the output signal of the buffer 42.

The output unit configured as described above transfers the first data rData to the output signal out through the buffer 40 and the latch 44 when the second rising clock rclk_p is enabled at a high level, and the second falling clock. When (fclk_p) is enabled at the high level, the second data fData is transferred to the output signal out through the buffer 42 and the latch 44.

As shown in FIG. 5, the output unit is coupled to the transfer element T1 that transfers the first data rData as an output signal out in synchronization with the second rising clock rclk_p and the second falling clock fclk_p. And a transfer element T2 for synchronously transferring the second data fData as an output signal out. The output section includes a buffer 50 for buffering the output signal out.

The output unit configured as described above transfers the first data rData to the output signal out through the transfer gate T1 when the second rising clock rclk_p is enabled at a high level, and the second falling clock fclk_p. When enabled at this high level, the second data fData is transferred to the output signal out through the transfer gate T2.

6 shows an internal signal timing diagram of a data output circuit according to an embodiment of the present invention.

As shown, the data output circuit according to the present embodiment has a first rising clock rclk in which the pulse width becomes larger than 1/2 tCK by the rising fast design method through the data clock control unit 15. And the pulse widths of the first falling clock fclk are adjusted to generate the second rising clock rclk_p and the second falling clock fclk_p. The second rising clock rclk_p and the second falling clock fclk_p are signals having a pulse width of 1/2 tCK or less, and unlike the first rising clock rclk and the first falling clock fclk, the enable period is different. The overlapping phenomenon X does not occur. That is, as shown in (Y), since the enable period of the second rising clock rclk_p and the second falling clock fclk_p is formed separately, distortion is not generated in the output signal out transmitted to the data pad 19. Can be prevented from occurring.

As described above, the data output circuit according to the present invention adjusts the pulse width of the rising clock rclk and the falling clock fclk during the high frequency operation of the semiconductor device, so that the rising clock rclk and the falling clock fclk are simultaneously By preventing it from being enabled, there is an effect of preventing distortion in the data transferred to the data pad (DQ Pad).

Claims (12)

A data clock controller which receives the first and second clock signals and adjusts and outputs pulse widths of the first and second clock signals; And And a data latch unit for outputting latched data in synchronization with the first and second clock signals whose pulse width is adjusted. The data output circuit of claim 1, wherein the data clock control unit reduces and outputs pulse widths of the first and second clock signals. The method of claim 1, wherein the data clock control unit A first delay unit delaying the first clock signal by a predetermined period; And And a first logic unit configured to logically output the first clock signal and an output signal of the delay unit. 4. The data output circuit according to claim 3, wherein the first delay unit is an inverter chain. 4. The data output circuit of claim 3, wherein the first logic unit performs a negative logic sum operation. 4. The data output circuit of claim 3, wherein the first logic unit performs an AND operation. The method of claim 3, wherein the data clock control unit A second delay unit delaying the second clock signal by a predetermined period; And And a second logic unit configured to logically output the second clock signal and the output signal of the delay unit. 8. The data output circuit according to claim 7, wherein the second delay unit is an inverter chain. 8. The data output circuit according to claim 7, wherein the second logic unit performs a negative logic sum operation. 8. The data output circuit of claim 7, wherein the second logic unit performs an AND operation. The method of claim 1, wherein the data latch unit A first buffer buffering first data in response to the first clock signal; A second buffer buffering second data in response to the second clock signal; And And a latch for latching output signals of the first and second buffers. The method of claim 1, wherein the data latch unit A first transfer element transferring first data in response to the first clock signal; And a second transfer element transferring second data in response to the second clock signal.

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