KR100529039B1 - Semiconductor memory device with increased domain crossing margin - Google Patents

Semiconductor memory device with increased domain crossing margin Download PDF

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KR100529039B1
KR100529039B1 KR10-2003-0051021A KR20030051021A KR100529039B1 KR 100529039 B1 KR100529039 B1 KR 100529039B1 KR 20030051021 A KR20030051021 A KR 20030051021A KR 100529039 B1 KR100529039 B1 KR 100529039B1
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signal
additive latency
read
output enable
end signal
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KR20050011945A (en
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윤영진
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주식회사 하이닉스반도체
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    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation

Abstract

본 발명은 도메인크로싱 마진을 증가시킬 수 있는 반도체 메모리 소자를 제공하기 위한 것으로, 이를 위한 본 발명으로 커맨드를 디코딩하여 읽기카스신호를 생성하기 위한 커맨드 디코더; 상기 읽기카스신호를 입력 받아 애디티브레이턴시 종료신호를 생성하기 위한 애디티브레이턴시 종료신호 생성부; 및 상기 읽기카스신호를 입력 받아 상기 애디티브레이턴시 종료신호의 활성화 시점 이전에 도메인크로싱을 완료하고, 상기 애디티브레이턴시 종료신호의 활성화 시점 이후에 다양한 카스레이턴시에 대응하는 다수의 데이터출력 인에이블신호를 생성하기 위한 데이터출력 인에이블신호 생성부를 구비하는 반도체 메모리 소자를 제공한다.The present invention provides a semiconductor memory device capable of increasing a domain crossing margin. The present invention provides a command decoder for decoding a command to generate a read casing signal; An additive latency end signal generation unit configured to receive the read cascade signal and generate an additive latency end signal; And receiving the read cascade signal to complete domain crossing before the activation time of the additive latency end signal, and to output a plurality of data output enable signals corresponding to various cascadance times after the activation time of the additive latency end signal. A semiconductor memory device having a data output enable signal generator for generation is provided.

Description

도메인 크로싱 마진을 증가시킨 반도체 메모리 소자{SEMICONDUCTOR MEMORY DEVICE WITH INCREASED DOMAIN CROSSING MARGIN}Semiconductor memory devices with increased domain crossing margins {SEMICONDUCTOR MEMORY DEVICE WITH INCREASED DOMAIN CROSSING MARGIN}

본 발명은 반도체 설계 기술에 관한 것으로, 특히 출력인에이블신호의 생성에 관한 것이며, 더 자세히는 도메인크로싱 마진을 증가시킬 수 있는 반도체 메모리 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to the generation of output enable signals, and more particularly to semiconductor memory devices capable of increasing domain crossing margins.

일반적으로, DDR II SDRAM은 외부적으로는 커맨드를 연속적으로 인가받을 수 있지만, 입력받은 커맨드를 바로 수행하는 것은 아니다. 읽기동작의 경우, 읽기동작의 수행을 위해서는 읽기카스신호가 활성화 되어야 하는데, DDR II에서는 이 읽기카스신호의 활성화 시점을 지연시킴으로써, 연속된 커맨드의 수행을 위한 시간을 내부적으로 확보한다. 인가된 읽기커맨드에 의해서 내부 동작을 제어하는 읽기카스신호가 활성화되기까지의 지연시간을 애디티브레이턴시(Additive Latency : AL)라고 하며, 이 동안에는 반도체 메모리 소자는 아무런 동작도 수행하지 않는다. 또한, 애디티브레이턴시에 의해 활성화된 읽기카스신호로 부터 유효한 데이터가 출력될 때 까지 걸리는 시간이 카스레이턴시(Cas Latency : CL)이다. 즉, 읽기커맨드가 인가되고 내부 데이터가 출력될 때까지 걸리는 리드 레이턴시(Read Latency)는 애디티브레이턴시와 카스레이턴시의 합이 된다. In general, the DDR II SDRAM can receive commands continuously externally, but does not directly execute the received commands. In the case of the read operation, the read cascade signal must be activated in order to perform the read operation. In the DDR II, the time for activating the read cascade signal is delayed, thereby internally securing a time for executing a continuous command. The delay time until the read cascade signal, which controls the internal operation by the applied read command, is activated is called additive latency (AL), during which the semiconductor memory device does not perform any operation. In addition, the time taken from the read cascade signal activated by the additive latency until the valid data is output is the cas latency (CL). That is, the read latency required until the read command is applied and the internal data is output is the sum of the additive latency and the cascade latency.

도 1은 종래기술에 따른 출력인에이블신호 생성패스의 블록 구성도이다.1 is a block diagram of an output enable signal generation path according to the prior art.

도 1을 참조하면, 종래기술에 따른 출력인에이블신호 생성패스의 블록은 외부커맨드를 입력받기 위한 입력버퍼(10)와, 입력버퍼(10)의 출력신호를 입력으로 하여 읽기신호(rd)를 생성하기 위한 커맨드 디코더(11)와, 읽기신호(rd)를 입력으로 하여 애디티브레이턴시 이후 읽기카스신호(casp_rd)를 생성하기 위한 카스신호생성부(12)와, 읽기카스신호(casp_rd)를 입력으로 하여 지연고정루프의 클럭(rclk_dll 및 fclk_dll)에 동기시켜 여러 지연시간을 갖는 데이터 출력 인에이블신호(oe)를 생성하기 위한 데이터 출력 인에이블신호 생성부(13)를 구비한다.Referring to FIG. 1, the block of the output enable signal generation path according to the related art is an input buffer 10 for receiving an external command and an output signal of the input buffer 10 as an input to read a read signal rd. The command decoder 11 for generating, the read signal rd is input, and the cas signal generator 12 for generating the read cas signal signal casp_rd after the additive latency is input, and the read cas signal signal casp_rd is input. Thus, a data output enable signal generator 13 for generating a data output enable signal oe having various delay times in synchronization with the clocks rclk_dll and fclk_dll of the delay locked loop is provided.

도 2는 도 1의 데이터 출력인에이블신호 생성부(13)의 세부 회로도이다.FIG. 2 is a detailed circuit diagram of the data output enable signal generator 13 of FIG. 1.

도 2를 참조하면, 데이터 출력인에이블신호 생성부(13)는 읽기카스신호(casp_rd)을 입력으로 하여 내부클럭(iclk)에 동기된 데이터 출력인에이블신호(oe00)를 생성하기 위한 래치(20)와, 데이터 출력인에이블신호(oe00)를 지연고정루프의 라이징에지클럭(rclk_dll) 또는 내부클럭(iclk)에 동기된 데이터 출력인에이블신호(oe10)로 출력하기 위한 레지스터(21)와, 데이터 출력신호인에이블신호(oe10)를 지연고정루프의 클럭(fclk_dll 및 rclk_dll)에 동기시켜 다양한 카스레이턴시에 대응하는 데이터 출력인에이블신호(oe15, oe20, oe25, oe30, …)를 생성하기 위한 레지스터블록(22)를 구비한다.Referring to FIG. 2, the data output enable signal generator 13 receives a read cascade signal casp_rd as an input and generates a latch 20 for generating a data output enable signal oe00 synchronized with an internal clock iclk. And a register 21 for outputting the data output enable signal oe00 as a data output enable signal oe10 in synchronization with the rising edge clock rclk_dll or the internal clock iclk of the delay locked loop. A register block for generating data output enable signals oe15, oe20, oe25, oe30, ... corresponding to various cascade latencies by synchronizing the output signal enable signal oe10 with the clocks fclk_dll and rclk_dll of the delay locked loop. 22).

그리고 레지스터블록(22)은 데이터 출력인에이블신호(oe10)를 지연고정루프의 클럭(rclk_dll 및 fclk_dll)에 동기시켜 다양한 카스레이턴시에 대앙하는 다수의 데이터 출력인에이블신호(oe15, oe20, oe25, oe30, …)를 생성하기 위한 다수개의 쉬프터 레지스터로 구성된다.In addition, the register block 22 synchronizes the data output enable signal oe10 with the clocks rclk_dll and fclk_dll of the delay locked loop, thereby providing a plurality of data output enable signals oe15, oe20, oe25, and oe30 for various cascade latencies. , ...) is composed of a plurality of shifter registers.

다음으로, 도 1및 도 2를 참조하여 종래기술에 따른 출력인에이블신호 생성패스의 블록의 전체적 동작을 살펴본다.Next, the overall operation of the block of the output enable signal generation path according to the prior art will be described with reference to FIGS. 1 and 2.

먼저, 외부입력신호(/CS, /RAS, /CAS, /WE)가 입력버퍼(10)를 통해 버퍼링되어 커맨드디코더(11)를 통해 읽기신호(rd)로 활성화되고, 이는 카스신호생성부(12)를 통해 내부클럭(iclk)을 기준으로 애디티브레이턴시 만큼의 지연 후 읽기카스신호(casp_rd)로 활성화 된다. 이어 래치(20)는 읽기카스신호(casp_rd)를 입력으로 하여 데이터출력인에이블신호(oe00)를 생성하고, 레지스터(21)에서는 데이터출력인에이블신호(oe00)를 입력으로 하여, 저주파의 경우에는 입력되는 지연고정루프의 라이징에지클럭(rclk_dll)에 동기시켜 데이터출력인에이블신호(oe10)를 출력시키고, 고주파의 경우에는 한 주기 뒤에 입력되는 내부클럭(iclk)에 동기시켜 데이터 출력인에이블신호(oe10)를 출력시킨다. 레지스터 블록(22)은 데이터출력인에이블신호(oe10)를 입력으로 하여 지연고정루프의 클럭(rclk_dll 및 fclk_dll)에 동기된 다양한 카스레이턴시에 대응되는 데이터 출력인에이블신호(oe15, oe20, oe25 oe30, …)를 생성한다.First, the external input signals / CS, / RAS, / CAS, / WE are buffered through the input buffer 10 and activated as a read signal rd through the command decoder 11, which is a cas signal generator ( 12) after the delay by the additive latency based on the internal clock iclk, the read cas signal (casp_rd) is activated. The latch 20 then inputs the read casing signal casp_rd to generate the data output enable signal oe00. The register 21 receives the data output enable signal oe00 as an input. The data output enable signal oe10 is output in synchronization with the rising edge clock rclk_dll of the delayed fixed loop input, and in the case of a high frequency signal, the data output enable signal is synchronized with the internal clock iclk input one cycle later. output oe10). The register block 22 receives data output enable signals oe10 as inputs, and corresponding data output enable signals oe15, oe20, oe25 oe30, corresponding to various cascade latencies synchronized with the clocks rclk_dll and fclk_dll of the delay locked loop. ...)

아울러, 데이터 출력인에이블신호(oe15, oe20, oe25 oe30, …)들 중 모드레지스터(MRS)에 설정된 카스레이턴시을 만족시킬 수 있는 지연시간을 갖는 신호를 선택하여 출력인에이블신호(outen)로써 데이터출력 때 사용된다. In addition, among the data output enable signals oe15, oe20, oe25 oe30, ..., a signal having a delay time that satisfies the cascade latency set in the mode register MRS is selected to output the data as an output enable signal outen. When used.

그리고, 레지스터(21)는 데이터 출력인에이블신호(oe00)를 반도체 메모리 소자의 동작 주파수에 따라 지연고정루프의 클럭 (rclk_dll)또는 내부클럭(iclk)에 동기시키는 동작을 수행하는데, 이는 고주파수 동작시 내부클럭(iclk)에 비해 지연고정루프의 클럭(rclk_dll)의 인이에블 되는 시점이 빠르기 때문에 일어나는 오동작을 방지하기 위한 것이다.The register 21 synchronizes the data output enable signal oe00 with the clock rclk_dll or the internal clock iclk of the delay locked loop according to the operating frequency of the semiconductor memory device. This is to prevent malfunctions that occur because the timing at which the clock clock rclk_dll of the delay locked loop is enabled is faster than the internal clock iclk.

또한, 내부클럭(iclk)에 동기된 데이터출력 인에이블신호를 지연고정루프의 클럭(rclk_dll 또는 fclk_dll)에 동기시키는 것을 축 바꿈, 즉 도메인 크로싱(domain crossing) 이라고 하는데, 실 회로에서 데이터 출력인에이블신호를 클럭에 동기시켜 출력시키는데 회로자체의 지연이 있으므로 반도체 메모리 소자의 동작 주파수가 빨라짐에 따라 도메인 크로싱을 하기가 어려워진다.In addition, synchronizing the data output enable signal synchronized with the internal clock iclk to the clock of the delay locked loop (rclk_dll or fclk_dll) is referred to as axis switching, that is, domain crossing. Since there is a delay in the circuit itself in synchronizing the signal with the clock and outputting the signal, it is difficult to perform domain crossing as the operating frequency of the semiconductor memory device is increased.

참고적으로, 읽기신호(rd)는 라스신호(/RAS)와 쓰기신호(/WE)가 논리레벨 하이를 갖고, 칩선택신호(/CS)와 카스신호(/CAS)가 논리레벨 로우를 갖을 때 활성화된다.For reference, in the read signal rd, the ras signal / RAS and the write signal / WE have a logic level high, and the chip select signal / CS and the cas signal / CAS have a logic level low. When activated.

한편, 이러한 종래기술을 이용하는 경우 내부클럭에 동기된 데이터 출력인에이블신호를 지연고정루프의 클럭에 동기시켜 출력하는데 걸리는 시간이 줄어들어 도메인크로싱 마진이 짧아진다. On the other hand, when using this conventional technology, the time taken to output the data output enable signal synchronized with the internal clock in synchronization with the clock of the delay locked loop is reduced, thereby shortening the domain crossing margin.

이는 반도체 메모리 장치의 동작주파수가 증가함에 따라 카스레이턴시 자체가 변하는 것은 아니나, 카스레이턴시가 클럭을 가지고 카운팅 되므로, 실질적으로 도메인크로싱이 완료되어야 하는 시점이 점점 빨라지기 때문에 발생된다. 따라서, 도메인크로싱 마진의 감소는 반도체 메모리 설계의 어려움이 된다.This occurs because the cascade latency itself does not change as the operating frequency of the semiconductor memory device increases. However, since the cascade latency is counted with a clock, the time at which domain crossing should be completed is substantially faster. Therefore, reducing the domain crossing margin is a difficulty in semiconductor memory design.

본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로, 도메인크로싱 마진을 증가시킬 수 있는 반도체 메모리 소자를 제공하기 위한 것이다. The present invention has been proposed to solve the above problems of the prior art, and to provide a semiconductor memory device capable of increasing the domain crossing margin.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 내부읽기카스신호를 입력으로 하여, 내부읽기카스신호의 활성화시점으로 부터 애디티브레이턴시의 지연을 카운팅하여 애디티브레이턴시의 종료를 알리는 애디티브레이턴시 종료신호를 생성하기 위한 애디티브카운팅부; 및 상기 내부읽기카스신호, 지연고정루프의 출력클럭, 및 상기 애디티브레이턴시 종료신호를 입력으로 하여 지연고정루프의 출력클럭에 동기시켜 다양한 카스레이턴시를 갖는 다수개의 내부출력인에이블신호를 생성하기 위한 내부출력인에이블신호생성부를 구비하는 반도체 메모리 장치를 제공한다.According to an aspect of the present invention for achieving the above technical problem, by inputting the internal read cask signal, counting the delay of the additive latency from the time of activation of the internal read cask signal to notify the end of the additive latency An additive counting unit for generating a TV latency end signal; And generating a plurality of internal output enable signals having various cascadances by synchronizing with the output clocks of the delayed fixed loops by inputting the internal read casing signals, the outputs of the delayed fixed loops, and the additive latency end signals. A semiconductor memory device having an internal output enable signal generation unit is provided.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 3은 본발명의 일 실시예에 따른 출력인에이블신호 생성패스의 블록 구성도이다.3 is a block diagram illustrating an output enable signal generation path according to an embodiment of the present invention.

도 3을 참조하면, 본 발명의 일 실시예에 따른 출력인에이블신호 생성패스의 블록은 외부커맨드(/CS, /RAS, /CAS, /WE)를 입력받기 위한 입력버퍼(10)와, 입력버퍼(10)의 출력신호를 입력으로 하여 읽기카스신호(casp_rd)를 생성하기 위한 커맨드디코더(11)와, 읽기카스신호(casp_rd)를 입력으로 하여 애디티브레이턴시 만큼의 지연이 지났음을 알리는 애디티브레이턴시 종료신호(AL_end_flag)를 생성하기 위한 AL종료신호 생성부(31)와, 읽기카스신호(casp_rd)를 입력 받아 애디티브레이턴시 종료신호(AL_end_flag)의 활성화 이전에 도메인 크로싱을 완료하고, 상기 애디티브레이턴시 종료신호(AL_end_flag)의 활성화 시점 이후에 다양한 카스레이턴시에 대응하는 데이터 출력인에이블신호(oe15, oe20, oe25 oe30, …)를 생성하기 위한 데이터출력인에이블신호생성부(30)를 구비한다.Referring to FIG. 3, a block of an output enable signal generation path according to an embodiment of the present invention includes an input buffer 10 for receiving an external command (/ CS, / RAS, / CAS, / WE), and an input. A command decoder 11 for generating a read casing signal casp_rd by using the output signal of the buffer 10 and an additive indicating that a delay equal to the additive latency has passed through the read cascade signal casp_rd as an input. After receiving the AL end signal generator 31 for generating the latency end signal AL_end_flag and the read casing signal casp_rd, the domain crossing is completed before activation of the additive latency end signal AL_end_flag. And a data output enable signal generation unit 30 for generating data output enable signals oe15, oe20, oe25 oe30, ... corresponding to various cascade latencies after the activation time of the latency end signal AL_end_flag.

도 4는 데이터 출력인에이블신호생성부(30)의 세부 회로도이다.4 is a detailed circuit diagram of the data output enable signal generation unit 30.

도 4를 참조하면, 데이터출력인에이블신호생성부(30)는 읽기카스신호(casp_rd)을 입력으로 하여 내부클럭(iclk)에 동기된 데이터 출력인에이블신호(oe00)를 생성하기 위한 래치(20)와, 데이터 출력인에이블신호(oe00)를 지연고정루프의 라이징에지클럭(rclk_dll)에 동기시켜 신호를 출력하기 위한 레지스터(21)와, 레지스터(21)의 출력신호를 애디티브레이턴시 종료신호(AL_end_flag)의 활성화에 응답하여 데이터출력인에이블신호(oe10)를 출력시키기 위한 출력제어부(40)와, 데이터출력인에이블신호(oe10)를 지연고정루프의 클럭(fclk_dll 및 rclk_dll)에 동기시켜 다양한 카스레이턴시에 대응하는 데이터출력인에이블신호(oe15, oe20, oe25 oe30, …)를 출력하기 위한 레지스터블록(22)으로 구성된다.Referring to FIG. 4, the data output enable signal generation unit 30 receives a read cascade signal casp_rd as an input and generates a latch 20 for generating a data output enable signal oe00 synchronized with an internal clock iclk. ) And a register 21 for outputting a signal by synchronizing the data output enable signal oe00 with the rising edge clock rclk_dll of the delay locked loop, and an output signal of the register 21 for the additive latency end signal ( Output control unit 40 for outputting the data output enable signal oe10 in response to activation of AL_end_flag, and the data output enable signal oe10 in synchronization with the clocks fclk_dll and rclk_dll of the delayed fixed loop. And a register block 22 for outputting data output enable signals oe15, oe20, oe25 oe30, ... corresponding to the latency.

도 3 및 도 4에서는, 종래기술에서 사용된 블럭과 동일한 입력과 역할을 갖는 블록에 대해서는 동일 도면부호를 사용했으며, 이에 대해서는 구체적 설명을 생략한다.3 and 4, the same reference numerals are used for blocks having the same input and role as the blocks used in the prior art, and detailed description thereof will be omitted.

다음으로 도 3 및 도 4를 참조하여, 본 발명의 일 실시예에 따른 출력인에이블신호 생성패스의 블록의 전체적 동작을 살펴보도록 한다.Next, the overall operation of the block of the output enable signal generation path according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4.

먼저, 외부입력신호(/CS, /RAS, /CAS, /WE)가 입력버퍼(10)를 통해 버퍼링되어 커맨드디코더(11)를 통해 읽기카스신호(casp_rd)로 활성화된다. 이어 읽기카스신호(casp_rd)는 래치(20)를 통해 내부클럭(iclk)에 동기된 펄스형태의 데이터 출력인에이블신호(oe00)로 출력되고, 이는 레지스터(21)를 통해 지연고정루프의 라이징에지클럭(rclk_dll)에 동기됨으로써 도메인 크로싱이 완료된다. 그동안, AL종료신호 생성부(31)는 읽기카스신호(casp_rd)를 입력으로 하여 내부클럭(iclk)을 기준으로 카운팅하여 애디티브레이턴시 지연이 지났음을 알리는 애디티브레이턴시 종료신호(AL_end_flag)를 활성화시킨다. 이에 응답하여 출력제어부(40)는 데이터출력인에이블신호(oe10)를 출력시키고 레지스터블록(22)은 지연고정루프의 클럭(rclk_dll 및 fclk_dll)에 동기된 다양한 카스레이턴시에 대응하는 데이터 출력인에이블신호(oe15, oe20, oe25 oe30, …)를 생성한다.First, the external input signals / CS, / RAS, / CAS and / WE are buffered through the input buffer 10 and activated as the read cascade signal casp_rd through the command decoder 11. Then, the read casing signal casp_rd is output as an enable signal oe00 of a pulse type data output synchronized with the internal clock iclk through the latch 20, which is applied to the rising edge of the delay locked loop through the register 21. The domain crossing is completed by synchronizing with the clock rclk_dll. In the meantime, the AL end signal generator 31 inputs the read casing signal casp_rd and counts the internal clock iclk to activate the additive latency end signal AL_end_flag indicating that the additive latency delay has passed. . In response, the output controller 40 outputs a data output enable signal oe10, and the register block 22 corresponds to a data output enable signal corresponding to various cascade latencies synchronized with the clocks rclk_dll and fclk_dll of the delay locked loop. Create (oe15, oe20, oe25 oe30,…).

이를 종래기술에 따른 동작과 비교하여 보면, 크게 다른점은 종래에는 애디티브레이턴시 이후 활성화되었던 읽기카스신호(casp_rd)를 입력으로 하여 데이터 출력인에이블신호(oe)를 생성했던 반면, 본 발명에서는 내부동작이 없었던 애디티브레이턴시 동안 미리 도메인크로싱을 완료시키고, 이후 애디티브레이턴시 만큼의 지연시간이 경과됐음을 알리는 애디티브레이턴시 종료신호(AL_end_flag)가 활성화 되면, 이에 동기시켜 도메인크로싱이 완료된 신호를 데이터 출력인에이블신호생성부(22)에 인가시킴으로써, 여러 카스레이턴시를 갖는 출력인에이블신호(oe15, oe20, oe25 oe30, …)를 생성하는 점이다.Compared with the operation according to the prior art, the major difference is that the data output enable signal oe is generated by inputting the read cascade signal casp_rd, which has been activated after the additive latency, whereas in the present invention, After the domain crossing is completed in advance during the idle latency, when the additive latency end signal AL_end_flag is activated, indicating that the delay time has elapsed as much as the delay time, the domain crossing is completed. By applying to the enable signal generation unit 22, the output enable signals oe15, oe20, oe25 oe30, ... having various cascade latencies are generated.

결과적으로, 전술한 본 발명에 따르면 종래에 내부적 동작이 없었던 애디티브레이턴시 동안 내부출력인에이블신호의 도메인크로싱을 완료함으로써, 도메인크로싱 마진을 크게 할 수 있다. As a result, according to the present invention described above, the domain crossing margin can be increased by completing the domain crossing of the internal output enable signal during the additive latency in which there is no internal operation.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 애디티브레이턴시 동안 도메인크로싱을 수행함으로써, 도메인크로싱 마진을 개선할 수 있으며, 도메인크로싱 마진의 증가로 반도체 메모리의 설계를 용이하도록 한다.The present invention described above can improve domain crossing margin by performing domain crossing during additive latency, and facilitate the design of semiconductor memory by increasing domain crossing margin.

도 1은 종래기술에 따른 출력인에이블신호 생성패스의 블록 구성도.1 is a block diagram of an output enable signal generation path according to the prior art;

도 2는 도 1의 데이터출력인에이블신호 생성부의 세부 회로도.FIG. 2 is a detailed circuit diagram of a data output enable signal generator of FIG. 1. FIG.

도 3은 본발명의 일 실시예에 따른 출력인에이블신호 생성패스의 블록 구성도.3 is a block diagram illustrating an output enable signal generation path according to an embodiment of the present invention.

도 4는 도 3의 데이터 출력인에이블신호생성부의 내부 블록도.4 is an internal block diagram of a data output enable signal generation unit of FIG. 3;

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

20 : 래치20: latch

21 : 레지스터21: register

22 : 레지스터 블록22: register block

40 : 출력 제어부 40: output control unit

Claims (4)

커맨드를 디코딩하여 읽기카스신호를 생성하기 위한 커맨드 디코더;A command decoder for decoding a command to generate a read cascade signal; 상기 읽기카스신호를 입력 받아 애디티브레이턴시 종료신호를 생성하기 위한 애디티브레이턴시 종료신호 생성부; 및An additive latency end signal generation unit configured to receive the read cascade signal and generate an additive latency end signal; And 상기 읽기카스신호를 입력 받아 상기 애디티브레이턴시 종료신호의 활성화 시점 이전에 도메인크로싱을 완료하고, 상기 애디티브레이턴시 종료신호의 활성화 시점 이후에 다양한 카스레이턴시에 대응하는 다수의 데이터출력 인에이블신호를 생성하기 위한 데이터출력 인에이블신호 생성부After receiving the read cascade signal, the domain crossing is completed before the activation time of the additive latency end signal, and a plurality of data output enable signals corresponding to various cascade times are generated after the activation time of the additive latency end signal. Data output enable signal generator for 를 구비하는 반도체 메모리 소자.A semiconductor memory device having a. 제1항에 있어서,The method of claim 1, 상기 애디티브레이턴시 종료신호 생성부는,The additive latency end signal generator, 상기 읽기카스신호를 입력으로 하여 내부클럭신호를 기준으로 애디티브레이턴시 만큼 카운팅을 수행한 후 상기 애디티브레이턴시 종료신호를 출력하는 카운터를 구비하는 것을 특징으로 하는 반도체 메모리 소자.And a counter for outputting the additive latency end signal after counting by an additive latency based on an internal clock signal using the read cas signal as an input. 커맨드를 디코딩하여 읽기카스신호를 생성하기 위한 커맨드 디코더;A command decoder for decoding a command to generate a read cascade signal; 상기 읽기카스신호를 입력 받아 애디티브레이턴시 종료신호를 생성하기 위한 애디티브레이턴시 종료신호 생성부;An additive latency end signal generation unit configured to receive the read cascade signal and generate an additive latency end signal; 상기 읽기카스신호를 입력 받아 내부 클럭신호에 동기키셔 출력하기 위한 래치부;A latch unit for receiving the read cas signal and synchronizing the internal clock signal with an output; 상기 래치부의 출력신호를 입력 받아 지연고정루프클럭신호에 동기시켜 출력하기 위한 레지스터;A register for receiving the output signal of the latch unit and outputting the same in synchronization with a delay locked loop clock signal; 상기 애디티브레이턴시 종료신호에 응답하여 상기 레지스터의 출력신호를 출력하기 위한 출력 제어부; 및An output controller for outputting an output signal of the register in response to the additive latency end signal; And 상기 출력 제어부의 출력신호를 입력받아 다양한 카스레이턴시에 대응하는 다수의 데이터출력 인에이블신호를 생성하기 위한 레지스터 블록A register block for generating a plurality of data output enable signals corresponding to various cascading times by receiving the output signals of the output control unit. 를 구비하는 반도체 메모리 소자.A semiconductor memory device having a. 제3항에 있어서,The method of claim 3, 상기 애디티브레이턴시 종료신호 생성부는,The additive latency end signal generator, 상기 읽기카스신호를 입력으로 하여, 상기 내부 클럭신호를 기준으로 애디티브레이턴시 만큼 카운팅을 수행한 후 상기 애디티브레이턴시 종료신호를 출력하는 카운터를 구비하는 것을 특징으로 하는 반도체 메모리 소자.And a counter for outputting the additive latency end signal after counting by the additive latency based on the internal clock signal based on the read cas signal.
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