KR19990056812A - Debugging message display - Google Patents

Abstract

The present invention relates to a technology for displaying a debugging message during the development of a PC (PC), in order to be able to freely display the current system state in the LCD window with letters or numbers during the development of the PC, the microprocessor (23B) An LCD unit 23A for displaying a debugging message transmitted from the; When the latch interrupt signal (LATCH-INT) is input from the decoder 21, the latched value is read from the latch unit 22, the corresponding code is found in the flash ROM 23C, and the contents thereof are read. A microprocessor 23B which outputs to the side), reads the table data from the outside, and writes the data to the flash ROM 23C; A flash logic section (23D) for supplying power to the flash ROM (23C) for writing or reading table data; It is configured to include an interface unit 23E and a serial port 23F for serial communication between the microprocessor 23B and the PC.

Description

Debugging message display

The present invention relates to a technique for displaying a debugging message when developing a program of a PC (PC), and in particular, a debugging message display that enables the display of the system status by letters or numbers on the display device by newly implementing a debugging message display device. Relates to a device.

1 is a block diagram of a display of a debugging message according to the prior art, as shown in FIG. 1, when decoding an address signal ADDR input through a system ISA address bus and a write signal lOW ^* is input in an active state. A decoder 11 for outputting a latch signal LAT to the latch unit 12; A latch unit 12 for latching data loaded on an ISA data bus when a latch signal LAT is input from the decoder 11; It is composed of a display unit 13 having a plurality of LEDs (LED1-LED8) to display the data latched in the latch unit 12 in octal or hexadecimal, the operation thereof is as follows.

When developing the program of PC, the 80H address is used as the debugging port. At boot time, the program outputs the current system state to the 80H address. At this time, the write signal (lOW ^* ) is activated as "low".

The decoder 11 decodes the address signal ADDR input through the system ISA address bus and outputs the latch signal LAT to the latch unit 12 when the write signal LOW ^* is input in an active state. .

Accordingly, the latch unit 12 latches data Data on the ISA data bus according to the latch signal LAT, whereby the LEDs LED1-LED8 of the display unit 13 latch the data. Lights up correspondingly to indicate the system status in octal or hexadecimal form.

Thereafter, the display state is maintained until the output for the next 80H occurs.

However, in the conventional debugging message display technology, the current system state is displayed in octal or hexadecimal by the LED operation of the display unit, which makes it difficult for the developer to recognize the contents.

Accordingly, the technical problem to be achieved by the present invention is to provide a debugging message display device for freely displaying the current system state in the LCD window in the form of letters or numbers in the development of the PC program.

1 is a block diagram of a debugging message display chapter according to the prior art.

Figure 2 is an exemplary block diagram of a debugging message display device according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

21 decoder unit 22 latch unit

23: display unit 23A: LCD

23B: Microprocessor 23C: Flash ROM

23D: flash logic section 23E: interface section

23F: Serial port SW1, SW2: Switch

FIG. 2 is a block diagram illustrating an example of a debugging message display device for achieving an object of the present invention. As shown in FIG. 2, an address signal input through a system ISA address bus S-ADDR is decoded and a write signal ( a decoder 21 for outputting a latch signal LAT to the latch unit 22 when LOW ^* ) is input in an active state; A latch unit (22) for latching data loaded on a system ISA data bus (S-DATA) when a latch interrupt signal (LATCH-INT) is input from the decoder (21); When the decoder 21 decodes the specific address 80H and receives the latch interrupt signal LATCH-INT therefrom, the latch 21 reads the latched value and then the flash ROM 23C reads the latched value. A microprocessor 23B for finding the code and displaying the contents in the LCD unit 23A, reading table data from the outside, and writing the data to the flash ROM 23C; A flash logic unit (23D) for supplying power to write or read table data to the flash ROM (23C); An interface unit (RS232 DRIVER) 23E and a serial port 23F for serial communication between the microprocessor 23B and the PC; The switch SW1 for selecting the previous message view and the switch SW2 for selecting the current message view will be described in detail with reference to the operation of the present invention.

First, a process of displaying a debugging message on the LCD unit 23A will be described.

When developing a program of PC, 80H address is used as a debugging port. Upon booting, the program outputs the current system state to 80H address. At this time, the decoder 21 decodes 80H address and latches an interrupt signal (LATCH-INT). Is generated, and the latch interrupt signal LATCH-INT is transmitted to the microprocessor 23B and the latch unit 22.

Accordingly, the latch unit 22 latches data loaded on the system ISA data bus S-DATA when the latch interrupt signal LATCH-INT is input from the decoder 21.

In addition, the microprocessor 23B outputs a latch-out enable signal L-OE ^* to the latch unit 22 when a latch interrupt signal LATCH-INT is input from the decoder unit 21. After reading the latched value, the code corresponding to the value is found in the flash ROM 23C, the contents are read out, and displayed on the LCD unit 23A.

At this time, when the user presses the switch SW1, the microprocessor 23B recognizes this and displays the previous message on the LCD unit 23A. When the user presses the switch SW2, the microprocessor 23B recognizes this and then recognizes it. Display the current message.

Meanwhile, the process of writing the table data in the flash ROM 23C by interfacing the PC with the microprocessor 23B will be described below.

The microprocessor 23B interfaces with the PC through the interface unit 23E and the serial port 23F, reads the table data having a predetermined format, and writes the data to the flash ROM 23C. In this case, the flash logic unit 23D is used. The enable signal EN is " high "

At this time, the latch interrupt signal LATCH-INT output from the decoder 21 is ignored, and when the series of data writing process is completed for the flash ROM 23C, the enable signal EN is set to " Low ".

As described in detail above, the present invention has an effect that it is possible to deliver a debugging message to the program developer more reliably by implementing the display unit to freely display the current system state in the LCD window in the form of letters or numbers when developing the program of the PC. .

Claims (2)

An LCD unit 23A for displaying a debugging message transmitted from the microprocessor 23B; When the latch interrupt signal (LATCH-INT) is input from the decoder 21, the latched value is read from the latch unit 22, the corresponding code is found in the flash ROM 23C, and the contents thereof are read. A microprocessor 23B which outputs to the side), reads the table data from the outside, and writes the data to the flash ROM 23C; A flash logic section (23D) for supplying power to the flash ROM (23C) for writing or reading table data; And a serial port (23F) and an interface unit (23E) for serial communication between the microprocessor (23B) and the PC. The method of claim 1, further comprising a switch SW1 for selecting a view of a previous page and a switch SW2 for selecting a view of a current page among debugging messages displayed on the LCD unit 23A. Debugging message display.