KR200334309Y1 - Bus Signal Generating Device Using Parallel Port - Google Patents

Abstract

The present invention relates to an apparatus for controlling an I / O device by generating an address bus, a data bus, and a control bus based on parallel ports. The main configuration of the present invention is a parallel port for outputting a predetermined control command by the computer as a signal; A control signal generator for generating a bus control signal from the parallel port; An interface unit for providing an external output data bus and an address bus based on a bus control signal output from the control signal generator; And an expansion slot unit through which the address bus provided by the interface unit and the external I / O device and a computer input and output data. According to the present invention, since the interface with the external input and output device based on the parallel port is not affected by the use address of the computer, if there is a simple interface with the computer there is an advantage that the input and output control with the external device. In addition, users who used the Turbo-C ™ program used in MS-DOS ™ can use it under Windows ™ -98.

Description

Bus Signal Generating Device Using Parallel Port {Bus Signal Generating Device Using Parallel Port}

The present invention relates to an I / O device control device of a computer, and more particularly, to an apparatus for controlling an I / O device by generating an address bus, a data bus, and a control bus based on a parallel port.

In general, buses for controlling a input / output (I / O) device by a microprocessor or a central processing unit (CPU) include an address bus, a data bus, and a control bus. In the conventional computer, data input / output with the input / output device was possible using the ISA bus, but recently, external I / O devices are controlled based on the PCI bus. However, the PCI bus has a problem in that it is not easy to use due to the difficulty in assigning IRQs and use addresses with existing devices.

Parallel ports, on the other hand, have been applied to computers for quite some time as printer ports and are still very versatile as highly compatible and easy to control interface ports. However, no device has yet been disclosed that uses such parallel ports to provide a bus for interfacing with a general external I / O device.

On the other hand, the parallel port includes an SPP (Standard Parallel Port) port, a Bi-Directional Parallel Port (EB), an Enhanced Parallel Port (EPP) port, and an Enhanced Capability Port (ECP) port.

Bi-Directional Parallel Port is a bi-directional transmission standard that improves the function of the SPP port method. You can also check. The transfer rate is three times better than the SPP port, supporting up to 6MB per minute.

Next, the Enhanced Parallel Port (EPP) port developed by Intel ™ and Xircom ™ is an improved bi-directional transfer of the SPP parallel port, which constantly checks and configures the status of connected devices. do.

Next, the Enhanced Capability Port (ECP) port is a specification made by Microsoft ™ and Hewlett-Packard ™, the most advanced and fastest of the parallel ports. The ECP parallel port is faster than EPP because it uses DMA channels and accesses data directly in memory without going through the CPU. It is also a bi-directional transmission standard and can transfer speeds of about 22MB per minute, and most parallel devices in the market support ECP mode.

As such, most of the personal computers currently on the market have powerful functions, highly compatible, and easy-to-control parallel ports, and thus there is a need to develop a bus generation and control device using the same.

SUMMARY The present invention provides a method and apparatus for controlling an I / O device by generating an address bus, a data bus, and a control bus based on parallel ports.

1 is a circuit diagram of a bus signal generator using a parallel port according to an embodiment of the present invention.

FIG. 2 is a block diagram for explaining operation of main parts of the apparatus shown in FIG. 1; FIG.

3 is a flow chart briefly summarizing the overall operation of the apparatus of FIG.

The configuration of the present invention for achieving the object of the present invention is a bus signal generating device using a parallel port,

A parallel port for outputting a control command distinguished by predetermined logic according to a predetermined control by a computer as a printer control signal conforming to the Centronics standard;

Input and logic the printer control signal output from the parallel port to generate a bus control signal including an I / O read signal for reading data, an I / O write signal for writing data, and an address enable signal for an address latch. A control signal generator;

Eight inverter buffers are selectively enabled or disabled based on a bus control signal output from the control signal generator and connected to an 8-bit data port of a parallel port to provide a data bus for computer side input. Eight D flip-flops are selectively enabled or disabled based on the bus control signal output from the control signal generator, and are connected to the 8-bit data port of the parallel port so that the signal from the parallel port is a data signal or An interface unit for providing an external output data bus and an address bus in accordance with the address signal; And

And an expansion slot unit into which an external I / O device is inserted and outputs data to and from the external I / O device and a computer through a control signal output from the control signal generator and an address bus and a data bus provided by the interface unit. It is characterized by.

In addition, the bus signal generating apparatus using the parallel port further includes a reset unit for resetting only the I / O interface apart from the computer reset by supplying a reset signal in the form of a pulse to the control signal generator when pressed with a switch. It is desirable to.

In addition, the bus signal generator using the parallel port,

It is preferable to further include a voltage stabilizer having a zener diode to provide a constant voltage even when the input voltage fluctuates above a predetermined voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a bus signal generator using a parallel port according to a preferred embodiment of the present invention. Referring to FIG. 1, a bus signal generator using a parallel port according to a preferred embodiment of the present invention includes a parallel port 10, a control signal generator 12, an interface unit 14, and an expansion slot unit 160. ), A reset unit 162, and a voltage stabilizer 164. The interface unit 14 includes eight inverter buffers 142 and eight D flip-flops 144.

The operation of the bus signal generator using the parallel port according to the preferred embodiment of the present invention as described above will be described. The parallel port 10 outputs a control command distinguished by predetermined logic according to a predetermined control by a computer as a printer control signal conforming to the Centronics standard.

When describing the parallel port, 8 bits of data (D0 to D7) are used as printer output information from the computer through the parallel ports (pins 2 to 9), and another multiple bit output is output from the computer to the parallel ports (pins 1, 14, 31, 36) to control the printer. In the present invention, the printer control signal portion for controlling the printer is logicized as a bus control signal.

The control signal generator 12 inputs and logicalizes the printer control signal output from the parallel port 10 to output the I / O read signal IOR for reading data and the I / O write signal for writing data. And a bus control signal including an address enable signal (AEN) for the address latch.

In this embodiment, the control signal generation unit 12 uses a model name PALCD22V10 chip, which is a PLD (Programmable Logic Device) element, and inputs the data bus and other control signals of the parallel port to the control signal generation unit 12 for necessary control. Generate signals IOW, IOR, AEN. The control signal generation unit 12 composed of the PLD elements receives each necessary signal line and logics the necessary control signals internally and outputs them to the outside again, integrating various required elements into one PLD element. .

Next, the interface unit 14 includes eight inverter buffers 142: 74LS541 which are selectively enabled or disabled based on the bus control signal output from the control signal generator 12, and the parallel port 10 is provided. Is connected to an 8-bit data port to provide a data bus for computer-side input.

In addition, the interface unit 14 includes eight D flip-flops 144 (74LS573), each of which is selectively enabled or disabled based on the bus control signal output from the control signal generator 12, and has a parallel port. It is connected to an 8-bit data port so that the external output data buses D0 to D7 and address buses A0 to A7 are provided so that signals from the parallel port are data signals or address signals.

Next, the expansion slot unit 160 has an external I / O device inserted therein and outputs the control signal output from the control signal generator 12 and the address bus and data bus provided by the interface unit 12. I / O devices and computers input and output data.

On the other hand, the reset unit 162 includes a switch, a resistor, and a condenser. When the switch is pressed, the reset unit 162 supplies a reset signal in the form of a pulse to the control signal generation unit by the action of the resistor and the condenser, so as to separate the I / O from the computer reset. Only reset the interface.

In addition, the voltage stabilizer 164 includes a power transistor and a zener diode to provide a constant voltage even when the input voltage fluctuates above a predetermined voltage, thereby preventing damage even when an abnormal voltage is supplied from the computer side.

FIG. 2 is a block diagram illustrating the operation of the main parts of the apparatus shown in FIG. 1. Referring to FIG. 2, the parallel port 20 outputs a control command distinguished by predetermined logic according to a predetermined control by a computer as a printer control signal conforming to the Centronics standard. Next, the control signal generator 22 inputs and logics the printer control signal output from the parallel port 20 to write an I / O read signal IOR for reading data and an I / O write for writing data. A bus control signal including the signal IOW and the address enable signal AEN for the address latch is generated, and the interface unit 24 is controlled.

As a result, the interface unit 24 outputs the address signals A0 to An and the data signals D0 to D7 when n is a predetermined positive integer under the control of the control signal generation unit 22, respectively. Provide a bus.

3 is a flow chart briefly summarizing the overall operation of the apparatus of FIG. Referring to Fig. 3, first, a bus cycle is started (step S302), an address output (step S304) is made, and next, whether the bus check mode is identified (step S306), and in the bus check mode, a bus connection ( The process for step S306 is performed, and when it is not in the bus test mode, the data output and control signals IOR, IOW, and AEN output processes are performed. The step of identifying whether the bus is in the test mode (step S306) can be performed by software operating in a computer, and identifying whether the data output and control signals (IOR, IOW, AEN) are not being output. Can be understood.

Since the bus signal generator using the parallel port is interfaced with an external input / output device based on the parallel port, the bus signal generation device is not affected by the use address of the computer. The process of inserting into the corresponding bus slot also has the advantage of allowing the input / output control with the external device by creating a bus using the existing parallel port.

In addition, the parallel port can be operated directly in the basic environment of a computer such as DOS mode, so users of the Turbo-C ™ program used in MS-DOS ™ can use Windows ™ -98. 98), it can be used as is, and Windows ™ -ME / 2000 / XP users can use the drive file provided separately.

As described above, according to the present invention, the interface is connected to an external input / output device based on a parallel port, so that it is not affected by the use address of the computer. It is possible to control input / output with an external device by creating a bus using the existing parallel port without having to insert it into the port. In addition, users who used the Turbo-C ™ program used in MS-DOS ™ can still use it under Windows ™ -98 and Windows ™ -ME / 2000 / XP. ™ -ME / 2000 / XP) users can use the drive file provided separately.

Claims (3)

A bus signal generator using a parallel port, comprising: a parallel port configured to output a printer control signal conforming to a Centronics standard according to a predetermined control by a computer; Input and logic the printer control signal output from the parallel port to generate a bus control signal including an I / O read signal for reading data, an I / O write signal for writing data, and an address enable signal for an address latch. A control signal generator; Eight inverter buffers are selectively enabled or disabled based on a bus control signal output from the control signal generator, and are connected to an 8-bit data port of a parallel port to provide a data bus for computer side input. And eight D flip-flops, each of which is selectively enabled or disabled based on a bus control signal output from the control signal generator, and connected to an 8-bit data port of the parallel port so that the signal from the parallel port is a data signal. Or an interface unit for providing an external output data bus and an address bus in accordance with the address signal; And an expansion slot unit into which an external I / O device is inserted and outputs data to and from the external I / O device and a computer through a control signal output from the control signal generator and an address bus and a data bus provided by the interface unit. Bus signal generation apparatus using a parallel port, characterized in that. The method of claim 1, further comprising a reset unit for resetting only the I / O interface apart from the computer reset by supplying a reset signal in the form of a pulse to the control signal generator when pressed with a switch. Bus signal generator using port. The apparatus of claim 1, further comprising a voltage stabilizer including a power transistor and a zener diode to provide a constant voltage even when the input voltage fluctuates above a predetermined voltage.