KR19990055492A - Data communication method between a private exchange of a communication system and a module provided therein - Google Patents

Abstract

The present invention relates to a data exchange method between a private switch of a communication system and a module included in the communication system capable of greatly improving the data transmission speed even by simplifying the overall configuration by reducing the number of bus lines and address lines. In the present invention, at least one first module for transmitting and receiving data, a first interrupt processor for generating a first interrupt signal, a clock signal, and a synchronization signal according to a control signal of the first module, and transmitting and receiving data A plurality of second interrupt processors for generating an interrupt trigger signal according to a control signal of the second module, and receiving an interrupt signal transmitted from the first interrupt processor; 2 module writes data to be transmitted and receives from the first module. And a plurality of storage portions for storing the foundation, and includes the first module and between the plurality of storage sub-unit to the bus so that the transmission and reception of data performed.

Description

Data communication method between a private exchange of a communication system and a module provided therein

The present invention relates to a data communication method between a private exchange of a communication system and a module provided therein, and more particularly, a bus line which minimizes the number of data transmission lines between modules having a common back plane in the configuration of the entire system. And a data exchange method between a private switch of a communication system and a module included in the communication system capable of improving a data transmission speed even by using a memory line.

In general, a private exchange connected to a terminal of a building or a set area is connected to a public switched telephone network (PSTN) through an intermediate connection device such as an E1 to T1 trunk to control internal communication between subscribers and also to a private exchange. Control communication between subscribers and external subscribers. However, the number of subscribers that must be handled by one private exchange is increasing. In light of this trend, the capacity of private exchanges must continue to increase, while the speed of information processing must be faster.

1 is a block diagram showing the internal configuration of a private switch in a conventional CDMA communication system. Referring to FIG. 1, in a conventional CDMA communication system, a private exchange includes a master module 10, 16 slave modules 20a-20n, the master module 10, and 16 slabs. It consists of an eight-line parallel bus 30 and a control bus line 40 that provide a communication path between the Eve modules 20a-20n. In addition, each master module 10 and 16 slave modules 20a-20n include buffers 13 and 23 for storing data, and memory 12 and 22 and a controller 11 for controlling generation of control signals. And 21 are provided, respectively.

In a private switch in the conventional CDMA communication system having such a configuration, a signal transmission between 16 slave modules and a master module uses a method of transmitting and receiving data for 2 ms with a period of 8 ms. In other words, 2ms is divided into 16 corresponding to 16 slave modules so that data can be transmitted only during the time allocated to each module. At this time, the time allocated to one module assigned to one module is 125μs, and the 125μs is divided into a time of retransmission and a time of reception, so transmission and reception operations are performed for each 65.5μs. In this case, since 16 bytes of data are generally transmitted and received during this 65.5 μs, it can be seen that the time for transmitting and receiving 1 byte becomes 3.9 μs.

The meaning of transmission at this time means that any slave module 20a sends 16 bytes to the master module 10 for 62.5 μs, and the reception is performed for 62.5 μs for the master module 10 to any slave module 20a. It is sending 16 bytes.

In such a conventional data transmission method, each allocated time is occupied in a set order to transmit and receive data, thereby occupying the data bus for a set time even when there is no data to transmit and receive. Therefore, in general, the data transfer efficiency of the parallel bus 30 having eight bus lines is poor.

In addition, the start point of the data transmission starts from the control signal (for example, SLAC) provided by the master module 10 becomes " 0 ", which is not shown in the drawing, but each slave module 20a-20n. Each peripheral circuit such as a counter must be configured. As a result, the design of the entire busline becomes very complicated, and if a noisy signal is introduced from the outside, the clock for synchronizing each slave module 20a-20n becomes unstable, which leads to a high probability of error in data transmission. There was a growing problem.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned problems of the related art, and it is possible to reduce the number of bus lines and address lines so that the data transmission speed can be greatly improved even if the overall configuration is simplified. It is to provide a data communication method between a private exchange and a module provided therein.

In order to achieve the same object as that described above, the private exchange according to the present invention includes at least one first module for transmitting and receiving data and a first interrupt signal, a clock signal, and a synchronization signal according to a control signal between the first modules. A first interrupt processor for generating a signal, a plurality of second modules for transmitting and receiving data, an interrupt trigger signal according to a control signal of the second module, and receiving an interrupt signal transmitted from the first interrupt processor; A plurality of second interrupt processors, a plurality of storage units for writing data to be transmitted by each second module, and storing data to be received from the first module, and a plurality of first modules and a plurality of storage units And a bus unit for transmitting and receiving data between the units.

In order to achieve the above object, a method of data communication between modules in a private exchange of a communication system according to the present invention is to transmit data from any one of a plurality of slave access modules to a master access module. A method comprising: transmitting a first interrupt signal to the master access module, receiving the first interrupt signal from the slave access module and recognizing that the slave access module has stored data; Reading the data.

In addition, in order to achieve the above another object, a method of data communication between modules in a private exchange of a communication system according to the present invention is a slave access module of any one of a plurality of slave access modules to the data in the master access module. A method of transmitting to a module, the method comprising: transmitting data to be transmitted to a plurality of slave access modules; detecting and storing the data if the data has its own address value; Generating an interrupt signal, a corresponding slave access module recognizes an interrupt signal, recognizes that there is data transmitted, and reads stored data.

1 is a block diagram showing the internal configuration of a private switch in a conventional CDMA communication system.

2 is a block diagram showing an internal configuration of a private switch in a CDMA communication system according to the present invention;

FIG. 3 is a block diagram illustrating an internal configuration of an interrupt processor connected to the slave access module shown in FIG. 2. FIG.

4 and 5 are block diagrams showing an internal configuration of an interrupt processor connected to the master access module shown in FIG.

<Description of the symbols for the main parts of the drawings>

100,200a-200n: Access Module 110: Interrupt Processor Master

210a, 210n: interrupt processor slave

300,330,340,350: Data bus 310: Lead / light line

320: address line 400a-400n: bidirectional FIFO

500a-500n: address decoder

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration, operation and effects according to an embodiment of the present invention.

2 is a block diagram showing an internal configuration of a private switch in a CDMA communication system according to the present invention.

Referring to FIG. 2, FIG. 2 illustrates an interrupt signal STMINT according to a control signal of a master access module 100 and a master access module 100 for transmitting and receiving data in a CDMA communication system according to the present invention. , MSTINT), interrupt processor 110 for generating interrupt clock signal CLOCK and synchronization signal SYNC, a plurality of slave access modules 200a to 200n for transmitting and receiving data, and a plurality of slave accesses A plurality of interrupt processors 210a-210n for generating an interrupt trigger signal ST2-STn according to the control signals of the modules 200a-200n, and receiving an interrupt signal transmitted from the interrupt processor 110, respectively. A plurality of storages for writing data to be transmitted by the plurality of slave access modules 200a to 200n and storing data to be received from the master access module 100 And a bus unit 300, 310, and 320 for transmitting and receiving data between the master 400a-400n and the master access module 100 and the plurality of storage units 400a-400n.

Here, the storage units 400a-400n use a first in-first out (FIFO) buffer, and the bus units 300, 310, and 320 have one read / write line 310 and an address line. 320, the data bus 300 is selected from among 8 bits, 16 bits, and 32 bits.

In addition, as shown in FIG. 2, the interrupt processor 110 belonging to the master access module and the interrupt processors 210a through 210n belonging to the slave access modules 200a to 200n may connect at least two serial buses STMINT and MSTINT. Send and receive interrupt signals.

Data communication between different modules, that is, the master access module 100 and the optional slave access module 200a in the private exchange of the communication system according to the present invention having the above configuration will be described with reference to FIGS. 2 to 5. Is as follows.

First, when the slave access module 200a transmits data to the master access module 100, the master access module 100 receives an interrupt signal from the slave access module 200a and is connected to the slave access module 200a. Recognizing that there is useful data in the bidirectional FIFO 400a, the contents of the data stored in the bidirectional FIFO 400a are read through the read / write line 310.

In contrast, when the master access module 100 transmits data to the slave access module 200a, the master access module 100 transmits the data to the bidirectional FIFO 400a connected to the slave access module 200a. Save it via 320). At this time, an address decoder 500a is provided between each bidirectional FIFO 400a and the address line 320. The role of the address decoder 500a compares data transmitted through the address line 320 with a specific value. If it matches, it is accepted and output. Subsequently, the master access module 100 generates an interrupt signal through the interrupt processor 110 to allow the interrupt processor 210a to recognize it. Then, the slave access module 200a recognizes that useful data is stored in the bidirectional FIFO 400a, and reads the contents of the data stored in the bidirectional FIFO 400a.

In addition, when data transmission is required between two slave access modules, the master access module 100 transmits the data through a relay. That is, the master access module 100 receives the data from one slave access module to which the data is to be transmitted and transmits the data to another slave access module which is desired to be transmitted.

For the above operation, the interrupt processor 110 connected to the master access module 100 and the interrupt processors 210a-210n connected to the slave access modules 200a-200n include at least two serial buses (STMINT, MSTINT) and an interrupt clock. A clock and a sync are used.

That is, as shown in FIG. 2, the slave access module 200a writes data to be transmitted to the bidirectional FIFO 400a and then interrupts an interrupt control signal (eg, through an interrupt trigger application line ST2). When a signal having one rising edge is generated, a signal is transmitted to the CS_INT 211 terminal of the master access module 100 shown in FIG. 3 to have a high level signal of "1" in the de-flop D1. When the logic level of the logic sum gate OR1 becomes "0", the interrupt signal STMINT of the output terminal 214 becomes "0". The output signal 216 of the OR gate OR2 outputs the output terminals Q0, Q1, Q2, and Q3 of the counter UC1 to the slave numbers SN0, SN1, SN2, and SN3 and four exclusive OR gates XR1-. Compared through XR4), when the same value is obtained, the level is "0". The counter UC1 operates in synchronization with a clock signal and a synchronization signal sync provided from the interrupt processor 110 connected to the master access module 100. At this time, when the level of "0" is given to the clear terminal CD of the counter UC1, the values of the output terminals Q0, Q1, Q2, and Q3 of the counter UC1 are all "0" at the ring edge of the next clock. Will have the value of.

4 and 5 show the internal configuration of the interrupt processor 110 shown in FIG.

The interrupt signal STMINT shown in FIG. 2 is the interrupt signal STMINT shown in FIG. 4, shifted through the shift registers SR1 and SR2, and latched by the clock signal CL1. The interrupt request signal IRQ is generated (i.e., at a logic level of " 0 ") via the instantaneous de-flip flop D3 and the de-flip flop D4 is removed by the interrupt receive signal IACK. That is, the logic level is "1".

The master access module 100 of FIG. 2 sets the interrupt control signal ST1 and the read / write line 310 to " 0 " and " 1 ", respectively, through the data bus 300 shown in FIG. The latched values of the de-flip flops D3 and D4 are read. These values indicate whether an interrupt signal has been generated in the Wth slave access module.

When data is written to the de-flip flops D5 and D6 shown in FIG. 5, a value of "0" is applied to the interrupt signal MTSINT by a circuit operation corresponding to the value, and the interrupt signal MTSINT shown in FIG. The output signal of the OR gate OR2 and the OR gate OR3 are ORed to generate an interrupt request signal IRQ by clocking the de-flip flop D2. That is, the interrupt request signal IRQ becomes "1" by the interrupt reception signal IACK.

According to the present invention as described above, in a private exchange having one master access module and a plurality of slave access modules, conventionally, all slave access modules are configured with peripheral circuits such as counters to design the entire busline. Although very complicated, in the present invention, only one read / write line, an address line, and a data bus are provided with a bidirectional FIFO in each of the plurality of slave access modules, and only two serial buses transmit an interrupt signal to each other. Although the configuration of the circuit becomes simpler, the processing speed of the data is rather faster. In addition, since such a simple configuration can prevent the inflow of the noisy signal from the outside, the probability of an error occurring during data transmission is significantly reduced.

Claims (11)

At least one first module for transmitting and receiving data; A first interrupt processor for generating a first interrupt signal, a clock signal, and a synchronization signal according to the control signal of the first module; A plurality of second modules for transmitting and receiving data; A plurality of second interrupt processors generating an interrupt trigger signal according to a control signal of the second module and receiving an interrupt signal transmitted from the first interrupt processor; A plurality of storage units for writing data to be transmitted by each second module and storing data to be received from the first module; And a bus unit configured to transmit and receive data between the first module and the plurality of storage units. 2. The private exchange of claim 1, wherein the plurality of storage units is a first in-first out (FIFO) buffer. 2. The private exchange of claim 1, wherein said bus portion comprises one read / write line and an address line. 2. The private exchange of claim 1, wherein the bus unit comprises a data bus having any one of 8 bits, 16 bits, and 32 bits to transmit data. 2. The private exchange of claim 1, wherein the first and the plurality of second interrupt processors transmit and receive the interrupt signal through at least two serial buses. A method for transmitting data to a master access module in any one of a plurality of slave access modules, the method comprising: Transmitting a first interrupt signal to the master access module; Receiving the first interrupt signal from the slave access module and recognizing that the slave access module has stored data; And reading the stored data. A method of data communication between modules in a private exchange of a communication system. 7. The data according to claim 6, wherein the data written first is read first when the stored data is read, and executed in both directions of the master access module or the slave access module. Communication method. A method for transmitting data from a master access module to any one of a plurality of slave access modules, the method comprising: Transmitting data to be sent to a plurality of slave access modules; Detecting and storing the data if the data has its own address value; Generating an interrupt signal to the slave access module; The slave access module recognizes an interrupt signal and recognizes that there is data transmitted; A method of data communication between modules in a private exchange of a communication system, comprising the steps of: reading stored data. The data between modules in a private exchange of a communication system according to claim 8, characterized in that the data written first is read first when the stored data is read, and executed in both directions of the master access module or the slave access module. Communication method. 1. A method for transferring data between any two slave access modules of a plurality of slave access modules, the method comprising: a master access module; Transmitting data to be transmitted to the master access module; Transmitting the data to a plurality of slave access modules; Detecting and transmitting the transmitted data if the data has its own address value and storing the received data; Generating an interrupt signal to the slave access module; The slave access module recognizes an interrupt signal and recognizes that there is data transmitted; A method of data communication between modules in a private exchange of a communication system, comprising the steps of: reading stored data. 11. The method of claim 10, wherein the data written first is read first when the stored data is read, and is executed in both directions of the master access module or the slave access module. Communication method.