KR19990053511A - Miniature Interleaver for Downstream Transmission in Cable Transmission Systems - Google Patents

Abstract

The present invention relates to a reduced interleaver that supports various interleaving modes (I, J) for downstream transmission of a cable transmission system.

According to the present invention, a block data stream consisting of N symbols is interlaced in two or more interleaving modes having an interleaving interval I (= N / J, I≤M) and an interleaving depth J (an integer of p≤J). M tabs are positioned in the direction, and the i th tab of the M tabs has a storage unit for storing (i-1) registers in series and storing an input symbol as a register of the corresponding tab. Share it. To this end, in the case of distributing symbols by connecting an input commutator to the input side of the storage unit and an output commutator to the output side, the start of each cycle is connected to the first tap and the next tap with the interleaving interval I of each mode as one cycle. The switching action is connected to the tap increased by J according to the interleaving depth J.

In the related art, various interleavers were implemented separately, but inefficient. However, the present invention supports all the various interleavers, but has an effect of simplifying the design and reducing the area and the amount of hardware.

Description

Reduced Interleaver of the cable transmission system in the downstream direction

The present invention relates to a cable transmission system, and more particularly, to a reduced interleaver that supports various interleaving modes for downstream transmission.

Cable modem network provides various services such as telecommuting, video conferencing, and web search to subscribers by connecting to internet and intranet together with Integrated Information Communication Network (ISDN) and Multi-Digital Subscriber Line (xDSL).

1 is a reference diagram of a cable modem network that supports broadband service. A headend 110 including a cable modem termination system (hereinafter referred to as CMTS) is connected to a backbone network 100 including a private network or a public network provided by a communication network operator. The cable modem 130 (hereinafter referred to as CM) is connected. Between the head end 110 and the CM (130) is located a photoelectric converter (120, Optic / Electro Converter) is connected by the optical cable to convert the optical signal and the electrical signal, the photoelectric converter 120 and the CM (130), The CM 130 and the subscriber side 140 are connected by coaxial cable. Bi-directional communication is possible between the service provider and the subscriber side, and the two bidirectional communication paths are combined at the headend 110. The headend 110 includes a CMTS 111 that enables bidirectional communication, an operation support system for the CMTS 111 (not shown), and a combiner 112 that transmits various application services of an information provider by combining data signals. And a transmission buffer 114, a reception buffer 115 and a distributor 113 for receiving and distributing subscriber request data, and a security and access control unit 116. The CMTS 111 includes a network terminal 111-1 in charge of the CMTS and a network interface, a modulator 111-2 for modulating application service data (downstream data) of an information provider, and request data of a subscriber ( Demodulation section 111-3 for demodulating upstream data). The cable modem network shown in FIG. 1 is a broadband system using RF signals, and an RF interface exists between the CM and the cable network, between the CMTS and the cable network downstream, and between the CMTS and the cable network upstream.

The downstream channel transmitted from CMTS to each CM broadcasts broadband service data at a transmission rate of 50 to 860 MHz, and the upstream channel transmitted from CM to CMTS is 5 to 42 MHz. Send in a point-to-point fashion

The downstream protocol of the cable transmission system is as defined in ITU-T Recommendations J.83, Annex B. The downstream signal processing is shown in FIG. The downstream modulation process is performed by framing the MPEG-2 data stream input in the packet unit from the MPEG frame unit 200, and then performing a forward error correction algorithm in the FEC encoder 210 to perform a channel ( To obtain reliable data. The FEC code output from the FEC encoder 210 is QAM modulated by the QAM modulator 220 and then transmitted through the cable channel 230 as an RF signal. The downstream demodulation is performed through the QAM demodulator 240, the FEC decoder 250, and the MPEG frame unit 260 in a reverse process to modulation. The MPEG framing process provides a parity check pattern for packet synchronization between the transmitter and the receiver. The QAM modulation process supports 64QAM mode and 256QAM mode. The FEC encoding process uses a concatenated coding technique, and an outer coder uses a Reed-Solomon code having T error correction capabilities, and an inner coder. By using the TCM codeword to generate the coded modulation code, the error that is not corrected by the internal decoder is usually corrected by the external decoder so that the error rate is almost zero.

3, the FEC encoder 210 (see FIG. 2) is composed of a Reed Solomon encoder 300, an interleaver 310, a randomizer 320, and a trellis encoder 330. The FEC decoder 250 includes a trellis decoder 350, an inverse randomizer 360, a deinterleaver 370, and a Reed Solomon decoder 380.

The Reed Solomon encoder 300 encodes the MPEG transport stream using a (128,122) RS block code. (128, 122) The RS block code consists of 128 symbols per block, of which only 122 symbols are information symbols and 6 symbols are parity for error correction, so up to 3 symbols per RS block are error corrected. The RS block code is used identically in the 64QAM mode and the 256QAM mode.

The interleaver 310 convolutionally interleaves the (128, 122) RS block codes to rearrange the data streams. The interleaver 310 is for efficiently coping with successive error symbols (cluster errors, burst errors) generated during channel transmission. The convolutional interleaver structure supports a programmable structure, that is, various interleaving modes in 64QAM mode and 256QAM mode.

The randomization unit 320 randomizes the interleaved data so that the interleaved data does not have a specific pattern, thereby preventing the RF-modulated signal from interfering with other channels and extracting synchronization from the receiver. Randomized data is output by generating a pseudo noise code promised with the receiver and adding it to the input data.

The trellis encoder 330 performs trellis coded modulation (TCM). TCM is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel and is implemented by combining a coding technique and a modulation technique. The TCM structure is composed of a convolutional encoder having a finite state and a QAM modulator (64 / 256QAM).

A process of convolutional interleaving by receiving an RS block code in symbol units in the interleaver 310 will be described with reference to FIG. 4.

4 is a circuit diagram illustrating a convolutional interleaver and a deinterleaver. The convolutional interleaver 400 includes an input commutator 410, a plurality of shift register stages 1 to I, and an output commutator 420. The convolutional deinterleaver 450 is composed of an input commutator 460, a plurality of shift register stages 1 to I having an opposite structure to the convolutional interleaver, and an output commutator 470.

In the shift register structure of the convolutional interleaver, the top tab 1 is directly connected to an input and an output without a shift register, and the shift register length is " 0 ", and from the next taps 2 to I, the " J " "2J", "3J",... , As long as "(I-1) J". The memory difference between successive register tabs stores more "J" symbols than the registers in the previous tab. The register width is 7 bits, which is the same as that of the RS symbol since the RS block code is processed in symbol units.

The shift register structure of the convolutional deinterleaver 450 has a structure opposite to that of the shift interleaver 400. In other words, the top tab 1 has a shift register length of "(I-1) J", and from the next tabs 2 to I, "(I-2) J",... , "2J", "J", "0" has a length as long as.

The input commutator 410 of the convolutional interleaver 400, the output commutator 420, the input commutator 460 of the deinterleaver 450, and the output commutator 470 all operate in synchronization. Data is interleaved by switching sequentially from the first tap to the last I-1 tap according to the symbol clock, and then repeatedly switching from the first tap. Through this switching operation, the first data of the I cycle input to the first tap of the convolutional interleaver 400 is output without a delay, and the second data of the I cycle input to the second tap is input to the third tap after an IJ delay. The third data is after a 2IJ delay,... , The last data of cycle I input to tap I is output after (I-1) IJ delay.

As a result, in the interleaver 400 on the transmitting side, IJ arbitrary symbol data is inserted between two neighboring symbol data in the input data string and transmitted to the convolutional deinterleaver 450 on the receiving side through the channel 430.

The first data of the I cycle input to the first tap of the convolutional deinterleaver 450 is output after (I-1) IJ delay, and the second data of the I cycle to the second tap is (I-2) IJ delay ,… , The last second data of cycle I entered through tap I-1 is output after J delay, and the last data of cycle I entered into tap I is output without delay.

As a result, after the system is operated, the original data stream that was input to the convolutional interleaver 400 after the (I-1) IJ delay is obtained.

In general, the specification of the convolutional interleaver is represented by the (I, J) parameter, where I represents the number of taps in the shift register, which is called an interleaving interval, and J is an interleaving depth representing a register increment between neighboring taps. This is called interleaving depth.

Meanwhile, in the cable transmission system, the interleaver specification supports the reduced interleaving mode and the extended interleaving mode. Among them, the reduced interleaving mode supports five types: (I, J) = (128,1), (64,2), (32,4), (16,8), (8,16). have. Each of the interleavers shown in FIG. 4 according to the five modes is required. The minimum amount of memory required to design the interleaver as shown in FIG. (symbols).

Therefore, in designing the interleaver according to each mode, (128,1) mode is 8,128 symbols, (64,2) mode is 4,032 symbols, (32,4) mode is 1,984 symbols, and (16,8) mode is 960 symbols and (8,16) modes require registers to store 448 symbols, respectively, as well as separate input / output commutators. This has a problem that the amount of the hardware can not be ignored if implemented in the general logic (LOGIC) or ASIC (custom semiconductor).

Accordingly, the present invention has been made to solve the above problems, the present invention is to switch the memory of the corresponding mode of the shared memory in accordance with the mode control signal for the downstream transmission of the cable transmission system performing multi-mode interleaving The purpose is to provide a miniature interleaver.

In order to achieve the above object, the present invention provides an interleaving interval I (= N / J, an integer of I≤M, M is a maximum value of a multimode interleaving interval), and an interleaving depth J ( In the interleaving of two or more types of interleaving modes (I, J), where p is equal to J and p is the minimum value of the multimode interleaving depth, the input symbols are distributed and output according to the mode control signal for distinguishing the interleaving modes. Input commutator; 0 registers in the 1st tap, p registers in the 2nd tap in series, 2p registers in the 3rd tap in series,… A storage unit for storing the symbols output from the input commutator in the registers of the corresponding tabs while having (M-1) p registers connected in series to the M th taps in a vertical direction; And an output commutator for receiving and outputting symbols of the storage unit according to the mode control signal.

1 is a reference configuration diagram of a cable modem network supporting broadband services;

2 is a block diagram showing a downstream signal processing procedure of a cable transmission system;

3 is a detailed block diagram of a forward error correction unit of FIG. 2;

4 is a detailed circuit diagram of the interleaver / deinterleaver of FIG.

5 is a block diagram of a reduced interleaver for downstream transmission according to the present invention.

Explanation of symbols on the main parts of the drawings

500: input commutator 510: storage unit

520: output commutator R: shift register

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

This embodiment relates to a reduced interleaving mode supported in both 64QAM / 256QAM modes of a cable transmission system. The parameters of the reduced interleaving mode and corresponding mode control signals are shown in Table 1.

Mode control signal (4 bits) I (# of taps) J (increment) Burst Defense 0001 128 One 95㎲ / 66㎲ 0011 64 2 47㎲ / 33㎲ 0101 32 4 24㎲ / 16㎲ 0111 16 8 12㎲ / 8.2㎲ 1001 8 16 5.9㎲ / 4.1㎲

In Table 1 above, the interleaving parameters I and J are appropriately selected for a given channel, and these parameter values are also related to burst defenses. In Table 1, the reduced interleaving mode shows that burst protection increases as I increases when the value of I × J is constant. The control signal (4 bits) of the reduced interleaving mode is transmitted to the receiving side during the FEC frame synchronization interval, and the receiving side performs deinterleaving of the corresponding mode for a given channel.

5 is a block diagram of a reduced interleaver for downstream transmission according to the present invention. The reduced interleaver uses the RS block data stream consisting of 128 RS symbols in (128,1), (64,2), (32,4), (16,8), and (8,16) modes depending on the channel environment. It consists of an input commutator 500, a storage unit 510 and an output communicator 520 to weaving interleaving to any one.

In the five modes, since the maximum interleaving interval is 128 (= M) and the minimum interleaving depth is 1 (= q), the storage unit 510 has 128 tabs arranged in the vertical direction, and each i-th tap has a unit (I-1) registers of length 1 (= q) are arranged in series. That is, there is no register in the first tap, one register is connected in the second tap, two registers are connected in series in the third tap,. In the 127th tap, 126 registers are connected in series, and in the 128th tap, 127 registers are connected in series. The serially connected registers of each tap store one symbol per register, and receive new input symbol data at every symbol clock transition point and move the stored data one symbol. Each tap register can be implemented as a serial input serial output shift register.

The input commutator 500 and the output commutator 520 are synchronized with each other according to a mode control signal to switch to the same tap (tap of the storage unit 510). The mode control signal uses 4 bits that distinguish the five modes shown in Table 1. Tab of storage unit 510 connected to input / output commutator 500,520 according to (128,1), (64,2), (32,4), (16,8), (8,16) mode The number is set.

(128,1), 1,2,3,4,... , 127,128,1,2... Connected to the second tap, 1,3,5,7,... , 125,127,… , 1,3,… Connected to the second tap. (32,4), 1, 5, 9, 13,... , 121,125,1,5... Connected to the second tap, 1,9,17,25,... , 113,121,1,9,... Connected to the second tap. (8,16), 1,17,33,49,... , 97,113,1,17... Connected to the second tap. That is, switching starts from the first tap for one period corresponding to the interleaving interval I and is connected to the tap increased by the interleaving depth J of each mode, and then the next cycle is repeated again from the first tap.

Hereinafter, the operation and effect of the present embodiment will be described with reference to FIG. 5.

① (128,1) mode

In the (128,1) mode, the input / output communicator (500, 520) sets the tab incremented by one from the first tap of the storage unit (510) by one cycle by the mode control signal (0001). Switching connection in sequence. The input / output commutator 500,520 switches to the next tap in synchronization with the symbol clock, and repeats it starting from the first tap after 128 symbol clocks (1 → 2 → 3,…, 128 → 1 → 2…). ).

The first symbol data of the period input to the first tap of the storage unit 510 is output without delay, the second symbol data to the second tap is 128 × 1 delay, and the third symbol data to the third tap is 128 After the delay of × 2,... The last symbol data of the cycle input to the 128 tap is output after the delay of 128 × 127. As a result, interleaving is performed in which (128 × 1) arbitrary symbol data are inserted between two neighboring symbol data in the original input data stream.

② (64, 2) mode

In the (64, 2) mode, the input / output communicator (500, 520) by the mode control signal (0011) to the 64 symbol clock for one cycle to increase the tap from the first tap of the storage unit 510 by 2 Switching connection in sequence. At this time, the input / output commutator 500,520 switches to the next tap in synchronization with the symbol clock, and repeats the operation starting from the first tap after the 64 symbol clock (1 → 3 → 5,…, 127 → 1 → 3…).

The first symbol data of the cycle input to the first tap of the storage unit 510 is output without delay, the second symbol data to the third tap is 64 × 2 delay, and the third symbol data to the fifth tap is 64 After the delay of × 4,... , The last data of the cycle input to tap 127 is output after the 64 × 126 delay. As a result, on the transmitting side, interleaving is performed in which (64 × 2) arbitrary symbol data are inserted between two adjacent symbol data in the input data string.

③ (32,4) mode

In the (32, 4) mode, the input / output commutators 500 and 520 use the 32 symbol clocks as one cycle by the mode control signal 0101, and the taps increased by 4 from the first tap of the storage unit 510. Switching connection in sequence. At this time, the input / output commutator 500, 520 switches to the next tap in synchronization with the symbol clock, and starts repeatedly from the first tap after 32 symbol clocks (1 → 5 → 9,…, 125 → 1 →). 5…).

The first symbol data of the period input to the first tap of the storage is output without delay, the second symbol data to the 5th tap is 32 × 4 delayed, and the third symbol data to the 9th tap is 32 × 8 delayed. ,… , The last data of the cycle entered into tap 32 is output after 32 × 124 delay. As a result, on the transmitting side, interleaving is performed in which (32 x 4) arbitrary symbol data is inserted between two adjacent symbol data in the input data string.

④ (16,8) mode

In the (16,8) mode, the input / output commutators 500 and 520 use the 16-symbol clock as one cycle by the mode control signal 0111 to increase the taps increased by 8 from the first tap of the storage unit 510. Switching connection in sequence. At this time, the input / output commutator 500 and 520 are switched to the next tap in synchronization with the symbol clock, and are repeatedly executed starting from the first tap after 16 symbol clocks (1 → 9 → 17,…, 121 → 1 →). 9…).

The first symbol data of the period inputted into the 1st tap of the storage is output without delay, the second symbol data inputted to the 9th tap is 16x8 delayed, and the third symbol data inputted to the 17th tap is 16x16 delayed. ,… The last symbol data of the cycle input to tap 16 is output after a 16x120 delay. As a result, on the transmitting side, interleaving is performed in which (16 x 8) arbitrary symbol data are inserted between two adjacent symbol data in the input data string.

⑤ (8,16) mode

In the (8, 16) mode, the input / output commutators 500 and 520 use the eight symbol clocks for one cycle by the mode control signal 1001, and the tabs increased by 16 from the first tap of the storage unit 510. Switching connection in sequence. At this time, the input / output commutator 500, 520 switches to the next tap in synchronization with the symbol clock, and repeatedly starts from the first tap after eight symbol clocks (1 → 17 → 33,…, 113 → 1 →). 17…).

The first symbol data of the period input to the first tap of the storage is output without delay, the second symbol data to the 17th tap is 8 × 16 delayed, and the third symbol data to the 33rd tap is 8 × 32 delayed. ,… , The last symbol data of 8 cycles input to the 113th tap is output after 8 × 112 delay. As a result, on the transmitting side, interleaving is performed in which (8x16) arbitrary symbol data is inserted between two adjacent symbol data in the input symbol data string.

As described above, the present invention has a memory structure (storage unit) of (128,1) having the largest interleaving interval I and the smallest interleaving depth among the reduced interleaving five modes of the cable transmission system. The memory structure is shared by connecting to the memory taps which are increased by the interleaving interval J of the corresponding mode starting from the top tap 1 by the input / output commutator 500 and 520, thereby interleaving each mode.

As a result of sharing the memory, the amount of memory is much reduced compared to the conventional one. In fact, the total register capacity used when the five modes were separately designed was 15,552 symbols, but the total register capacity required by the present invention was 8,128 symbols. to be.

Although the present invention has been described herein only in connection with specific embodiments, it is applicable to programmable interleavers employing various interleaving modes.

In the related art, various interleavers were implemented separately, but inefficient. However, the present invention supports all five modes of reduced interleaving of the cable transmission system, but has an effect of reducing the memory side by 1/2 times compared to the conventional interleaver. In addition, by implementing a storage unit having the smallest interleaving depth and switching it with a memory tap increased by the corresponding interleaving depth according to each mode, the design is simple and the area and hardware amount can be reduced.

Claims (2)

Interleaving interval I (= N / J, integer where I≤M, M is the maximum value of the multimode interleaving interval), interleaving depth J (integer with p≤J, p is multimode interleaving) In weaving interleaving in two or more kinds of interleaving modes (I, J), which is the minimum of depth), An input commutator for distributing and outputting an input symbol according to a mode control signal for distinguishing an interleaving mode; A storage unit configured to store the symbols output from the input commutator while (i-1) registers are connected in series to the i th tab of the M tabs in a vertical direction; And And an output commutator for receiving and outputting the symbols of the storage unit according to the mode control signal and outputting the symbols. 2. The apparatus of claim 1, wherein the input and output commutators are connected to each symbol clock by switching to the same one of the M taps of the storage unit; The connected taps are interleaved interval I with one cycle, and the start of every cycle is connected with the tap 1 and the next tap is connected with the tap increased by J according to the interleaving depth J. Miniature interleaver for transmission.