KR19990076439A - A randomizing device of a digital transmission system - Google Patents

Abstract

The present invention relates to a randomizing apparatus for modifying data in order to obtain synchronization of symbol data during demodulation. More specifically, a randomization polynomial F (X) on a Galois field field GF (2 ^m ) in gemma feedback resistor unit for implementing the elements α ^K one randomized polynomial if in the field, the register part highest order output and the constant term α ^K to Galois field multiplication processing in the Galois field constant term treatment for feeding back to the register part lowest order input . The Galois field term processing obtains the Galois field element multiplied by α ^K by logic operation by appropriately manipulating the bits of the input element according to the multiplication rule determined according to the Galois field field in which the constant term exists.

Conventionally, since Galois field fields are stored in order to process an α ^K Galois field multiplication operation, considerable memory is required, and address manipulation of a memory is difficult. However, the present invention performs a Galois field multiplication operation by bit logic operation Therefore, memory is not needed, and it is easy to implement and high-speed processing is possible.

Description

A randomizer of a digital transmission system (Randomizer of digital transmission system)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a randomizing apparatus for modifying transmission symbol data to obtain synchronization of symbol data during demodulation.

Data transmitted in a digital transmission system is transmitted through a channel, is intertwined with other channels, or is exposed to various noises and is distorted. The receiver must recover the correct original data from the distorted data. In order to do this, the transmitting side randomizes the data and transmits the data, thereby maintaining the optimum reception state at the receiving side. In other words, by randomizing the information data by the pseudo noise code promised between the transmitting and receiving sides, it is possible to prevent interference with another channel during transmission and to extract a specific synchronization from the receiving side.

The pseudo noise code may be generated by a Galois field polynomial on the Galois field. An example of the pseudo noise code is a randomizing / de-randomizing device for downstream transmission of a cable modem network.

The cable modem network provides a variety of services such as telecommuting, video conferencing, and web browsing to subscribers by accessing the Internet and intranet along with ISDN and multi-digital subscriber line (xDSL).

1 is a block diagram of a cable modem network supporting broadband services. A head end 110 including a cable modem termination system (hereinafter referred to as " CMTS ") 111 is connected to a backbone network 100 including a private network or a public network provided by a network operator, And a cable modem 130 (Cable Modem: hereinafter referred to as CM) is connected. An optic / electro converter 120 is connected between the head end 110 and the CM 130 to convert an optical signal and an electrical signal. The CM 120 includes a photoelectric converter 120, a CM 130, The CM 130 and the subscriber side 140 are connected by a coaxial cable. Bidirectional communication is possible between the service provider and the subscriber, and two bi-directional communication paths are combined in the headend 110. [ The headend 110 includes an operation support system (not shown) for the CMTS 111, a CMTS 111 for enabling bidirectional communication, a combiner 112 for combining and transmitting various application services of the information provider, A transmission buffer 114, a reception buffer 115 and a distributor 113 for receiving and distributing data requested by the subscriber, a security and connection control unit 116, and the like. The CMTS 111 is provided with a network terminal 111-1 responsible for a network interface with the CMTS, a modulator 111-2 for modulating application service data (downstream data) of the information provider, And a demodulation unit 111-3 for demodulating the upstream data. The cable modem network shown in FIG. 1 is a broadband system using RF signals, and the RF interface exists between the CM and the cable network on the downstream, between the CMTS and the cable network on the downstream, and between the CMTS and the cable network on the upstream.

The downstream channels transmitted from the CMTS to each CM broadcast broadband service data at a transmission rate of 50 to 860 MHz. The upstream channel transmitted from each CM to the CMTS is transmitted to the subscriber in the range of 5 to 42 MHz, In a point-to-point manner.

The downstream protocol of the cable modem transmission system is as determined in ITU-T Recommendations J.83, Annex B, and the downstream signal processing procedure is shown in FIG. The downstream modulation is performed by framing the MPEG-2 data stream input in units of packets in the MPEG frame unit 200 and then performing a forward error correction algorithm in the FEC (Forward Error Correction) 230 to obtain reliable data. The FEC codeword output from the FEC encoder 210 is QAM modulated through the QAM modulator 220 and then transmitted through the cable channel 230 as an RF signal. Downstream demodulation is performed through the QAM demodulator 240, the FEC decoder 250, and the MPEG frame unit 260 in the reverse process of modulation. The MPEG framing process provides a parity check pattern for packet synchronization between transmitting and receiving sides, and the QAM modulation process supports 64QAM mode and 256QAM mode. The FEC encoding process uses a concatenated coding technique, an outer coder uses a Reed-Solomon code having T error correction capabilities, an inner coder, The TCM codeword for generating the coded modulation code is used to correct an uncorrectable error in the internal decoder by the external decoder so that the error rate is substantially zero.

3, the FEC encoder 210 (see FIG. 2) includes a Reed Solomon encoder 300, an interleaver 310, a randomizer 320, and a trellis encoder 330 The FEC decoder 250 includes a trellis decoder 350, a reverse randomizer 360, a deinterleaver 370, and a Reed Solomon decoder 380.

The Reed Solomon encoder 300 encodes the MPEG transport stream using the (128,122) RS block code. (128,122) The RS block code is composed of 128 symbols per block, of which only 122 symbols are information symbols and 6 symbols are parity for error correction, so that up to 3 symbols per RS block are error-corrected. The RS block codes are used in the 64QAM mode and the 256QAM mode.

The interleaver 310 performs convolutional interleaving on the (128,122) RS block codes to rearrange the data streams. The interleaver 310 is for effectively coping with a continuous error symbol (burst error) generated in the channel transmission. The convolutional interleaver structure supports a programmable structure in 64QAM mode and 256QAM mode, i.e., various interleaving modes.

The randomizer 320 randomizes the interleaved data so that the interleaved data does not have a specific pattern, thereby preventing the RF modulated signal from interfering with other channels and extracting the synchronization from the receiving side. Generates the pseudo noise code promised to the receiving side, and outputs the randomized data by adding the inputted pseudo noise code.

The trellis encoder 330 performs trellis coded modulation (TCM). TCM is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel, and is implemented by combining a coding technique and a modulation technique. The TCM structure consists of a finite convolutional encoder and a QAM modulator (64 / 256QAM).

Particularly, the randomizer 320 randomizes the data and transmits the data by using a QAM modulation technique to convert the carrier phase by the input bits and compare the phase shift value of the current symbol with the phase value of the next symbol This is because the transmitting side and the receiving side for synchronizing the original data are synchronized. If the receiving side is trying to synchronize, if the data bits of "1" or "0" are continuous for a long time, a data burst error that can not synchronize each data burst occurs. Therefore, the data bit stream is randomized and transmitted so that a sufficient phase change occurs in the receiver so that the received clock can be synchronized. In addition, it is important to make the FEC demodulation algorithm of a general receiver into a random pattern because the demodulated data sequence can not be properly demodulated if the modulated data string is not a random pattern.

The randomizer 320 randomizes the input data stream by adding input data, that is, 7-bit RS symbols, using 7-bit symbols as pseudo noise (PN) codes on the Galois field field GF 128. Also, while the synchronization signal of the FEC frame is inserted, the randomizer 320 is initialized, and operates from the time when the first symbol is actually input, and outputs a randomized symbol.

The randomization polynomial of the randomizer ^{F (X) = X 3 +} X + α 3 , The constant α ³ Is the polynomial of the Galois field field 7 alpha ⁷ + alpha ³ + 1 = 0 . The randomizer is basically composed of a feedback register according to the order and an adder for performing the exclusive OR operation on the input data to be randomized with the pseudo noise generated by the feedback register.

According to the patent application No. 97-73166 by the present inventors, in a conventional feedback randomized device register section Galois field constant processing unit that multiplies the maximum output and the difference Galois field constant α ³ of the register entered in the lowest order term of the register Respectively. The Galois field constant processing unit is provided with a memory storing all the elements on the Galois field. The Galois field constant processing unit matches the Galois field elements corresponding to the inputted maximum difference value, and then multiplies the Galois field elements, And outputs it as a result.

Therefore, the conventional randomizer has a disadvantage in that it takes a considerable amount of memory to process Galois field constants, and the processing time is delayed because memory access is required.

Accordingly, the present invention provides a randomizing device for presenting regularity between Galois field table elements for constant term processing of a randomized polynomial, and performing a Galois field multiplication operation with a simple bit logic combination according to the regularity, There is a purpose.

According to an aspect of the present invention, there is provided a method for transforming an input symbol into a Galois field field GF (2 ^m ) in which a constant of a randomization polynomial F (X) is an element α ^{K in a} Galois field except for '1' And outputting a randomized symbol to the maximum difference output of the feedback register unit and an input symbol to output a randomized symbol, the randomizer comprising:

Wherein the feedback register unit comprises: a plurality of register groups determined according to a randomization polynomial order; A Galois field constant (?) That provides a result obtained by performing? ^K multiplication by bit-logically combining the highest-order bits of the plurality of register groups in accordance with a predetermined rule, as a lowest difference input among the plurality of register groups ? ^K ) processing unit.

1 is a block diagram of a cable modem network,

2 is a block diagram illustrating a downstream signal processing procedure of a cable modem transmission system,

3 is a block diagram of the forward error correction unit of FIG. 2,

4 shows an element table on the Galois field GF (2 ⁷ )

FIG. 5 is a block diagram of a randomization apparatus implementing randomization polynomial F (X) = X ³ + X +? ³ according to the present invention,

FIG. 6 is a detailed view of the Galois field constant (? ³ ) processing unit of FIG.

Description of the Related Art [0002]

500: Feedback register section FR1 to FR3: Register

510: Galois field constant (α ^K ) processing unit 520, 530: Exclusive-

540:

600: Shift register unit 610:

620:

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

First, the Galois field field in which the randomizer operates is a number system having only a finite number of elements. The Galois field field indicated by GF (q) has q elements and performs various operations The resulting value is also a number system with one of the q elements. In particular, the finite Galois field system is useful for processing digital data because no overflow occurs. In addition, the number of elements of the Galois field GF ( ^2m ) in which GF (2) having {0,1} as an element is m-th degree expanded is 2 ^m , and only m bases are required to express all these elements . That is, the hardware can be implemented with m bits of binary digits. At this time, {alpha ⁰ , alpha ¹ , alpha ² , alpha ³ , ... ,? ^q } The basic base α is called the primitive element, and the polynomial with its root is called the primitive polynomial. A primitive polynomial is called a prime primitive polynomial, and a prime primitive polynomial is used to distinguish a field. Prime primitive polynomials are generally called field generator polynomials.

The field generating polynomial F (x), which is determined through the addition or multiplication operation on the Galois field field GF (2 ^m ) to be a value on the field, is also determined according to the value of m, The field generating polynomial is shown in Fig.

The field generator polynomial F (x) of GF (2 ^m ) m F (x) m F (x) 2 x ² + x + 1 6 x ⁶ + x + 1 3 x ³ + x + 1 7 x ⁷ + x ³ +1 4 x ⁴ + x + 1 8 x ⁸ + x ⁴ + x ³ + x ² + 1 5 x ⁵ + x ² + 1 9 x ⁹ + x ⁴ +1

The present embodiment is applied to a randomizing device or a reverse randomizing device implemented for a cable modem network downstream transmission. The randomization polynomial of this embodiment ^{F (X) = X 3 +} X + α 3 , Wherein the constant term α ³ Is the polynomial of the Galois field field 7 alpha ⁷ + alpha ³ + 1 = 0 .

Galois field field GF (2⁷) Are shown in Fig. Each element is expressed by the power of the element α. Element alphaⁱ(0 < = i < / = 126) is a 7-bit binary tuple (a₀, a_One, a₂, a₃, a₄, a₅, a₆),ⁱ= a₀+ a_Onealpha^One+ a₂alpha²+ a₃alpha³+ a₄alpha⁴+ a₅alpha⁵+ a₆alpha⁶. The 7-bit binary digit value of each element shown in Fig.₀ this LSB, and the rightmost a₆ This is the MSB.

A Galois field multiplication operation rule on the Galois field field is as follows. For example, the multiplicative value α ⁸ = (0,1,0,0,1,0,0) multiplied by the multiplier α = (0,1,0,0,0,0,0) is α ⁹ , The result of multiplying by the multiplier? ² is? ¹⁰ . Α ⁸ = (α ³ +1) α ² = α ⁵ + α ² = (0000010) + (0010000) = (0010010) = α ⁹ since α ⁷ = α ³ +1 by the prime primitive polynomial. As a result, the result is multiplied by an element that is increased by the degree of the element corresponding to the multiplier from the element corresponding to the multiplicand on the Galois field field table.

FIG. 5 is a block diagram of an embodiment of a randomization device implementing randomization polynomial F (X) = X ³ + X +? ³ according to the present invention.

The randomizer includes a feedback register unit 500 for providing a predetermined pseudo noise for transforming the input symbol, an adder 530 for performing an exclusive-OR operation on the input symbol and the pseudo noise of the feedback register unit, And an initialization unit 540 for providing an initial value of the feedback register.

The feedback register unit 500 receives the polynomial ^{F (X) = X 3 +} X + α 3 And the exclusive OR gate 520. The seven bit registers FR1, FR2, FR3, Galois constant (? ³ ) processing unit 510, The first exclusive OR gate 520 adds the contents of the first register FR1 and the contents of the third register FR3 to the second register FR2. The contents of the second register FR2 are provided to the third register FR3 and the contents of the third register FR3 are multiplied by the Galois field constant? ³ (through the Galois field constant processing unit 510) 1 register (FR1).

The value output from the third register FR3 of the feedback register unit 500 and the input RS symbol data to be actually randomized are subjected to exclusive OR computation through the adder 530 and transformed into a randomized symbol.

The initialization unit 540 initializes the first to third registers FR1 to FR3 and the Galois field constant processing unit 510 to 1111111 _{(2) by} receiving a control signal for initializing the entire receiving system, . The initialization timing is performed every frame. This is because the synchronization signal of the FEC frame must be transmitted as it is without being randomized. Therefore, while the synchronization signal is inserted, the registers FR1 to FR3 and the Galois field constant processing unit 510 are disabled, Since it must be enabled at the incoming point to generate the pseudo noise code.

The fact that the Galois field constant (? ³ ) processing unit 510 performs the? ³ multiplication operation means that when the element input to the basic element processing unit 510 is? ^I , the output thereof is? ^{I + 3} have. In other words. It is apparent that the Galois field multiplication result obtained by the fixed multiplier (? ³ ) is a Galois field element increased by a degree of multiplier from an arbitrary multiplicand (? ^I ). Since the corresponding element has already been determined, And the desired result can be obtained by operating it appropriately.

The rules for obtaining the multiplier result of fixed multiplier α ^K , K = 3 for any multiplicand α ⁱ on the Galois field are as follows:

- in GF (2 ^4): any multiplicand _{^{α i = (a 0, a}} 1, a 2, a 3) if the multiplication result ^{β = α i + 3 = (} a 1, a 2 ⊕ a ₁ , a ₃ ⊕ a ₂ , a ₀ ⊕ a ₃ ).

- GF (2 ⁵ ): multiplication result β = α ^{i + 3} = (a ₂ , a ₃ , a ₄ ) for any multiplicand α ⁱ = (a ₀ , a ₁ a ₂ a ₃ a ₄ ) ⊕ a ₂ , a ₀ ⊕ a ₃ , a ₁ ⊕ a ₄ ).

From GF (2 ^6): a random multiplicand _{^{α i = (a 0, a}} 1, a 2, a 3, a 4, a 5) if the multiplication result of ^{β = α i + 3 = (} a 3, a 4 ⊕ a ₃ , a ₅ ⊕ a ₄ , a ₆ ⊕ a ₅ , a ₁ , a ₂ ).

From GF (2 ^7): any multiplicand _{^{α i = (a 0, a}} 1, a 2, a 3, a 4, a 5, a 6) if the multiplication result of ^{β = α i + 3 = (} a 4 , a ₅ , a ₆ , a ₀ ⊕ a ₄ , a ₁ ⊕ a ₅ , a ₂ ⊕ a ₆ , a ₃ ).

FIG. 6 is a detailed diagram of the Galois field constant processing unit 510 of FIG. This embodiment applies the multiplication rule on GF (2 ⁷ ).

The Galois field constant processing unit 510 includes a shift register unit 600, a logical operation unit 610, and a buffer unit 620.

The shift register unit 600 has an annular shift register structure in which the output of the third register FR3 (see FIG. 5) is input, shifted by 3 bits to upper bits, and the output most significant bit is fed back to the least significant bit .

The logic operation unit 610 receives the MSB (a ₆ ), the MSB-1 (a), and the MSB-1 (a) of the outputs of the third register FR 3 while the three exclusive OR gates XOR 1 to XOR 3 are connected in parallel. _{5), MSB-2 (a} 4) of the shifted result bit by bit value from the shift register (600) MSB-1 (a 2), MSB-2 (a 1), MSB-3 (a 0) And performs bitwise OR operation on the bit values.

The buffer unit 620 receives the output bit of the logical operation unit 610 and the output bit of the logical operation unit 610 and temporarily stores the output bit and outputs the stored contents to the first register FR1 do.

That is, when the input to a third register of the element α ⁱ = output from the _{(FR3) (a 0, a} 1, a 2, a 3, a 4, a 5, a 6) are Galois field constant processor 510 The bit operation process is as follows. The output of the shift register unit 600 is (a ₄ , a ₅ , a ₆ , a ₀ , a ₁ , a ₂ , a ₃ ). The first gate (XOR) of the exclusive logical operation unit 610 is a ₂ ⊕ It is a _6-bit output MSB-1 beonjjae of the result of the calculation buffer unit 620. The second gate XOR2 is a ₁ ⊕ ₅ is a MSB-2 beonjjae output bits of the calculated result the buffer unit 620. The third gate XOR3 is a ₀ ⊕ and a _4-3 MSB of the operation result the buffer unit 620, the second output bits.

The MSB-1 to MSB-3 bits of the buffer unit 620 are received from the logical operation unit 610. [ The MSB, MSB-4, MSB-5, and LSB of the remaining bits of the buffer unit 620 are supplied with the same bit positions of the output bits of the shift register unit 600 as they are.

Accordingly, the content of the buffer unit 620 is divided into (a ₄ , a ₅ , a ₆ , a ₀ ⊕ a ₄ , a ₁ ⊕ a ₅ , a ₂ ⊕ a ₆ , a ₃ ).

As a result, the highest difference output of the third register FR3 in the feedback register unit 500 is multiplied by the? ^3- times multiplication result by the shifting and exclusive-OR operation of the Galois field constant processing unit 510 into the first register FR1 ) As the lowest difference input.

In the various systems that perform operations on the Galois field, the proposed Galois field multiplication rules may be effectively applied. For example, a system using a Reed-Solomon encoder / decoder or a Reed-Solomon symbol.

As described above, conventionally, in processing the constant term of the random polynomial, it is necessary to store all the Galois field elements and to read out the multiplication result, so that a considerable amount of memory is required, which leads to an increase in cost and a slow processing time . The present invention shows the regularity of the Galois field multiplication result on the Galois field, and it can be confirmed that the multiplication result is processed by a simple logical operation by bit manipulation of arbitrary multiplicand with respect to the fixed multiplier. The Galois field constants processing unit is a simple logic combination that performs an exclusive OR operation on the shifted bits of the multiplicand and the specific bits of the multiplicand, and is efficient in terms of cost, area, and processing speed.

Claims (4)

When the constant of the randomization polynomial F (X) on the Galois field field GF (2 ^m ) is an element? ^{K in} the Galois field except for '1', a feedback register unit for providing a predetermined code for transforming the input symbol And a randomizer for performing an exclusive OR operation on the highest difference output of the feedback register unit and the input symbol to output a randomized symbol, Wherein the feedback register unit comprises: a plurality of register groups determined according to a randomization polynomial order; A Galois field constant (?) That provides a result obtained by performing? ^K multiplication by bit-logically combining the highest-order bits of the plurality of register groups in accordance with a predetermined rule, as a lowest difference input among the plurality of register groups alpha ^K ) processing unit in the digital transmission system. The randomizer according to claim 1, wherein the Galois field constant processing unit (510) combines the bits of the input element according to a predetermined rule determined by the Galois field field in which the Galois field constant exists, and performs logic operation. The apparatus of claim 1, wherein the Galois field constant processing unit comprises: a shift register for shifting input element bits by K bits to upper bits and outputting the result in parallel; A logical operation unit performing an exclusive logical OR operation on a part of the input element and a part of output bits of the shift register; And a buffer unit for temporarily storing an output bit of the logic operation unit and an output bit of the shift register, the remaining bits being not provided to the logic operation unit. 3. The method of claim 2, wherein the predetermined rule for obtaining the multiplied result of the fixed multiplier < ^{RTI ID} = 0.0 > ³ < / RTI & - in ^{GF (2 4): α i} = (a 0, a 1, a 2, a 3) if the multiplication result _{^{α i + 3 = (a 1}} , a 2 ⊕ a ₁ , a ₃ ⊕ a ₂ , a ₀ ⊕ a ₃ ) - GF (2 ⁵ ): If the multiplication result α ^{i + 3} = (a ₂ , a ₃ , a ₄ ) for α ⁱ = (a ₀ , a ₁ a ₂ a ₃ a ₄ ) ⊕ a ₂ , a ₀ ⊕ a ₃ , a ₁ ⊕ a ₄ ) From ^{GF (2 6): α i} = (a 0, a 1, a 2, a 3, a 4, a 5) if the multiplication result _{^{α i + 3 = (a 3}} , a 4 ⊕ a ₃ , a ₅ ⊕ a ₄ , a ₆ ⊕ a ₅ , a ₁ , a ₂ ) From ^{GF (2 7): α i} = (a 0, a 1, a 2, a 3, a 4, a 5, a 6) if the multiplication result _{^{α i + 3 = (a 4}} , a 5, a ₆ , a ₀ ⊕ a ₄ , a ₁ ⊕ a ₅ , a ₂ ⊕ a ₆ , a ₃ ).