KR19990053510A - Scalable deinterleaver for downstream transmission of cable transmission systems - Google Patents

Abstract

The present invention relates to an extended interleaver that supports various extended deinterleaving modes (I, J) for downstream transmission of a cable transmission system.

The present invention is an input commutator for distributing and outputting the input symbols; (I-1) processing elements for storing the first input symbol of the period and (I-2) processing elements for storing the second input symbol of the period are connected in series with the interleaving interval I symbol as one period. ,… After storing the symbols output from the input commutator in the processing element, the processing elements for storing the (I-1) th input symbols of the I period are vertically connected and connected in series. A storage unit for selecting and outputting a symbol delayed by the interleaving depth J of the corresponding mode according to the mode control signal; And an output commutator for receiving and outputting the symbols output from the storage unit.

In the past, the deinterleaver in various modes was implemented separately, but the present invention is simple in design by sharing one memory by implementing one deinterleaver that supports various interleaving modes, and has an effect of reducing the area and the amount of hardware. have.

Description

Enhanced Deinterleaver of the cable transmission system in the downstream direction

The present invention relates to a cable transmission system and to an extended deinterleaver that supports various interleaving modes for downstream transmission.

Cable modem network provides various services such as telecommuting, video conferencing, and web search to subscribers by connecting to internet and intranet together with Integrated Information Communication Network (ISDN) and Multi-Digital Subscriber Line (xDSL).

1 is a reference diagram of a cable modem network that supports broadband service. A headend 110 including a cable modem terminal system (111, hereinafter referred to as CMTS) is connected to a backbone network 100 including a private network or a public network provided by a communication network operator. The cable modem (130, Cable Modem: hereinafter referred to as CM) is connected. Between the head end 110 and the CM (130) is located a photoelectric converter (120, Optic / Electro Converter) is connected by the optical cable to convert the optical signal and the electrical signal, the photoelectric converter 120 and the CM (130), The CM 130 and the subscriber side 140 are connected by coaxial cable. Bi-directional communication is possible between the service provider and the subscriber side, and the two bidirectional communication paths are combined at the headend 110. The headend 110 includes a CMTS 111 that enables bidirectional communication, an operation support system for the CMTS 111 (not shown), and a combiner 112 that transmits various application services of an information provider by combining data signals. And a transmission buffer 114, a reception buffer 115 and a distributor 113 for receiving and distributing subscriber request data, and a security and access control unit 116. The CMTS 111 includes a network terminal 111-1 in charge of the CMTS and a network interface, a modulator 111-2 for modulating application service data (downstream data) of an information provider, and request data of a subscriber ( Demodulation section 111-3 for demodulating upstream data). The cable modem network shown in FIG. 1 is a broadband system using RF signals, and an RF interface exists between the CM and the cable network, between the CMTS and the cable network downstream, and between the CMTS and the cable network upstream.

The downstream channel transmitted from CMTS to each CM broadcasts broadband service data at a transmission rate of 50 to 860 MHz, and the upstream channel transmitted from CM to CMTS is 5 to 42 MHz. Send in a point-to-point fashion

The downstream protocol of the cable transmission system is as defined in ITU-T Recommendations J.83, Annex B. The downstream signal processing is shown in FIG. The downstream modulation process is performed by framing the MPEG-2 data stream input in the packet unit from the MPEG frame unit 200, and then performing a forward error correction algorithm in the FEC encoder 210 to perform a channel ( To obtain reliable data. The FEC code output from the FEC encoder 210 is QAM modulated by the QAM modulator 220 and then transmitted through the cable channel 230 as an RF signal. The downstream demodulation is performed through the QAM demodulator 240, the FEC decoder 250, and the MPEG frame unit 260 in a reverse process to modulation. The MPEG framing process provides a parity check pattern for packet synchronization between the transmitter and the receiver. The QAM modulation process supports 64QAM mode and 256QAM mode. The FEC encoding process uses a concatenated coding technique, and an outer coder uses a Reed-Solomon code having T error correction capabilities, and an inner coder. By using the TCM codeword to generate the coded modulation code, the error that is not corrected by the internal decoder is usually corrected by the external decoder so that the error rate is almost zero.

3, the FEC encoder 210 (see FIG. 2) is composed of a Reed Solomon encoder 300, an interleaver 310, a randomizer 320, and a trellis encoder 330. The FEC decoder 250 includes a trellis decoder 350, an inverse randomizer 360, a deinterleaver 370, and a Reed Solomon decoder 380.

The Reed Solomon encoder 300 encodes the MPEG transport stream using a (128,122) RS block code. (128, 122) The RS block code consists of 128 symbols per block, of which only 122 symbols are information symbols and 6 symbols are parity for error correction, so up to 3 symbols per RS block are error corrected. The RS block code is used identically in the 64QAM mode and the 256QAM mode.

The interleaver 310 convolutionally interleaves the (128, 122) RS block codes to rearrange the data streams. The interleaver 310 is for efficiently coping with successive error symbols (cluster errors, burst errors) generated during channel transmission. The convolutional interleaver structure supports a programmable structure, that is, various interleaving modes in 64QAM mode and 256QAM mode.

The randomization unit 320 randomizes the interleaved data so that the interleaved data does not have a specific pattern, thereby preventing the RF-modulated signal from interfering with other channels and extracting synchronization from the receiver. Randomized data is output by generating a pseudo noise code promised with the receiver and adding it to the input data.

The trellis encoder 330 performs trellis coded modulation (TCM). TCM is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel and is implemented by combining a coding technique and a modulation technique. The TCM structure is composed of a convolutional encoder having a finite state and a QAM modulator (64 / 256QAM).

A process of convolutional interleaving by receiving an RS block code in symbol units in the interleaver 310 will be described with reference to FIG. 4.

4 is a circuit diagram illustrating a convolutional interleaver and a deinterleaver. The convolutional interleaver 400 includes an input commutator 410, a plurality of shift register stages 1 to I, and an output commutator 420. The convolutional deinterleaver 450 is composed of an input commutator 460, a plurality of shift register stages 1 to I having an opposite structure to the convolutional interleaver, and an output commutator 470.

In the shift register structure of the convolutional interleaver, the top tab 1 is directly connected to an input and an output without a shift register, and the shift register length is " 0 ", and from the next taps 2 to I, the " J " "2J", "3J",... , As long as "(I-1) J". The memory difference between successive register tabs stores more "J" symbols than the registers in the previous tab. The register width is 7 bits, which is the same as that of the RS symbol since the RS block code is processed in symbol units.

The shift register structure of the convolutional deinterleaver 450 has a structure opposite to that of the shift interleaver 400. In other words, the top tab 1 has a shift register length of "(I-1) J", and from the next tabs 2 to I, "(I-2) J",... , "2J", "J", "0" has a length as long as.

The input commutator 410 of the convolutional interleaver 400, the output commutator 420, the input commutator 460 of the deinterleaver 450, and the output commutator 470 all operate in synchronization. Data is interleaved by switching sequentially from the first tap to the last I-1 tap according to the symbol clock, and then repeatedly switching from the first tap. Through this switching operation, the first data of the I cycle input to the first tap of the convolutional interleaver 400 is output without a delay, and the second data of the I cycle input to the second tap is input to the third tap after an IJ delay. The third data is after a 2IJ delay,... , The last data of cycle I input to tap I is output after (I-1) IJ delay.

As a result, in the interleaver 400 on the transmitting side, IJ arbitrary symbol data is inserted between two neighboring symbol data in the input data string and transmitted to the convolutional deinterleaver 450 on the receiving side through the channel 430.

The first data of the I cycle input to the first tap of the convolutional deinterleaver 450 is output after (I-1) IJ delay, and the second data of the I cycle to the second tap is (I-2) IJ delay ,… , The last second data of cycle I entered through tap I-1 is output after J delay, and the last data of cycle I entered into tap I is output without delay.

As a result, after the system is operated, the original data stream that was input to the convolutional interleaver 400 after the (I-1) IJ delay is obtained.

In general, the specification of the convolutional interleaver is represented by the (I, J) parameter, where I represents the number of taps in the shift register, which is called an interleaving interval, and J is an interleaving depth representing a register increment between neighboring taps. This is called interleaving depth.

Meanwhile, in the cable transmission system, the interleaver specification supports the reduced interleaving mode and the extended interleaving mode. Among them, there are 8 types of extended interleaving modes (I, J) = (128,1), (128,2), (128,3), (128,4), (128,5), (128,6) , (128,7), (128,8) are supported. The extended interleaving mode is obtained by increasing the interleaving depth J while the interleaving interval I is constant. Therefore, the transmitter needs an interleaver as shown in FIG. 4 according to the five modes, and the receiver requires a corresponding deinterleaver. The minimum amount of memory required to design the deinterleaver as shown in FIG. (symbols). In designing the eight deinterleavers in the extended interleaving mode, respectively, in designing the eight interleavers in the extended interleaving mode, respectively, (128,1) mode is 8,128 symbols, (128,2) mode is 16,256 symbols, ( 128,3) mode is 24,384 symbols, (128,4) mode is 32,512 symbols, (128,5) mode is 40,640 symbols, (128,6) mode is 48,768 symbols, (128,7) mode is 56,896 symbols, ( 128,8) mode requires a register to store 65,024 symbols. In addition, each input / output commutator is required for each deinterleaver.

This has a problem that the amount of the hardware can not be ignored if implemented in the general logic (LOGIC) or ASIC (custom semiconductor).

Accordingly, the present invention has been made to solve the above problems, the present invention is to provide a mode control signal while sharing the memory in a system employing two or more interleaving modes, such as the extended interleaving mode of the cable transmission system The purpose is to provide a deinterleaver supporting the corresponding mode.

In order to achieve the above object, the present invention provides a block data stream consisting of N symbols, wherein the interleaving interval I (= N) and the interleaving depth J (an integer of 1≤J≤P) are two or more interleaving modes (I, J). Receiving interleaved data through a channel and performing deinterleaving on a symbol-by-symbol basis, the input commutator distributing and outputting an input symbol; With the interleaving interval I as a period, (I-1) processing elements for storing the first input symbol of the period are connected in series, and (I-2) processing elements for storing the second input symbol of the period are Connected in series,… In addition, one processing element for storing the I-1th input symbol of the I period is continuously connected in a vertical direction, and the symbols output from the input commutator are stored in the corresponding processing element, and then the mode control signal is stored in the processing element. A storage unit for selecting and outputting a symbol delayed by an interleaving depth J of a corresponding mode; And an output communicator for receiving and outputting the symbols output from the storage unit.

1 is a reference configuration diagram of a cable modem network supporting broadband services;

2 is a block diagram showing a downstream signal processing procedure of a cable transmission system;

3 is a detailed block diagram of a forward error correction unit of FIG. 2;

4 is a detailed circuit diagram of the interleaver / deinterleaver of FIG.

5 is a block diagram of an extended deinterleaver for downstream transmission according to the present invention;

FIG. 6 is a detailed circuit diagram of a processing element of the extended deinterleaver of FIG. 5.

Explanation of symbols on the main parts of the drawings

500: input commutator 510: storage unit

520: output commutator PE: processing element

R1 to R8: Register MUX: Multiplexer

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

This embodiment relates to a reduced interleaving mode supported in both 64QAM / 256QAM modes of a cable transmission system. The parameters of the extended interleaving mode and corresponding mode control signals are shown in Table 1.

Mode control signal (4 bits) I (# of taps) J (increment) Burst Defense 0000 128 One 95㎲ / 66㎲ 0010 128 2 190㎲ / 132㎲ 0100 128 3 285㎲ / 198㎲ 0110 128 4 379㎲ / 264㎲ 1000 128 5 474㎲ / 330㎲ 1010 128 6 569㎲ / 396㎲ 1100 128 7 664㎲ / 462㎲ 1110 128 8 759㎲ / 528㎲

In Table 1 above, the interleaving parameters I and J are appropriately selected for a given channel, and these parameter values are also related to burst defenses. In Table 1, the extended interleaving mode shows that burst defense increases as J increases when the I value is constant. Control information (4 bits) of the extended interleaving mode is transmitted to the receiver during the FEC frame synchronization interval, and the receiver performs deinterleaving of the corresponding mode for a given channel.

5 is a block diagram of an extended deinterleaver for downstream transmission according to the present invention. Expandable deinterleaver with 8 modes supports interleaved data with an interleaving interval 128 and interleaving depth J = 1,2,3,4,5,6,7,8. It receives the input and rearranges the data in order of data before interleaving of the corresponding mode according to the mode control signal.

Referring to FIG. 5, the extended deinterleaver stores an input commutator 500 for distributing input symbols and a symbol allocated from the input commutator 500 in a corresponding memory and interleaving depth J of a corresponding mode according to a mode control signal. It is composed of a storage unit 510 for delaying and outputting the delayed output, and an output communicator 520 for receiving and outputting the symbols output from the storage unit 510.

The storage unit 510 has eight modes (128,1), (128,2), (128,3), (128,4), (128,5), (128,6), (128,7) Has a processing element (PE) for supporting (128,8). Tab 1 of the storage unit 510 has 127 processing elements PE connected in series, and tap 2 has 126 processing elements PE connected in series,. In the tap 127, one (I-i) processing element PE is connected in series with each i-th tap such that one processing element PE is connected. The last tab 128 has no processing element (PE) and the input commutator 500 and the output commutator 520 are directly connected.

The input commutator 500 and the output commutator 520 are synchronized with each other to perform a switching operation on the same tap. The switching order is sequentially synchronized from the tap 1 to the tap 128 from the first symbol input with the interleaving interval 128 symbols in one cycle in synchronization with the symbol clock. Then repeat from tab 1 again.

6 is a detailed circuit diagram of the processing element PE of the storage unit 510. In the processing element PE, eight registers R1 to R8 that store one input symbol per register are connected in series. When a symbol is input by receiving the input symbol as R1, the next register is sequentially registered. Shift to. According to the mode control signal, a symbol delayed by the interleaving depth J of the corresponding mode is selected from the symbols output from the R1, R2, R3, R4, R5, R6, R7, and R8 registers through the multiplexer (MUX). The mode control signal uses 4 bits that distinguish the eight modes shown in Table 1.

The front processing element of each tap is input from the input commutator 500 and its output is passed to the next connected processing element, and the output of the last processing element is passed to the output commutator 520.

Hereinafter, the operation and effect of the present embodiment will be described with reference to FIGS. 5 and 6.

① (128, 1) mode

In the (128, 1) mode, interleaved data strings are inserted with (128 × 1) arbitrary symbols between adjacent symbols among 128 symbols corresponding to one period.

On the receiving side, the input interceptor 500 of the deinterleaver switches the taps 1 to 128 of the storage unit 510 in order according to the symbol clock for one period to distribute the input symbols. In the (128, 1) mode, each processing element PE selects and outputs the output of the register R1 by the mode control signal 0000. Therefore, the first data of a period input to tap 1 of the convolutional deinterleaver is output after a 127 × 128 symbol clock delay, and the second data of a period input to tap 2 is 126 × 128 symbol clock delay. The last second data input to tap 127 is output after one symbol clock delay, and the last data to tap 128 is output without delay. As a result, the deinterleaver starts to operate and gets the original data stream before being interleaved after a (127 x 128) symbol clock delay. At this time, the output commutator 520 is also synchronized with the input commutator 500 to switch the same tap.

② (128, 2) mode

In the case of (128, 2) mode, (128 x 2) arbitrary symbols are inserted between adjacent symbols at the time of input for interleaved data strings with one cycle of 128 symbols.

On the receiving side, the input intercommuter 500 of the deinterleaver switches the taps 1 to 128 of the storage unit 510 in sequence according to the symbol clock to distribute the input symbols. In the (128, 2) mode, the processing element PE selects and outputs the output of the register R2 by the mode control signal 0010. Therefore, the first data of the period input to the tap 1 of the convolutional deinterleaver is output after a (128 × 254) symbol clock delay, and the second data to the second tap is input after a (128 × 252) symbol clock delay,. In this case, the last second data input to tap 127 is output after the delay of 2 symbol clocks, and the last data to tap 128 is output without delay. As a result, the original data stream is obtained after the deinterleaver starts to operate but before interleaving after a (128 × 254) delay. At this time, the output commutator 520 is also synchronized with the input commutator 500 to switch the same tap.

③ (128, 3) mode

In the case of (128, 3) mode, the interleaved data string is transmitted to the interleaver with 128 symbols at one cycle, and (128 × 3) arbitrary symbols are inserted between adjacent symbols at the time of input into the interleaver.

On the receiving side, the input intercommuter 500 of the deinterleaver switches the taps 1 to 128 of the storage unit 510 in sequence according to the symbol clock to distribute the input symbols. In the (128, 3) mode, the processing element PE selects and outputs the output of the register R3 by the mode control signal 0100. Therefore, the first data of the period input to the tap 1 of the convolutional deinterleaver is output after a (128 × 361) symbol clock delay, and the second data to the second tap is input after a (128 × 368) symbol clock delay. The last second data input to tap 127 is output after 3 symbol clock delays, and the last data to tap 128 is output without delay. As a result, the original data stream is obtained after the deinterleaver starts operation (128 × 361) but before interleaving after a delay (128 × 361). At this time, the output commutator 520 is also synchronized with the input commutator 500 to switch the same tap.

In the remaining (I, J) = (128, 4), (128, 5), (128, 6), (128, 7), and (128, 8) modes, each processing element is controlled by the mode control signal in the same manner as above. From the eight registers of (PE), the content of the Jth register, that is, the symbol delayed by the interleaving depth J is selected, transferred to the next processing element, and the input data order is rearranged and output (deinterleaving).

As described above, the present invention supports all of the extended interleaving 8 modes of the cable transmission system, but it can be clearly seen that the memory is reduced in comparison with the conventional deinterleaver. In practice, the total register capacity used when 8 modes were separately designed was 292,608 symbols, but the total register capacity required by the present invention was 65,024 symbols.

Although the present invention has been described in terms of specific embodiments only, those skilled in the art can practice variously within the purview of the claims and embodiments.

As described above, in the related art, various deinterleavers were implemented inefficiently, but the present invention implements one deinterleaver that supports various interleaving modes to share a memory, and corresponds to an interleaving depth according to a mode control signal. By selecting the symbol, the design is simple and the area and hardware amount can be reduced.

Claims (2)

Receive interleaved interleaved data through the channel in a block data stream consisting of N symbols in two or more interleaving modes (I, J) with an interleaving interval I (= N) and an interleaving depth J (an integer of 1≤J≤P). Receive and deinterleave symbolically, An input commutator for distributing and outputting an input symbol; With the interleaving interval I as a period, (I-1) processing elements for storing the first input symbol of the period are connected in series, and (I-2) processing elements for storing the second input symbol of the period are Connected in series,… In addition, one processing element for storing the I-1th input symbol of the I period is continuously connected in a vertical direction, and the symbols output from the input commutator are stored in the corresponding processing element, and then the mode control signal is stored in the processing element. A storage unit for selecting and outputting a symbol delayed by an interleaving depth J of a corresponding mode; And And an output commutator for receiving and outputting the symbols output from the storage unit. The extended deinterleaver for the downstream transmission of the cable transmission system. The method according to claim 1, wherein the input commutator is sequentially synchronized with the output commutator from the first tap to the first tap of the storage unit according to a symbol clock for each period with I symbols of interleaving intervals as one period; The I-th tap outputs the last input symbol of an I period to the output commutator without delay; The n th tap except for the I th tap is delayed by the interleaving depth J (I-1) through (In) processing elements storing the n th input symbol of the I period, and then transferred to the output commutator. Scalable deinterleaver for downstream transmission of cable transmission systems.