KR19990066555A - Deinterleaver for downstream transmission of cable modem transmission system - Google Patents

Abstract

The present invention relates to a deinterleaver that supports various deinterleaving modes (I, J) for downstream transmission of a cable transmission system.

According to the present invention, M tabs are positioned in a vertical direction so that (Mi) processing elements are connected in series to the i th tap of the M taps, and each processing element stores an input symbol and then expands the extended mode control signal and the reduced mode. A storage unit is provided for delaying and outputting the interleaving depth J of the corresponding mode according to the control signal and the mode selection signal, and the storage unit is shared and used in each mode by the control signal. In order to share the storage unit, an input / output commutator for distributing symbols appropriately for the corresponding mode is provided by using a reduced mode control signal and a mode selection signal.

In the related art, various deinterleavers were implemented separately, but inefficient. However, the present invention supports all of the various deinterleavers, but the design is simple and the area and hardware amount can be reduced.

Description

Deinterleaver of the cable transmission system in the downstream direction

The present invention relates to a cable modem transmission system, and more particularly, to a deinterleaver that simultaneously supports a reduced interleaving mode and an extended interleaving mode for downstream transmission.

Cable modem network provides various services such as telecommuting, video conferencing, and web search to subscribers by connecting to internet and intranet together with Integrated Information Communication Network (ISDN) and Multi-Digital Subscriber Line (xDSL).

1 is a reference diagram of a cable modem network that supports broadband service. A headend 110 including a cable modem terminal system (111, hereinafter referred to as CMTS) is connected to a backbone network 100 including a private network or a public network provided by a communication network operator. The cable modem (130, Cable Modem: hereinafter referred to as CM) is connected. Between the head end 110 and the CM (130) is located a photoelectric converter (120, Optic / Electro Converter) is connected by the optical cable to convert the optical signal and the electrical signal, the photoelectric converter 120 and the CM (130), The CM 130 and the subscriber side 140 are connected by coaxial cable. Bi-directional communication is possible between the service provider and the subscriber side, and the two bidirectional communication paths are combined at the headend 110. The headend 110 includes a CMTS 111 that enables bidirectional communication, an operation support system for the CMTS 111 (not shown), and a combiner 112 that transmits various application services of an information provider by combining data signals. And a transmission buffer 114, a reception buffer 115 and a distributor 113 for receiving and distributing subscriber request data, and a security and access control unit 116. The CMTS 111 includes a network terminal 111-1 in charge of the CMTS and a network interface, a modulator 111-2 for modulating application service data (downstream data) of an information provider, and request data of a subscriber ( Demodulation section 111-3 for demodulating upstream data). The cable modem network shown in FIG. 1 is a broadband system using RF signals, and an RF interface exists between the CM and the cable network, between the CMTS and the cable network downstream, and between the CMTS and the cable network upstream.

The downstream channel transmitted from CMTS to each CM broadcasts broadband service data at a transmission rate of 50 to 860 MHz, and the upstream channel transmitted from CM to CMTS is 5 to 42 MHz. Send in a point-to-point fashion

The downstream protocol of the cable transmission system is as defined in ITU-T Recommendations J.83, Annex B. The downstream signal processing is shown in FIG. The downstream modulation process is performed by framing the MPEG-2 data stream input in the packet unit from the MPEG frame unit 200, and then performing a forward error correction algorithm in the FEC encoder 210 to perform a channel ( To obtain reliable data. The FEC code output from the FEC encoder 210 is QAM modulated by the QAM modulator 220 and then transmitted through the cable channel 230 as an RF signal. The downstream demodulation is performed through the QAM demodulator 240, the FEC decoder 250, and the MPEG frame unit 260 in a reverse process to modulation. The MPEG framing process provides a parity check pattern for packet synchronization between the transmitter and the receiver. The QAM modulation process supports 64QAM mode and 256QAM mode. The FEC encoding process uses a concatenated coding technique, and an outer coder uses a Reed-Solomon code having T error correction capabilities, and an inner coder. By using the TCM codeword to generate the coded modulation code, the error that is not corrected by the internal decoder is usually corrected by the external decoder so that the error rate is almost zero.

3, the FEC encoder 210 (see FIG. 2) is composed of a Reed Solomon encoder 300, an interleaver 310, a randomizer 320, and a trellis encoder 330. The FEC decoder 250 includes a trellis decoder 350, an inverse randomizer 360, a deinterleaver 370, and a Reed Solomon decoder 380.

The Reed Solomon encoder 300 encodes the MPEG transport stream using a (128,122) RS block code. (128, 122) The RS block code consists of 128 symbols per block, of which only 122 symbols are information symbols and 6 symbols are parity for error correction, so up to 3 symbols per RS block are error corrected. The RS block code is used identically in the 64QAM mode and the 256QAM mode.

The interleaver 310 convolutionally interleaves the (128, 122) RS block codes to rearrange the data streams. The interleaver 310 is for efficiently coping with successive error symbols (cluster errors, burst errors) generated during channel transmission. The convolutional interleaver structure supports a programmable structure, that is, various interleaving modes in 64QAM mode and 256QAM mode.

The randomization unit 320 randomizes the interleaved data so that the interleaved data does not have a specific pattern, thereby preventing the RF-modulated signal from interfering with other channels and extracting synchronization from the receiver. Randomized data is output by generating a pseudo noise code promised with the receiver and adding it to the input data.

The trellis encoder 330 performs trellis coded modulation (TCM). TCM is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel and is implemented by combining a coding technique and a modulation technique. The TCM structure is composed of a convolutional encoder having a finite state and a QAM modulator (64 / 256QAM).

A process of convolutional interleaving by receiving an RS block code in symbol units in the interleaver 310 will be described with reference to FIG. 4.

4 is a circuit diagram illustrating a convolutional interleaver and a deinterleaver. The convolutional interleaver 400 includes an input commutator 410, a plurality of shift register stages 1 to I, and an output commutator 420. The convolutional deinterleaver 450 is composed of an input commutator 460, a plurality of shift register stages 1 to I having an opposite structure to the convolutional interleaver, and an output commutator 470.

In the shift register structure of the convolutional interleaver, the top tab 1 is directly connected to an input and an output without a shift register, and the shift register length is " 0 ", and from the next taps 2 to I, the " J " "2J", "3J",... , As long as "(I-1) J". The memory difference between successive register tabs stores more "J" symbols than the registers in the previous tab. The register width is 7 bits, which is the same as that of the RS symbol since the RS block code is processed in symbol units.

The shift register structure of the convolutional deinterleaver 450 has a structure opposite to that of the shift interleaver 400. In other words, the top tab 1 has a shift register length of "(I-1) J", and from the next tabs 2 to I, "(I-2) J",... , "2J", "J", "0" has a length as long as.

The input commutator 410 of the convolutional interleaver 400, the output commutator 420, the input commutator 460 of the deinterleaver 450, and the output commutator 470 all operate in synchronization. Data is interleaved by switching sequentially from the first tap to the last I-1 tap according to the symbol clock, and then repeatedly switching from the first tap. Through this switching operation, the first data of the I cycle input to the first tap of the convolutional interleaver 400 is output without a delay, and the second data of the I cycle input to the second tap is input to the third tap after an IJ delay. The third data is after a 2IJ delay,... , The last data of cycle I input to tap I is output after (I-1) IJ delay.

As a result, in the interleaver 400 on the transmitting side, IJ arbitrary symbol data is inserted between two neighboring symbol data in the input data string and transmitted to the convolutional deinterleaver 450 on the receiving side through the channel 430.

The first data of the I cycle input to the first tap of the convolutional deinterleaver 450 is output after (I-1) IJ delay, and the second data of the I cycle to the second tap is (I-2) IJ delay ,… , The last second data of cycle I entered through tap I-1 is output after J delay, and the last data of cycle I entered into tap I is output without delay.

As a result, after the system is operated, the original data stream that was input to the convolutional interleaver 400 after the (I-1) IJ delay is obtained.

In general, the specification of the convolutional interleaver is represented by the (I, J) parameter, where I represents the number of taps in the shift register, which is called an interleaving interval, and J is an interleaving depth representing a register increment between neighboring taps. This is called interleaving depth.

Meanwhile, in the cable transmission system, the interleaver specification supports the reduced interleaving mode and the extended interleaving mode. Among them, the reduced interleaving mode supports five types: (I, J) = (128,1), (64,2), (32,4), (16,8), (8,16). have. There are eight types of extended interleaving modes: (I, J) = (128,1), (128,2), (128,3), (128,4), (128,5), (128,6) , (128,7), (128,8) are supported. Each of the deinterleavers shown in FIG. 4 according to 13 modes is required. The minimum amount of memory required to design one deinterleaver as shown in FIG. (symbols).

Therefore, in designing the deinterleaver according to each mode, the reduced deinterleaver has 8,128 symbols in (128,1) mode, 4,032 symbols in (64,2) mode, 1,984 symbols in (32,4) mode, ( The 16,8) mode requires 960 symbols, and the (8,16) mode requires a register to store 448 symbols. In case of extended deinterleaver, (128,1) mode is 8,128 symbol, (128,2) mode is 16,256 symbol, (128,3) mode is 24,384 symbol, (128,4) mode is 32,512 symbol, (128,5) mode 40,640 symbols, 48,768 symbols in (128,6) mode, 56,896 symbols in (128,7) mode, and 65,024 symbols in (128,8) mode respectively. In addition, each input / output commutator is required for each deinterleaver.

This has a problem that the amount of the hardware can not be ignored if implemented in the general logic (LOGIC) or ASIC (custom semiconductor).

Accordingly, the present invention has been made to solve the above problems, the present invention provides a multi-mode deinterleaver that simultaneously supports the reduced mode and extended mode by using a part of the shared memory according to the mode. There is a purpose.

In order to achieve the above object, the present invention provides an interleaving interval I (an integer of I≤M, M is a maximum value of a multimode interleaving interval) and an interleaving depth J (an integer of 1≤J). In deinterleaving interleaved data in various interleaving modes (I, J) according to the mode, M tabs are positioned in the vertical direction so that (Mi) processing elements are serially connected to the i th tap of the M taps. While connected to each processing element, each of the processing element is a storage unit for outputting the delayed by the interleaving depth J of the corresponding mode according to the extended mode control signal, the reduced mode control signal and the mode selection signal after storing the input symbol; An input communicator for sequentially allocating input symbols to taps of the storage unit corresponding to a corresponding mode according to a reduced mode control signal and a mode selection signal; And an output commutator for receiving and outputting the output symbols of the storage unit in the order of taps corresponding to the corresponding modes according to the reduced mode control signal and the mode selection signal.

1 is a reference configuration diagram of a cable modem network supporting broadband services;

2 is a block diagram showing a downstream signal processing procedure of a cable modem transmission system;

3 is a detailed block diagram of a forward error correction unit of FIG. 2;

4 is a detailed circuit diagram of the interleaver / deinterleaver of FIG.

5 is a block diagram of a deinterleaver for downstream transmission according to the present invention;

FIG. 6 is a detailed circuit diagram of the processing elements of FIG. 5.

Explanation of symbols on the main parts of the drawings

500: input commutator 510: storage unit

520: output commutator PE # 1: first processing element

PE # 2: second processing element

R1 to R16: Shift register MUX: Multiplexer

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

This embodiment relates to reduced and extended interleaving modes supported in both 64QAM / 256QAM modes of a cable transmission system. The parameters of the reduced and extended interleaving modes are shown in Table 1.

Mode symbol I (# of taps) J (increment) Burst Defense R1_MODE 128 One 95㎲ / 66㎲ R2_MODE 64 2 47㎲ / 33㎲ R3_MODE 32 4 24㎲ / 16㎲ R4_MODE 16 8 12㎲ / 8.2㎲ R5_MODE 8 16 5.9㎲ / 4.1㎲ E1_MODE 128 One 95㎲ / 66㎲ E2_MODE 128 2 190㎲ / 132㎲ E3_MODE 128 3 285㎲ / 198㎲ E4_MODE 128 4 379㎲ / 264㎲ E5_MODE 128 5 474㎲ / 330㎲ E6_MODE 128 6 569㎲ / 396㎲ E7_MODE 128 7 664㎲ / 462㎲ E8_MODE 128 8 759㎲ / 528㎲

In Table 1 above, the interleaving parameters I and J are appropriately selected for a given channel, and these parameter values are also related to burst defenses. It can be seen from Table 1 that the reduced interleaving modes (R1_MODE to R5_MODE) decrease I when the value of I × J is constant and burst defense decreases as J increases. In the extended interleaving mode (E1_MODE to E8_MODE), when I is constant, the burst defense increases as J increases. The control signal for distinguishing the extended / reduced interleaving mode is transmitted to the receiving side during the FEC frame synchronization interval, and the receiving side performs deinterleaving of the corresponding mode for a given channel.

5 is a block diagram of a deinterleaver for supporting reduced and extended modes for downstream transmission of the present invention.

The RS block data stream consisting of 128 RS symbols in the interleaver on the transmitting side is divided into five reduced modes (128,1), (64,2), (32,4), (16,8), and (8,16). Or 8 extended modes (128,1), (128,2), (128,3), (128,4), (128,5), (128,6), (128,7), (128, 8) Convolutional interleaving in any one of the transmission. The deinterleaver on the receiving side receives the interleaved data stream and rearranges the data in the data order before interleaving in the corresponding mode.

The deinterleaver of FIG. 5 includes an input communicator 500, a storage unit 510, and an output communicator 520 that weaving and deinterleaving a corresponding mode by a control signal. The control signal used in this embodiment is a reduced mode control signal (R) for distinguishing the reduced type 5 mode, an extended mode control signal (E) for distinguishing the extended 8 mode, and distinguishing whether it is a reduced type or an extended type. There is a mode selection signal (S). The reduced mode control signal R and the mode selection signal S are provided to the input communicator 500, the storage unit 510, and the output communicator 520, and the extended mode control signal E is stored. Provided to section 510.

Since the maximum interleaving interval in the 13 mode is 128 (= M), the storage unit 510 has 128 tabs arranged in the vertical direction and (Mi) processing elements (PE) for storing symbols in each i-th tap. ) Are arranged in series.

The processing element type of each tap uses the first processing element (PE # 1) from taps 1 to 120, and the second processing element from taps 121 to 127, depending on the number of registers constituting the processing element. # 2) is used.

That is, 127 first processing elements PE # 1 are connected in series to tab 1, and 126 first processing elements PE # 1 are connected in series to tab 2, and so on. PE # 1) is located. There are seven second processing elements (PE # 2) connected in series in tab 121, one fewer than the number of processing elements in the previous tap, and one second processing element (PE # 2) is connected in series in tab 127. .

FIG. 6 is a detailed circuit diagram of the processing elements of FIG. 5.

FIG. 6A illustrates a first processing element (PE # 1), in which eight registers R1 to R8 that store one input symbol per register are connected in series and receive the input symbol as R1 to input the next symbol. Each time one symbol is shifted in sequence. The eight-input one-output multiplexer (MUX) has the control signals, i.e., the extended mode control signal (E), the reduced mode control signal (R), and the mode selection signal (S). From among the symbols output from the R7, R8th registers, a symbol delayed by the interleaving depth J of the corresponding mode is selected and output.

FIG. 6B shows a second processing element (PE # 2), in which 16 registers R1 to R16, which store one input symbol per register, are connected in series and receive the input symbol as R1 to input the next symbol. Each time one symbol is shifted in sequence. The nine-input one-output multiplexer (MUX) has the control signals, i.e., the extended mode control signal (E), the reduced mode control signal (R), and the mode selection signal (S). Selects and outputs the symbols delayed by the interleaving depth J of the corresponding mode among the symbols output from the R7, R8, and R16th registers.

The first processing element of each tap receives a symbol from the input commutator 500 and outputs it after a predetermined time delay, and the output thereof is transferred to the next connected processing element, and the output of the last processing element is output to the output commutator 520. Delivered.

The input commutator 500 and the output commutator 520 are switched to the same tap (tap of the storage unit 510) in synchronization with each other according to the mode selection signal S and the reduced mode control signal R. Do it. For example, when the reduced mode is selected by the mode selection signal S, the reduced mode control signal R causes (128,1), (64,2), (32,4), (16 (8) and (8, 16) modes are determined, and accordingly, the tab number order of the storage unit 510 connected to the input / output commutators 500 and 520 is determined. On the other hand, when the extended mode is selected by the mode selection signal S, the tab order of the storage unit 510 connected to the input / output commutator 500.520 regardless of the mode type is 128 starting from the first tap. It connects sequentially in increments of 1 to the tab, and then repeats from tab 1 again.

First, the operation in the reduced mode for the present embodiment will be described with reference to FIGS. 5 and 6, and in the following, the extended mode will be described.

１. Miniature mode

Referring to FIG. 5, the tap number order of the input / output commutators 500 and 520 in the reduced mode is as follows. In tabs 1-128 in (128,1) mode, in tabs 65-128 in (64,2) mode, in tabs 97-128 in (32,4) mode, (16,8) The mode is allocated sequentially to the tabs 113 to 128, and to the tabs 121 to 128 in the (8, 16) mode. This switching sequence is repeated with the interleaving interval I as a period.

Referring to FIG. 6A, among the symbols stored in the eight registers R1 to R8 of the first processing element PE # 1 in the reduced mode, it is selected as follows. Select the symbol of R1 in (128,1) mode, the symbol of R2 in (64,2) mode, the symbol of R4 in (32,4) mode, and the symbol of R8 in (16,8) mode. Output In the (8, 16) mode, the first processing element PE # 1 is not used.

Referring to FIG. 6B, among the symbols stored in the registers R1 to R8 of the second processing element PE # 2 in the reduced mode, it is selected as follows. Symbol of R1 in (128,1) mode, symbol of R2 in (64,2) mode, symbol of R4 in (32,4) mode, symbol of R8 in (16,8) mode, (8 , 16) mode, selects and outputs the symbol of R16.

The operation of the embodiment for the (128,1) and (64,2) modes will be described by applying the above rules.

① (128,1) mode

In the (128, 1) mode, the transmitting side generates an interleaving data string in which (128 × 1) arbitrary symbols are inserted between two adjacent symbols at the time of input using 128 symbols as one cycle.

The receiving side receives and deinterleaves the interleaved data in the (128,1) mode. The input / output commutators 500 and 520 of the deinterleaver sequentially switch and connect taps increased by 1 from tap 1 to tap 128 of the storage unit 510 using 128 symbol clocks as one cycle. The input / output commutator 500,520 switches to the next tap in synchronization with the symbol clock, and repeats it starting from the first tap after 128 symbol clocks (1 → 2 → 3,…, 128 → 1 → 2…). ).

The first and second processing elements PE # 1 and PE # 2 of the storage unit 510 select and output the contents of the register R1 delayed by one symbol from among the registers.

Therefore, the first symbol data of the period inputted to the first tap of the deinterleaver is output after a 127 × 128 symbol clock delay, and the second symbol data inputted to the second tap is 126 × 128 symbol clock delayed. In this case, the last second symbol data input to the 127th tap is output after 1 symbol clock delay, and the last symbol data input to the 128th tap is output without delay. As a result, the deinterleaver starts to operate and gets the original data stream before being interleaved after a (127 x 128) symbol clock delay.

② (64, 2) mode

In the (64, 2) mode, the transmitter generates an interleaving data string in which 64 symbols are inserted between two adjacent symbols at the time of input using 64 symbols as one cycle.

The receiving side receives and deinterleaves the interleaved data in the (64, 2) mode. The input / output commutators 500 and 520 of the deinterleaver sequentially switch the taps increased by 1 from the 65th tap to the 128th tap of the storage unit 510 using 64 symbol clocks as one cycle. At this time, the input / output commutator 500,520 switches to the next tap in synchronization with the symbol clock, and repeats the operation starting from the tap 65 again after the 64 symbol clock (65 → 66 → 67,…, 128 → 65 →). 66…).

The first and second processing elements PE # 1 and PE # 2 of the storage unit 510 select and output the contents of the register R2 delayed by two symbols among the registers.

Therefore, the first symbol data of the period input to the tap 65 of the storage unit 510 is output after the 64 × 126 delay, the second symbol data input to the tap 66 is input to the tap 67 after the delay 64 × 124 The third symbol data is delayed after 64 x 120 delays. In this case, the last second symbol data input to tap 127 is output after a 64 × 2 delay, and the last symbol data of a period input to tap 128 is output without a delay. Eventually, we get the original data stream after the deinterleaver starts operating but before interleaving after a 64x126 symbol clock delay.

As shown in the (128, 1), (64, 2) mode, the rest of the (32, 4), (16, 8), and (8, 16) modes of the input / output commutator (500, 520) described above Since the processing proceeds in the same way according to the switching order and the output symbol rules of the processing elements PE # 1 and PE # 2 of the storage unit 510, the description will be omitted below. As a result, the (32,4) mode has 32 × 124 symbol clock delays, the (16,8) mode has 16 × 120 symbol clock delays, and the (8,16) mode has 8 × 112 symbol clocks before interleaving. You can get a stream.

2. Expandable mode

Referring to FIG. 5, in the extended mode, the input / output commutators 500 and 520 sequentially increase the taps increased by one tap according to the symbol clock from the first to the 128th taps with an interleaving interval of 128 (= I). Switch to the input symbol.

Referring to FIG. 6A, among the symbols stored in the eight registers R1 to R8 of the first processing element PE # 1 in the extended mode, it is selected as follows. Symbol of R1 in (128,1) mode, symbol of R2 in (128,2) mode, symbol of R3 in (128,3) mode,... In the (128,8) mode, a symbol delayed by the interleaving depth J is selected and output in each processing element PE # 1, such as selecting a symbol of R8. The second processing element PE # 2 of FIG. 6B also performs the same operation as the first processing element PE # 1.

The operation of the embodiment for the (128,2) mode will be described by applying the above rules.

In the (128, 2) mode, interleaved data strings are inserted with (128 × 2) arbitrary symbols between two adjacent symbols among 128 input symbols corresponding to one period.

In the deinterleaver on the receiver side, in the (128,2) mode, the input / output commutators 500 and 520 are moved from tab 1 to tab 128 of the storage unit 510 according to the symbol clock for 128 symbol clocks (1 cycle). Allocates input symbols by switching in order.

The output of R2 is selected and output from among the registers of the first and second processing elements PE # 1 and PE # 2 of the storage unit 510.

Therefore, the first symbol data of the period input to the first tap of the storage unit 510 is output after a (128 × 254) symbol clock delay, and the second symbol data to the second tap is a (128 × 252) symbol clock delay. After,… The second symbol data input to tap 127 is output after the delay of 2 symbol clocks, and the last symbol data input to tap 128 is output without delay. As a result, the original data stream is obtained after the deinterleaver starts operation but before the interleaving after a (128 × 254) symbol clock delay.

As shown in the (128, 2) mode, the switching order and the angle of the input / output commutator 500 and 520 described above also in the remaining I = 128, J = 1,3,4,5,6,7,8 modes. Since the process proceeds in accordance with the output symbol rule (symbol delayed by the interleaving depth J) of the processing element PE, it will be omitted below.

As described above, the present invention shares a memory (storage unit 510) to support both the reduced and extended interleaving 13 modes of the cable transmission system, and the memory selectively selects a symbol of the corresponding mode according to a control signal. It consists of a number of processing elements that are output. The input commutator and output commutator on the input side and the output side of the storage unit appropriately distribute the input / output symbols according to the control signal to perform deinterleaving in each mode. That is, the present invention is designed to program each processing element (PE) of the input / output commutator (500, 520) and the storage unit 510 (I × J) after the system starts operation for each (I, J) mode (I × J The original data stream is obtained after the symbol clock.

This sharing of memory results in a much smaller amount of memory than in the past.

In the present specification, the present invention has been described only in connection with specific embodiments. However, the present invention can be applied to a programmable deinterleaver employing various interleaving modes, and those skilled in the art can make various changes within the technical spirit of the claims and embodiments. Can be.

In the related art, various deinterleavers were separately implemented and inefficient. However, the present invention has implemented one deinterleaver that supports both the reduced and extended interleaving 13 modes of the cable transmission system. According to the present invention, the memory is shared by appropriately distributing the symbols of the corresponding mode according to the control signal, thereby simplifying the design and reducing the area and the amount of hardware. Compared with the conventional deinterleaver, the memory side is reduced by about 1/6 times.

Claims (3)

A block data stream consisting of N symbols is divided into various interleaving modes (I, J) having an interleaving interval I (an integer of I≤M, M is a maximum value of a multimode interleaving interval) and an interleaving depth J (an integer of 1≤J). In deinterleaving convolutional interleaved data in the corresponding mode, (M) processing elements are connected in series to the i th tap of the M taps in a vertical direction, and each processing element stores an input symbol and then expands the mode control signal and the scale mode control signal. And a storage unit for delaying and outputting the interleaving depth J of the corresponding mode according to the mode selection signal. An input communicator for sequentially allocating input symbols to taps of the storage unit corresponding to a corresponding mode according to a reduced mode control signal and a mode selection signal; And According to the reduced mode control signal and the mode selection signal, the downstream transmission of the cable modem transmission system comprising an output commutator for receiving and outputting the output symbols of the storage unit in the order of taps corresponding to the corresponding mode. Deinterleaver for The semiconductor device of claim 1, wherein the processing element comprises: a shift register configured to sequentially shift one symbol each time an input symbol is input while predetermined registers for storing the input symbol are connected in series; And And a multiplexer for selecting and outputting a symbol delayed by an interleaving depth of a corresponding mode among the parallel output symbols of the shift register. 2. The apparatus of claim 1, wherein the input commutator and the output commutator are connected to each symbol clock by switching to the same one of the M taps of the storage unit; In the extended mode constant with the parameter I = N of the interleaving mode (I, J), the switching sequence is connected to the tap increased by +1 starting from the first tap of every cycle with the interleaving interval I as one period; In the reduced mode constant with the parameter IJ = N of the interleaving mode (I, J), the switching sequence starts sequentially from the tap of (M-I + 1) of each cycle with the interleaving interval I as one period, and sequentially +1. A deinterleaver for downstream transmission of a cable transmission system, characterized by switching to the last M-th tap, such as connected to taps incremented by taps.