KR19990052812A - Multilayer semiconductor package and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a structure of a stacked package and a method of manufacturing the same for improving signal transmission capability between leads of packages of each layer in the stacked semiconductor package. The stacked semiconductor package of the present invention has a plurality of stacked layers, each of which has a plurality of packages having a plurality of outleads for signal transmission between the semiconductor chip and an external circuit, and corresponding leads of the packages in each layer. A stacked semiconductor package including a plurality of rails electrically connected to each other, the out lead of the package being rotated by 90 degrees from an end of the body portion by a predetermined length, and a groove is formed in the rail to insert the rotated portion of the lead. Thereby electrically connecting the corresponding leads of the plurality of packages.

Description

Multilayer semiconductor package and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a structure of a side rail and a semiconductor package and a method of manufacturing the same, for connecting between the out leads of a semiconductor package stacked in a stacked semiconductor package.

Package diversification, miniaturization and multipinning are underway. In order to meet the demands of electronic devices such as small size, light weight, high speed, and high performance, semiconductor packages have been continuously developed in various forms and types. Corresponding to the use of electronic devices, the proper use of the semiconductor package is important. Logic semiconductors, such as central processing units (CPUs) and on-demand semiconductors (ASICs), require more multi-output pins as their functions become more advanced. The System On Silicon mindset pushes the growth of semiconductor chip sizes and pushes the size of packages. At the same time, the problems of package electrical characteristics and heat dissipation due to the high speed of chips have become important issues in the structural design of packages. Packages corresponding to these include a pin grid array (PGA), a ball grid array (BGA), a multi chip module (MCM), a quad flat package (QFP), and the like. There is the same improvement type. For memory semiconductor products, the miniaturization and thinning of packages are the center of development. As a memory, there is a strong demand for packaging a large capacity semiconductor chip with high density. From this point of view, a thin Small Outerlead Package (TSOP) with a 1.0 mm package thickness, Ultra Thin Small Outerlead Package (UTSOP) or a vertical surface is further thinned to a 0.5 mm thickness. Package Vertical Packages (SVPs) have been developed. These packages are mounted at high density on a printed board to realize high density of the entire memory module.

However, only miniaturization and thinning of such packages themselves have limitations in realizing high density and high capacity packages. To overcome this limitation, a stacked semiconductor package has been proposed in which a plurality of packages are stacked to electrically connect corresponding leads to each other.

1 is a perspective view of a stacked semiconductor package according to the related art, in which four semiconductor chips are stacked. FIG. 2A is a perspective view of a side rail used in the stacked semiconductor package of FIG. 1, and FIG. 2B shows a state in which an out lead of each semiconductor package is connected to the side rail of FIG. 2A.

Referring to FIG. 1, four semiconductor packages 2 are stacked, and a plurality of side rails 6 are stacked in order to electrically connect corresponding out leads 4 of the stacked packages to each other. Are provided on both sides.

When the out leads 4 are attached only to the side rails 6 by soldering, the side rails 6 have a grooveless structure as shown in FIG. 2A. However, in this case, there is a disadvantage that the contact portion between the out lead 4 and the side rail 6 falls due to an external impact, and the contact area between the side rail 6 and the out lead 4 is small so that the signal is transmitted. Has the disadvantage of increasing resistance. Therefore, as shown in FIG. 2B, a plurality of grooves are formed in the side rails 6, and the out leads 4 of the semiconductor package in each layer are inserted into the grooves.

However, even in the case of insertion, as in Fig. 2B, since the width w2 of the insertion portion 4a of the side rail 4 is smaller than the width w1 of the out lead 4, the resistance is still high. In other words, since the resistance is inversely proportional to the length of the wiring and proportional to the cross-sectional area, when the contact area of the side rails 6 is small, the resistance increases and signal transmission is not smooth. In order to prevent this, as shown in Figs. 3 to 5, a groove is formed in the side rail 6, the outlead 4 is inserted into the groove to increase the contact area, or the out leads are bent to contact the side rail. The method was presented. In the drawing, reference numeral 10 denotes a printed circuit board, and 12 denotes a wiring formed on the printed circuit board 10.

However, these methods also have limitations in reducing resistance because the width of the out lead is larger than that of the side rails, and there are disadvantages in that the work process according to the manufacture of the lead is complicated and difficult.

Accordingly, the present invention has been made to solve the above problems, and can reduce the manufacturing cost, while reducing the contact resistance between the outlead and the side rails and at the same time simplifying the manufacturing process thereof, and a manufacturing method thereof. The purpose is to provide.

1 is a perspective view of a stacked semiconductor package according to the prior art.

2A and 2B are partial perspective views of side rails of the stacked semiconductor package of FIG.

3 to 5 are partial cross-sectional views illustrating a connection structure of an out lead and a side rail of a semiconductor package according to the related art.

6A to 6B are cross-sectional views of each semiconductor package used in the stacked semiconductor package according to the embodiment of the present invention, and FIG. 6C is a plan view of each semiconductor package.

7 is a perspective view of a side rail used in a stacked semiconductor package according to an embodiment of the present invention.

8 is a partial cross-sectional view of a stacked semiconductor package according to an embodiment of the present invention.

9 is a partial cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

62: package body 64, 64 ': lead

66: side rail 68: polyimide

70: adhesive

According to the present invention, a plurality of semiconductor packages are stacked, each of which has a plurality of packages having a plurality of out leads for signal transmission between the semiconductor chip and an external circuit, and corresponding leads of the packages in each layer. A stacked semiconductor package including a plurality of rails electrically connected to each other, the out lead of the package being rotated by 90 degrees from a end of the body portion by a predetermined length, and a groove is formed in the rail to form a rotated portion of the lead. Inserting to electrically connect corresponding leads of the plurality of packages.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

6A and 6B are cross-sectional views illustrating a preparation process of each package used in the stacked semiconductor package of the present invention, and FIG. 6A illustrates a body 62 for protecting a semiconductor chip from an external environment, such as an epoxy molding compound. After the construction, the length L1 of the outlead protruding outward of the body portion is cut from 30 to 50 mil (1 mil corresponds to 1 / 1,000 inch, or 0.254 μm) from the end of the body portion. 6B is a cross-sectional view of the deformed state in order to mount the outlead on the side rail, and holds and fixes the portion l2 from the end of the package body portion 62 to 10 to 15 mils, and the remaining portion thereof. Shows the configuration rotated by 90 °.

FIG. 6C is a plan view of each semiconductor package having the modified leads as shown in FIG. 6B, and partially shows a right part of the package.

FIG. 7 schematically shows a configuration of the side rails 66 for stacking the prepared packages and then electrically connecting the corresponding leads to each other. To interconnect the 64's.

Referring to FIG. 7, the side rails 66 have grooves into which the out leads are inserted along their longitudinal direction to interconnect the out leads arranged in a row in the stacked state. The width of the groove is formed to be similar to or slightly larger than the thickness of the out lead so that only the rotated portion of the out lead 64 'is inserted, as shown in FIGS. 6B and 6C. In addition, the groove of the side rail 66 may be formed to be similar to or slightly larger than the width of the out lead so that a part of the unrotated portion is inserted together with the rotated portion, but in this case, the width of the side rail 66 is Since it is wider, the spacing between adjacent leads must be sufficiently secured, and thus the spacing between the out leads is widened, so that it is difficult to have many out leads in one package. Therefore, it is preferable that the side rail has a structure in which only the rotated portion is inserted into the groove. In addition, it is preferable that the depth of the groove is 10-15 mil so that the groove depth thereof corresponds to the rotated portion of the out lead of the semiconductor package.

FIG. 8 is a cross-sectional view illustrating a state in which packages and side rails connected to packages prepared as shown in FIGS. 6A to 6C and 7 are vertically cut based on one side rail 66.

Referring to FIG. 8, the rotated portions of the out leads 64 ′ of the stacked packages are inserted into the grooves of the side rails 66 and attached to the inner wall surfaces of the grooves by soldering. In FIG. 9, the dotted line portion indicated on the side rail 66 indicates the position of the groove.

9 is according to another embodiment of the present invention. As shown in FIG. 8, the outer leads 64 ′ and the side rails 66 of the stacked packages are connected to each other, and the surface of the package stacked on the top is shown. The conductive material film is easily laminated with heat dissipation. The conductive material film is made of copper or beryllium, and attached to the upper surface of the package with an adhesive tape 70 having good heat resistance and heat dissipation.

As described above, the semiconductor package of the present invention has the following effects.

First, the contact area between the out leads and the side rails is increased, so that electrical signals are quickly transferred between the leads of each package.

Second, since a predetermined portion of the out leads of the package is only rotated and prepared, and grooves are formed in the side rails, work time can be shortened.

Third, since the out leads are inserted into and fixed in the grooves of the side rails, the problem that the out leads are separated from the side rails due to external impact or other factors can be prevented.

Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (12)

A plurality of stacked packages, each of which has a plurality of packages having a plurality of outleads for signal transmission between the semiconductor chip and an external circuit, A stacked semiconductor package comprising a plurality of rails electrically connecting corresponding leads of packages in each layer to each other, wherein the out lead of the package is rotated 90 degrees from a end of the body portion by a predetermined length. And forming a groove to insert the rotated portion of the lead to electrically connect the corresponding leads of the plurality of packages. 2. The stacked semiconductor package of claim 1, wherein the out lead of each package has a length of 30 to 50 mils. 2. The stacked semiconductor package of claim 1, wherein the rotated portion of the out lead is 10-15 mils from an end of the body portion of the package. 2. The stacked semiconductor package of claim 1, wherein the side rail has a groove depth corresponding to a rotated portion of the out lead of the semiconductor package. 5. The stacked semiconductor package of claim 4, wherein the depth of the groove is 10-15 mils. The multilayer semiconductor package of claim 1, further comprising a conductive material film on a surface of a package located at the top of the plurality of stacked packages to facilitate external heat emission. The multilayer semiconductor package of claim 6, wherein the conductive material layer is formed of one material selected from copper and beryllium. A plurality of stacked packages, each of which has a plurality of packages having a plurality of outleads for signal transmission between the semiconductor chip and an external circuit, Prepare a plurality of rails having grooves into which the outleads are inserted, and electrically connecting the corresponding leads of the packages in each layer to each other, and rotating the outleads by 90 degrees over a predetermined length from the end of the body portion. Making a step; And inserting and rotating the rotated portions of the outleads of the package into the grooves of the rails. 10. The method of claim 8, wherein the out lead of each package has a length of 30 to 50 mils. 9. The method of claim 8, wherein the rotated portion of the out lead is 10-15 mils from an end portion of the body portion of the package. 10. The method of claim 8, wherein the side rail has a groove depth corresponding to a rotated portion of the out lead of the semiconductor package. The method of claim 11, wherein the groove has a depth of 10-15 mils.