KR19990049232A - Semiconductor memory capable of reproducing address - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory capable of reproducing an address. In the related art, if a small capacity DRAM in a region in which a defect does not occur can be used if it is determined to be a defect in a test of a large capacity DRAM, it is rejected to reduce production efficiency. There was a problem. In view of the above problems, the present invention provides a low buffer and a column buffer for receiving and buffering a low address and a column address; A row decoder and a column decoder for receiving word lines and bit lines of a memory cell array by receiving and decoding the outputs of the low and column buffers; A semiconductor memory comprising a sense amplifier for sensing and outputting data of a memory cell array cell in which a word line and a bit line are selected, and when a defect occurs in any one of the low addresses during a test of the semiconductor memory, the low address is switched. When a large memory cell is judged to be defective through a semiconductor memory capable of reproducing an address, which further includes an address switching unit which is switched through the memory, the rejected process can be switched to a smaller capacity, thereby improving production efficiency and economy. There is.

Description

Semiconductor memory capable of reproducing address

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory capable of reproducing an address. In particular, when a defect occurs in a cell of one address during a test of a large capacity (for example, 256M) DRAM, a small capacity in which the defect does not occur by replacing the address with another cell ( For example, the present invention relates to a semiconductor memory capable of reproducing an address suitable for use with 128M DRAM.

FIG. 1 is a block diagram showing a conventional 64M RAM. As shown in FIG. 1, a row for selecting a word line of a memory cell array 3 by decoding a low address through a low buffer 1 is shown. A decoder 2; A column decoder 5 for receiving and decoding the column address through the column buffer 4; A sense amplifier 6 for sensing and outputting data of a cell corresponding to a bit line selected through the row decoder 2 and the column decoder 5; The sense amplifier 6 and the input / output pad 8 are composed of an input / output buffer 7 which buffers data to input and output data. The operation of the conventional circuit as described above will be described below.

First, in the case of a read operation, the low address is buffered through the low buffer 1, and then decoded by the low decoder 2 to select a word line of the memory cell array 3, wherein the column address is a column buffer ( After buffering through 4), it is decoded by the column decoder 5 to select a bit line of the memory cell array 3.

As described above, the sense amplifier 6 senses data of the memory cell array 3 cells corresponding to the selected word line and the bit line and outputs the data to the input / output pad 8 through the input / output buffer 7.

In the case of a write operation, the row decoder 2 and the column decoder 5 decode the low address and the column address as described above, select a word line and a bit line of the memory cell array 3, and set a target cell. Thereafter, the data to be written is applied through the input / output pad 8 and the input / output buffer 7 to write the data to the target cell of the memory cell array 3.

However, in the conventional circuit as described above, if it is determined that the defect is a defect in the test of the large-capacity DRAM, there is a problem in that the production efficiency is reduced due to the reject process despite the use of the small-capacity DRAM in the region where the defect does not occur. .

The present invention was devised to solve the above problems, and an object of the present invention is that when a defect is determined during the test of a large capacity DRAM using the same protocol of the same package, the defect does not occur. An object of the present invention is to provide a semiconductor memory capable of reproducing an address that can use a small capacity DRAM in an unoccupied area.

Figure 1 is a block diagram showing a conventional 64M RAM.

Figure 2 is a block diagram showing an embodiment of the present invention.

3 is a detailed circuit diagram of a switch in FIG.

*** Description of the symbols for the main parts of the drawings ***

11: Address change part 12: Low decoder

13: Memory cell array 14: Column buffer

15: Column decoder 16: Sense amplifier

17: I / O buffer 18: I / O pad

An object of the present invention as described above is a low buffer and a column buffer for receiving and buffering the low address and column address; A row decoder and a column decoder for receiving word lines and bit lines of a memory cell array by receiving and decoding the outputs of the low and column buffers; A semiconductor memory comprising a sense amplifier for sensing and outputting data of a memory cell array cell in which a word line and a bit line are selected, and when a defect occurs in any one of the low addresses during a test of the semiconductor memory, the low address is switched. It is achieved by further comprising an address switching unit for switching through the, and will be described in detail with reference to Figures 2 and 3 attached to the semiconductor memory capable of reproducing the address according to the present invention.

First, Figure 2 is a block diagram showing an embodiment of the present invention, the address switching unit 11 for switching the address when a failure occurs during the test of a large capacity DRAM by receiving a low address as shown therein; A row decoder 12 for decoding the output of the address switching unit 11 and selecting a word line of the memory cell array 13; A column decoder 15 which receives the column address through the column buffer 14 and decodes the bit address of the memory cell array 13 to select the bit line; A sense amplifier 16 for sensing and outputting data of the memory cell array 13 corresponding to the selected word line and the bit line through the row decoder 12 and the column decoder 15; The sense amplifier 16 and the input / output pad 18 are configured with an input / output buffer 17 for buffering the input and output of data. The address switching section 11 receives the low addresses input from the address pads PAD0 to PAD9, respectively. Low buffers BUF0 through BUF9 that receive and buffer the switches SW0 through SW9, respectively; The low addresses input from the address pads PAD0 to PAD8 are constituted by switches SW10 to SW19 such that the low addresses are connected between the switch SW9 and the low buffer BUF9.

3A is a detailed circuit diagram of the switches SW0 to SW9, and FIG. 3B is a detailed circuit diagram of the switches SW10 to SW19. As shown therein, the switches SW0 to SW9 are connected to the power supply voltage VCC. A fuse FU1 and a resistor R1 connected in series between the grounds; A resistor R2 and a fuse FU2 connected in series between the power supply voltage VCC and ground; The transmission gate TG1 receives the output between the fuse FU1 and the resistor R1 at the positive terminal, receives the output between the resistor R2 and the fuse FU2 at the negative terminal, and transmits the low address. The switch SW10 to SW19 receive the output between the fuse FU1 and the resistor R1 at the negative terminal, and receive the output between the resistor R2 and the fuse FU2 at the positive terminal. It consists of a transmission gate (TG2) for blocking the low address.

Hereinafter, the operation of one embodiment of the present invention as described above will be limited to the operation of selecting a bit line by applying a low address, which is the subject of the present invention.

First, when there is no defect in the test of the memory cell array 13, the switches SW0 to SW9 in the address switching unit 11 are turned on, and the switches SW10 to SW19 are shut off, so that the address pad PAD0 is the same as before. Each low address input through ˜PAD9 is buffered through the low buffers BUF0 to BUF9 and input to the low decoder 12 to select a bit line of the memory cell array 13.

When the memory cell array 13 is tested, for example, when a defect occurs in the address pad PAD8, the switches SW0 to SW7 are turned on, and the switches SW10 to SW17 are shut off, and the switches SW8 and SW9 are turned off. By cutting the fuses FU1 and FU2 shown in Fig. 3A, the transfer gate TG1 is switched from the transfer state to the cutoff state so that the switches SW8 and SW9 are cut off, and the switches SW18 and SW19 are shown in Fig. 3B. By disconnecting the illustrated fuses FU1 and FU2, the transfer gate TG2 is switched from the cutoff state to the transfer state so that the switches SW18 and SW19 are conducted.

Therefore, the low address input through the address pads PAD0 to PAD7 selects the bit lines of the memory cell array 13 through the low buffers BUF0 to BUF7 and the low decoder 12 as described above, The low address input through the PAD8 is input to the low buffer BUF9 through the switches SW18 and SW19, buffered, and then input to the low decoder 12 to select the bit line of the memory cell array 13. do.

The semiconductor memory capable of reproducing the address according to the present invention as described above can be used to switch the rejected process to a small capacity when a large memory cell is determined to be defective, thereby improving the production efficiency and economic aspects. .

Claims (3)

A low buffer and a column buffer which receive and buffer the low address and the column address; A row decoder and a column decoder for receiving word lines and bit lines of a memory cell array by receiving and decoding the outputs of the low and column buffers; A semiconductor memory comprising a sense amplifier for sensing and outputting data of a memory cell array cell in which a word line and a bit line are selected, and when a defect occurs in any one of the low addresses during a test of the semiconductor memory, the low address is switched. And an address switching unit for switching over to output to the low buffer. 2. The apparatus of claim 1, wherein the address switching unit comprises: low buffers BUF0 to BUF9 which receive and buffer low addresses respectively inputted from the address pads PAD0 to PAD9 through the switches SW0 to SW9; A semiconductor capable of reproducing an address, characterized in that the low addresses inputted from the address pads PAD0 to PAD8 are constituted by switches SW10 to SW19 such that the low addresses are connected between the switch SW9 and the low buffer BUF9. Memory. 3. The switch of claim 2, wherein the switches SW0 to SW9 include: a fuse FU1 and a resistor R1 connected in series between the power supply voltage VCC and ground; A resistor R2 and a fuse FU2 connected in series between the power supply voltage VCC and ground; The transmission gate TG1 receives the output between the fuse FU1 and the resistor R1 at the positive terminal, receives the output between the resistor R2 and the fuse FU2 at the negative terminal, and transmits the low address. The switches SW10 to SW19 include a fuse FU1 and a resistor R1 connected in series between the power supply voltage VCC and ground; A resistor R2 and a fuse FU2 connected in series between the power supply voltage VCC and ground; The transmission gate TG2 which receives the output between the fuse FU1 and the resistor R1 at the negative terminal and blocks the low address input by receiving the output between the resistor R2 and the fuse FU2 at the positive terminal. And a semiconductor memory capable of reproducing an address.