JPH1116385A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device whose defective memory cells can be substituted even after the package is sealed. SOLUTION: A semiconductor memory device has a UPROM(universal PROM) spare row decoder 1 which decodes the row addresses of defective cells in a memory array 17, a UPROM spare column decoder 2 which decodes the column addresses of the defective cells and a substitution control circuit 3. The substitution control circuit 3 selects whether the defective cell is substituted by the spare memory cells with respect to rows or with respect to columns. Further, the substitution control circuit 3 controls the writing of defect address information into the UPROM. If the defects are produced after the package is sealed, the defect address information in the memory array 17 which is detected by a memory test device (not shown) is stored in the UPROM. With this constitution, the defective cells in the memory array 17 are substituted by the spare memory cells with respect to the rows or with respect to columns.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device capable of replacing a defective memory cell with a spare memory cell.

[0002]

2. Description of the Related Art Since a DRAM has a simple memory cell structure, the capacity of the DRAM is still being increased by miniaturization technology. However, as the miniaturization progresses, bit defects, column defects, and row defects in the memory array due to crystal defects, impurities, and the like tend to increase.

In order to reduce such defects, spare memory cells are provided in advance in a memory chip, and defective memory cells are stored in units of rows (rows) or columns (columns).
A method of replacing in units has been put to practical use.

FIG. 3 is a block diagram showing an internal configuration of a conventional semiconductor memory device having spare memory cells. The illustrated semiconductor memory device includes a row address buffer 11, a column address buffer 12, a row decoder 13 for decoding a row address, a column decoder 14 for decoding a column address, and a spare row decoder for decoding a row address of a defective cell. 15, a spare column decoder 16 for decoding a column address of a defective cell, and a memory array 17.

The memory cells in the memory array 17 can be replaced by spare memory cells (not shown) in units of rows (rows) or in units of columns (columns). The replacement with spare memory cells is performed by cutting fuses. Do.

FIG. 4A is an example of a circuit diagram showing the internal configuration of the spare row decoder and spare column decoder of FIG. In the decoder shown in FIG. 4A, a plurality of MOs which are turned on / off by the logic of each bit of the address signal are provided.
S transistors Q1 to Q4 are provided, and a fuse 21 is connected between the drain and source of each of the MOS transistors Q1 to Q4. These fuses 2
An arbitrary address value can be decoded by cutting some of the fuses 21 out of one.

For example, when a normal memory cell becomes defective, the fuse connected to the output terminal of the normal decoder shown in FIG. To decode the same address value as in (b), some fuses 21 in FIG. 4 (a) are cut. As a result, the defective memory cell is replaced with a spare memory cell.

[0008]

By the way, FIG. 4 (a)
In general, fuses are formed using polysilicon as a material.Because the fuse must be burned off by laser to cut the fuse, defective parts can only be replaced in the wafer state. Was. However, it is known that a relatively large number of defects occur even in the burn-in process after the package sealing. They had to be discarded as non-defective products, and it was not easy to improve the yield of memory chips.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of replacing a defective memory cell even after package sealing. It is in.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a spare memory cell which can be replaced with a part of a memory array and a part of the memory array which is used as the spare memory cell. A switching unit for switching whether or not to replace the memory array, wherein the switching unit has a nonvolatile storage unit for storing defective address information in the memory array detected after package sealing. Then, a defective portion in the memory array is replaced with the spare memory cell based on the defective address information stored in the storage unit.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the switching means includes a fuse capable of electrically cutting at least a part of a connection between the memory array and the spare memory cell. If a defect occurs in the memory array before package sealing, the defective portion in the memory array is replaced with the spare memory cell by cutting the fuse, and after the package sealing, If a defect occurs in the memory array, a defective portion in the memory array is replaced with the spare memory cell based on the defect address information stored in the storage unit.

According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the memory array includes m
The storage unit is configured by a plurality of memory cells of row × n columns (m and n are integers of 2 or more), and the storage unit stores the defective address information for each row and column of the memory array,
A defective portion in the memory array is replaced with the spare memory cell in a row unit or a column unit based on the defective address information stored in the storage unit.

According to a fourth aspect of the present invention, there is provided the semiconductor memory device according to any one of the first to third aspects, further comprising a replacement control circuit for performing control for replacing a defective portion in the memory array with the spare memory cell. A replacement control circuit configured to select whether to replace a defective portion in the memory array with the spare memory cell on a row basis or on a column basis with the spare memory cell; A second control cycle for replacing a defective portion in the array with the spare memory cell for each row or column of the memory array based on a result of selection by the first control cycle; A third control cycle for performing end control of a process of replacing a portion with the spare memory cell is continuously performed.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the replacement control circuit includes a RAS signal for controlling reading and writing to the memory array in the first control cycle. When the first address signal is input when the signal and the write enable signal have a predetermined logic, control is performed to replace a defective portion of the memory array with the spare memory cell on a row-by-row basis. When the second address signal is input when the signal, CAS signal, and write enable signal have the predetermined logic, control is performed to replace a defective portion of the memory array with the spare memory cell in column units. Do.

According to a sixth aspect of the present invention, in the semiconductor memory device according to the fourth or fifth aspect, the replacement control circuit is configured to control the RAS signal and the CA signal in the second control cycle.
The defective address information is stored in the storage unit using the third address signal input when the S signal and the write enable signal become the predetermined logic as a defective address.

According to a seventh aspect of the present invention, in the semiconductor memory device according to any one of the first to sixth aspects, the storage unit includes a U
PROM (Unerasable PROM).

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a semiconductor memory device according to the present invention, and shows an internal configuration of a DRAM. FIG.
Here, the same reference numerals are given to the same components as those in FIG. 3, and the following description will focus on the portions different from FIG.

The semiconductor memory device of FIG. 1 has, in addition to the configuration of FIG. 3, a spare row decoder (hereinafter, referred to as a spare row decoder for UPROM) 1 using an UPROM (Unerasable PROM),
A spare column decoder using a ROM (hereinafter, referred to as an UPROM spare column decoder) 2 and a replacement control circuit 3 are provided. Further, the semiconductor memory device of FIG. 1 is provided with an unillustrated UPROM that substitutes for a fuse. In FIG. 1, the spare row decoder 15 in FIG. 3 is referred to as a “preliminary polysilicon row decoder”, and the spare column decoder 16 is referred to as a “polysilicon spare column decoder”.

A spare memory cell (not shown) is provided in the memory array 17. If a failure occurs in some of the memory cells in the memory array 17, the spare memory cell is provided in units of rows (rows) or columns (columns). Replacement with a memory cell is performed.

To replace with a spare memory cell, 2
There are two methods. One is a method of replacing the fuse by cutting the fuse as in the conventional case, and the other is a method of storing a specific value in the UPROM and performing the replacement. The former is performed before package sealing, and the latter is performed after package sealing. The UPROM stores, for each row and each column in the memory array 17, information indicating whether or not there is a defect.

The UPROM spare row decoder 1 shown in FIG. 1 decodes a row address of a defective cell in the memory array 17. Similarly, the UPROM spare column decoder 2 decodes a column address of a defective cell in the memory array 17. The replacement control circuit 3 selects whether to replace a defective cell with a spare memory cell on a row (row) basis or on a column (column) basis. The replacement control circuit 3 also controls writing of defective address information to the UPROM.

FIG. 2 is an operation timing chart of a defect repair cycle in the semiconductor memory device of FIG. 1. The operation of FIG. 1 will be described based on this diagram.

If a defect occurs before the package is sealed, a fuse formed of polysilicon is cut off to remove a defective portion in the memory array 17 as in the conventional device shown in FIG. Replace with spare memory cells in row units or column units.

On the other hand, if a defect is found in the memory array 17 by a memory test device (not shown) after the package is sealed, a defect relief cycle shown in FIG. 2 is executed. The defect relief cycle is divided into a defect relief entry cycle shown at times T1 and T2 in FIG. 2, a defective address fetch cycle shown at times T2 and T3, and a defect relief end cycle shown at times T3 and T4.

First, from time T1 to T2, the CAS signal and the WE signal are set to low level, and then the RAS signal is set to low level. Thereby, the replacement control circuit 3
Starts the defect relief operation of the memory array 17.

More specifically, when the RAS signal goes low, the first address value (for example, $ 333)
When H) is input, the replacement control circuit 3 controls replacement with spare memory cells on a row (row) basis. On the other hand, when the second address value (for example, $ 355H) is input at the time when the RAS signal becomes low level, the replacement control circuit 3 controls the replacement with the spare memory cell in units of columns (columns). I do.

In the defective address fetch cycle at times T2 and T3, the CAS signal and W
After the E signal is set to the low level, the RAS signal is set to the low level. At this time, the defective address detected by the memory test device is input to the address terminal.

This address is decoded in the replacement control circuit 3, and information (for example, "1") indicating that a failure has occurred is stored in the corresponding storage area in the UPROM. More specifically, the UPROM has a storage area corresponding to each of the row address and the column address in the memory array 17, and the storage area corresponding to the row address or the column address of the defective portion has a failure. (For example, “1”) is stored.

The UPROM has a fuse 21 shown in FIG.
In the case where "1" is stored, a defective portion in the memory array 17 is replaced with a spare memory cell in units of rows (rows) or columns (columns).

In the defect repair end cycle between times T3 and T4, RAS is set after the CAS signal is set to the low level and the write enable signal WE is set to the high level.
The signal is set to low level. As a result, the replacement control circuit 3 ends the defect repair processing.

In a normal use state of the semiconductor memory device, when a defective address is input from the outside, the address is decoded by the spare row decoder 1 for UPROM and the spare column decoder 2 for UPROM, and instead of the defective memory cell, The spare memory cell is accessed.

As described above, according to the present invention, the semiconductor memory device is provided with the UPROM which performs the same operation as the fuse,
When a bit defect, a row defect, or a column defect occurs in the memory array 17, the defective address information is stored in the UPROM and the defective part is automatically replaced with a spare memory cell. In addition, defects in the memory array 17 can be relieved. Therefore,
Even if a defect occurs in the burn-in process after the package is sealed, it is not necessary to discard it as a defective product, and the yield of memory chips can be improved.

In the above-described embodiment, the description has been made by taking the example of the DRAM defect relief. However, the present invention is not limited to the SRAM or the EE.
It can be applied to all kinds of memory chips such as PROM.

In the above-described embodiment, an example in which the defective address information is stored in the UPROM only after the package is sealed is described. However, the defective address information is stored in the UPROM as a substitute for the fuse before the package is sealed. Is also good. This eliminates the need for a fuse and simplifies the memory configuration.

[0035]

As described above in detail, according to the present invention, a nonvolatile memory for storing defective address information in a memory array is provided in a semiconductor memory device, and the defective address information is stored in the memory. Is stored, the defective portion in the memory array is automatically replaced with a spare memory cell.
The defect of the memory array can be relieved, and the yield of memory chips can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is an operation timing chart of a defect relief cycle.

FIG. 3 is a block diagram showing an internal configuration of a conventional semiconductor memory device.

4A is a circuit diagram of a spare row decoder or a spare column decoder, and FIG. 4B is a circuit diagram of a row decoder or a column decoder.

[Explanation of symbols]

 Reference Signs List 1 spare row decoder for UPROM 2 spare column decoder for UPROM 3 replacement control circuit 11 row address buffer 12 column address buffer 13 row decoder 14 column decoder 15 spare row decoder 16 spare column decoder 17 memory array

Claims (7)

[Claims] 1. A semiconductor memory device comprising: a spare memory cell that can be replaced with a part of a memory array; and switching means for switching whether to replace a part of the memory array with the spare memory cell, The switching means has a non-volatile storage unit for storing defective address information in the memory array detected after package sealing, and based on the defective address information stored in the storage unit, the memory array A semiconductor memory device, wherein a defective portion in the inside is replaced with the spare memory cell. 2. The switching means includes a fuse capable of electrically cutting at least a part of a connection between the memory array and the spare memory cell, and a failure occurs in the memory array before package sealing. In this case, the defective portion in the memory array is replaced with the spare memory cell by cutting the fuse, and if a defect occurs in the memory array after package sealing, the defective portion is stored in the storage unit. 2. The method according to claim 1, wherein a defective portion in the memory array is replaced with the spare memory cell based on the defective address information.
3. The semiconductor memory device according to claim 1. 3. The memory array according to claim 1, wherein the memory array has m rows × n columns (m, n
The memory unit stores the defect address information for each row unit and column unit of the memory array, and the defect address stored in the storage unit. 3. The semiconductor memory device according to claim 1, wherein a defective portion in the memory array is replaced with the spare memory cell in a row unit or a column unit based on information. 4. A replacement control circuit for performing control to replace a defective portion in the memory array with the spare memory cell, wherein the replacement control circuit replaces the defective portion in the memory array with the spare memory cell on a row basis. A first control cycle for selecting whether to replace or replace the spare memory cell in a column unit; and determining a defective portion in the memory array specified in advance based on a selection result by the first control cycle. A second control cycle for replacing the spare memory cells with the spare memory cells for each row or column of the memory array, and a third control cycle for performing termination control of the process of replacing a defective portion in the memory array with the spare memory cells. The semiconductor memory device according to claim 1, wherein the operation is performed continuously. 5. The replacement control circuit according to claim 1, wherein in the first control cycle, when a RAS signal, a CAS signal, and a write enable signal for controlling reading and writing to the memory array become a predetermined logic, When one address signal is input, control is performed to replace a defective portion of the memory array with the spare memory cell on a row basis, and the RAS signal, CAS signal, and write enable signal become the predetermined logic. 5. The semiconductor memory device according to claim 4, wherein when a second address signal is input at the time, control is performed to replace a defective portion of the memory array with the spare memory cell on a column basis. 6. 6. The replacement control circuit according to claim 2, wherein in the second control cycle, the third address signal input when the RAS signal, the CAS signal, and the write enable signal become the predetermined logic is defective. As an address,
6. The semiconductor memory device according to claim 4, wherein said defective address information is stored in said storage unit. 7. The storage unit according to claim 5, wherein the storage unit is an UPROM (Unerasable PR).
OM). The semiconductor memory device according to claim 1, wherein