KR19990046868A - Thin Film Transistor Manufacturing Method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. Technical problem to be solved by the invention

It is an object of the present invention to provide a method for manufacturing a thin film transistor having a structure capable of reducing the turn-off current of the device and improving the characteristics of the leakage current in manufacturing the thin film transistor.

3. Summary of the Solution of the Invention

Forming a gate conductive layer pattern on the semiconductor substrate; A second step of forming a first gate insulating layer on the resultant of which the first step is completed; A third step of forming a second gate insulating film having a portion overlapping with an upper portion of the gate conductive film on the first gate insulating film; And a fourth step of forming a conductive film for channel formation along the entire surface of the resultant product in which the third step is completed.

4. Important uses of the invention

Used in thin film transistor process in semiconductor device manufacturing process.

Description

Thin Film Transistor Manufacturing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, such as a static random access memory (SRAM), and more particularly, to a method of manufacturing a thin film transistor (TFT) used as a pull-up device.

In general, an SRAM cell is composed of two transfer transistors, two pull-down N-channel (pull down) driver transistors, and two pull-up load elements. There are a number of problems with the manufacturing process. In order to reduce the area of the pull-up bulk transistor used as a pull-up device in SRAM by 40%, a high load resistor (HLR) type cell including a load resistor is used. However, when using a resistor as a pull-up device, it is difficult to store information.

In order to further improve information storage and area reduction, TFT-type cells in which a load element is composed of a P-channel thin film transistor have been widely used. The thin film transistor used as a pull-up load element in an SRAM circuit has a characteristic of performing a role as a pull-up element in an SRAM cell as the turn-on current is large and the turn-off current is small.

1A and 1B are cross-sectional views showing a portion of a thin film transistor of an SRAM cell according to the prior art, wherein reference numeral 11 denotes a polysilicon film for channel formation, reference numeral 12 denotes a gate oxide film, and reference numeral 13 denotes a gate. The polysilicon films for electrode formation are shown, respectively.

First, FIG. 1A is a cross-sectional view of a top gate type thin film transistor, and as shown in the drawing, a polysilicon film 11 for forming a channel on a lower layer where a predetermined process is completed and a gate oxide film 12 of a MOS transistor in order Laminated. A polysilicon film 13 for forming a gate electrode is formed thereon, and then patterned to form a gate electrode. As a result, the channel region is formed under the gate.

Next, FIG. 1B is a cross-sectional view illustrating a BOTTOM gate type thin film transistor, and as shown in the drawing, a polysilicon film 13 for forming a gate electrode is stacked, patterned, and then lowered thereon. The gate oxide film 12 is formed along the step of. A polysilicon film 11 for forming a channel is formed thereon to perform a mask process to form a thin film transistor having source and drain regions.

As described above, the conventional thin film transistor has one surface of the polysilicon film 13 for forming a gate electrode of a portion where the polysilicon film 13 for gate formation and the polysilicon film 11 for channel formation overlap. Since only the channel is present (see drawings), there is a limit to reducing the turn-off current proportional to the overlapping length of the polysilicon film 13 for forming the gate electrode and the polysilicon film 11 for forming the channel. have. Therefore, there is a problem in that the prior art cannot be applied to a high speed low voltage SRAM cell which needs to increase the stability of the cell by reducing the turn-off current of the thin film transistor.

In addition, there is a problem in that the drain leakage current must be removed due to the structure of the thin film transistor. In order to reduce the drain leakage current, the size of the thin film transistor itself is controlled, which causes a limitation in process capability and causes a problem in that the size of the cell itself is increased. Other drain leakage current solutions include increasing the gate oxide film thickness and decreasing the channel region thickness, but these all contribute to an increase in the turn-off current.

Therefore, as described above, in order to reduce the turn-off current and the leakage current of the thin film transistor, it is necessary to develop a thin film transistor having a new structure that is improved from the conventional method.

SUMMARY OF THE INVENTION The present invention devised to solve the above-described problems provides a method of manufacturing a thin film transistor having a structure capable of reducing the turn-off current of the device and improving the characteristics of the leakage current in manufacturing the thin film transistor. The purpose.

1A and 1B are cross-sectional views of a conventional thin film transistor fabrication process.

2A to 2E are cross-sectional views of a manufacturing process of a thin film transistor according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21: bottom layer comprising a silicon substrate

22: gate conductive film

23: first gate oxide film

24: second gate oxide film

25: polysilicon film for channel formation

26, 27: source and drain regions

In order to achieve the above object, a thin film transistor manufacturing method of the present invention, the first step of forming a gate conductive film pattern on the semiconductor substrate; A second step of forming a first gate insulating layer on the resultant of which the first step is completed; A third step of forming a second gate insulating film having a portion overlapping with an upper portion of the gate conductive film on the first gate insulating film; And a fourth step of forming a conductive film for channel formation along the entire surface of the resultant product in which the third step is completed.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2E are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a polysilicon film for a gate electrode is deposited on a lower layer 21 including a silicon substrate on which a predetermined process is completed, and then a patterning process using a gate electrode exposure mask (not shown) is performed. The gate conductive film 22 is formed.

Next, as shown in FIG. 2B, the first gate oxide film 23 and the second gate oxide film 24 are sequentially deposited on the entire structure. The second gate oxide film 24 is formed to be one to two times thicker than the first gate oxide film 23.

Next, as shown in Fig. 2C, after the photoresist is applied over the entire structure, a gate conductive film 22 is used by using a previously used exposure electrode for a gate electrode, using the opposite photoresist used at that time. A photoresist etch mask 201 is formed to expose the upper second gate oxide layer 24. In addition, only the second gate oxide layer 24 is etched by using the previously formed photoresist etching mask 201 to expose the first gate oxide layer 23 formed on the gate conductive layer 22.

Next, as shown in FIG. 2D, the polysilicon film 25 for channel formation is formed along the surface where the above-described process is completed.

Next, as shown in FIG. 2E, ion implantation is performed to form source and drain regions, and a channel region 25 is formed on the gate conductive layer 22, and a source region 26 connected thereto. ) And a drain region 27 are formed, and a drain offset region formed between the drain region 27 and the channel region 25 is formed.

The length of the channel region 25 is increased by the influence of the second gate oxide film 24 and the thickness of the gate oxide film between the gate conductive film 22 and the drain region 27 is increased by the above-described process. The drain induced drain leakage (GIDL) from the film is reduced.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention as described above, in manufacturing the thin film transistor, the gate oxide film of the thin film transistor is deposited in two steps, that is, after forming the gate conductive film pattern, the first gate oxide film and the second gate oxide film of the thin film transistor are deposited. The second gate oxide layer is etched, and only the width of the previously formed gate conductive layer pattern is etched, and a polysilicon layer for channel formation is formed along the step formed therein. In addition, the thickness of the oxide layer between the gate conductive layer and the drain may be increased to reduce the drain leakage current (GIDL) induced from the gate conductive layer. As a result, the channel length is increased by a predetermined step, thereby reducing the leakage current of the thin film transistor.

Claims (4)

Forming a gate conductive layer pattern on the semiconductor substrate; A second step of forming a first gate insulating layer on the resultant of which the first step is completed; A third step of forming a second gate insulating film having a portion overlapping with an upper portion of the gate conductive film on the first gate insulating film; And A fourth step of forming a conductive film for channel formation along the entire surface of the resultant product in which the third step is completed A thin film transistor manufacturing method comprising a. The method of claim 1, On the conductive film for channel formation A fifth step of forming a source and a drain by ion implantation using an ion implantation mask for the source and drain The thin film transistor manufacturing method further comprises. The method of claim 1, And forming the second gate insulating layer at least thicker than the first gate insulating layer. The method of claim 1, The third step is A thin film transistor manufacturing method using the photomask used in the first step.