KR19990038244U - Clock supply - Google Patents

Abstract

A clock supply apparatus is disclosed. This clock supply device receives the duplicated clock from the GPS, selects the main part and the inputted clock to switch to the intermediate supply, and alternates and monitors the clock.The selected clock is selected first as the master clock. A selection stage for selecting a later input clock as a slave clock, a comparison stage for comparing and grasping a clock with a predetermined frequency, and reporting the result to a controller, and controlling to determine whether to switch according to a clock comparison result at the comparison stage An intermediate supply comprising a stage, and a receiving stage for receiving the clock determined by the intermediate supply as a stable clock through the receiving RIVER.

Description

Clock supply

The present invention relates to a clock supply device, and in particular, when an error occurs in a system that duplicates a 2.048 MHz, 8 KHz, and 50 Hz used as a reference clock in a personal communication system (PCS) field, A stable clock supply device contributes to stabilization of a system.

Redundant switching of clocks can be switched in a number of ways, and in many cases it can be implemented with a lot of logic to determine when to monitor and switch clocks.

1 is a block diagram of a conventional clock supply apparatus. As shown, the conventional clock supply apparatus includes a clock input unit 1; A monitoring unit 2 for monitoring and monitoring an input clock; A state unit 3 for monitoring a state in the monitoring unit and detecting a state of a clock; It consists of a selection part 4 which outputs the clock of A side or B side according to the state of a state part. Therefore, if an error occurred after selecting the clock, it was not possible to switch the opacity so that the system could not provide a stable clock.

The present invention is invented to solve the problems of the prior art operating as described above,

It is an object of the present invention to provide a stable clock supply device that stabilizes a system by supplying a stabilized clock and immediately switching over when an error occurs.

Other objects and advantages of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

1 is a block diagram of a conventional clock supply apparatus.

2 is a block diagram of one embodiment of a clock supply apparatus of the present invention;

3 is a detailed block diagram of the central supply of FIG.

<Explanation of symbols for the main parts of the drawings>

1: input unit

2: monitoring unit

3: Status section

4: selection

11: main part

12: intermediate supply

13: final receiver

121: selection

122: comparison

123: control stage

Therefore, a preferred embodiment according to the present invention devised to achieve the object as described above,

The main unit for receiving the duplicated clock from the GPS input to the intermediate supply,

An intermediate supply that selects an input clock to switch and monitor the clock;

And a final receiving unit receiving the clock determined by the intermediate supply unit as a stable clock through the receiving RIVER.

In a preferred embodiment of the present invention, the intermediate supply unit,

A selection step of selecting the duplicated clock to select a first input clock as a master clock and a later input clock as a slave clock;

A comparison stage that compares and grasps a clock with a predetermined frequency and reports the result to a control stage; and

And a control stage for determining whether to switch according to a result of the clock comparison in the comparison stage. When an abnormality occurs in the master clock, the controller transitions to the slave clock.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the preferred embodiment of the present invention.

2 is a block diagram of a stable clock supply apparatus of the present invention. Figure 3 shows a detailed block diagram of the intermediate supply of Figure 2; As shown in FIG. 2, the stable clock supply device of the present invention includes a main unit 11 for inputting a redundant clock from a global positioning system (GPS) to an intermediate supply unit, and selects an input clock to switch clocks. And a receiving unit 13 that receives the monitored intermediate supply unit 12 and the clock determined from the intermediate supply unit as a stable clock through the receiving RIVER.

As shown in FIG. 3, the intermediate supply unit 12 selects the redundant clock to select a first input clock as a master clock and a later input clock as a slave clock. And the selection stage 121; A comparison unit 122 for comparing and grasping a clock with a predetermined frequency and reporting the result to the control unit 123; And a control stage 123 that determines whether to switch over based on a clock comparison result of the comparison stage 122.

Referring to the operation of the present invention is as follows.

First, the main unit 11 receives the duplicated clock from the GPS and supplies it to the intermediate supply unit 12. The select terminal 121 of the intermediate supply unit 12 selects the redundant clock. That is, the clock inputted first is selected as the master clock, and the clock inputted later is selected as the slave clock.

The clock comparator 122 monitors the master clock at 33 MHz. If an error occurs in the received master clock, it is switched to the slave clock. However, if an error occurs in the slave clock, it is not switched. The control stage 123 then reports the selected clock state to the processor. The control terminal 123 of FIG. 3 supplies a stable clock to the final receiver 13 through the reception RIVER.

The clock select terminal 121 of the intermediate supply unit 12 takes the input clock as the master clock. Through the above operation, if an error occurs in the master clock, switching to the slave clock is possible.

The comparison unit 122 determines 50Hz, 4.096MHz, and 8KHz, and determines whether to switch clocks in the control unit 123 accordingly. If an abnormality occurs in the slave clock, it is not switched, and the control unit 123 reports the selected state to the processor of the upper block as a clock monitoring result.

The present invention may be variously modified and may take various forms and the detailed description of the present invention has been described only with respect to specific embodiments thereof. It is to be understood, however, that the present invention is not limited to the particular form referred to in the detailed description of the invention, but rather includes all modifications, equivalents, and substitutes within the spirit and scope of the invention as defined by the appended claims. It should be understood to do.

The present invention operating as described above, due to the configuration of the present invention as described above, only a slight noise occurs during the actual switching of the clock and no problem occurs in the communication channel, so the reliability of the system by a stable clock supply To improve.

Claims (2)

In a mobile communication system in which a reference clock is duplicated, A main unit which receives a duplicated clock from the GPS and inputs it to an intermediate supply unit; An intermediate supply unit which selects an input clock to switch and monitor the clock; And A clock supply device comprising a final receiver for receiving a clock determined by the intermediate supply as a stable clock through a receiving RIVER The method of claim 1, wherein the intermediate supply unit, Selecting the redundant clock to select a first input clock as a master clock and a later input clock as a slave clock; A comparison stage that compares and grasps a clock with a predetermined frequency and reports the result to a control stage; and It includes a control stage for determining whether to switch in accordance with the clock comparison result in the comparison stage, The controller does not switch to the slave clock when an error occurs in the master clock and does not change when an error occurs in the slave clock.