KR19990027710A - Horizontal Deflection Circuit in Multi-Mode Monitors - Google Patents

Abstract

The present invention relates to a horizontal deflection circuit of a multi-mode monitor for varying the base current of a horizontal output transistor according to a video mode.

According to the present invention, when a predetermined S correction control signal is output through the S correction control signal output stages CS1, CS2, and CS3 of the microcomputer 50, which outputs different S correction control signals according to the video mode, the S correction is performed. The bias control transistors Q1, Q2, and Q3, whose collectors are connected to respective connection points of the bias resistors R21, R22, R23, and R24, which are connected in series to the base of the horizontal output transistor 40 in accordance with the control signal, By increasing / decreasing the base current i _B of the horizontal output transistor 40 by changing the overall bias resistance value as it is turned on and off, the horizontal output transistor 40 is prevented from being overheated and damaged when performing the switching operation. It is supposed to be.

Description

A horizontal deflection circuit in a multi-mode monitor

The present invention relates to a horizontal deflection circuit of a multi-mode monitor.

In general, a multi-mode monitor is a monitor that reproduces a predetermined image by automatically changing circuit constants inside the monitor according to the video card type (EGA, VGA, SVGA, XGA), that is, the video mode. It is divided by the frequency of the synchronization signal or the vertical synchronization signal, and when the video mode is changed, the horizontal / vertical synchronization circuit, the horizontal / vertical deflection circuit, the deflection correction circuit, etc. The circuit constant of is changed.

In particular, as shown in FIG. 1, when the horizontal drive signal H.drive whose frequency is changed according to the video mode is applied to the horizontal deflection circuit, the horizontal drive transistor 10 is turned on and off, and the horizontal drive transistor ( 10) is turned on and off to change the predetermined power supply (24V) applied to the primary winding of the horizontal drive transformer 20, the horizontal drive signal is amplified current through the secondary winding of the horizontal drive transformer 20 Is output. In addition, the voltage of the horizontal drive signal current amplified by the horizontal drive transformer 20 is dropped by the bias unit 30 is applied to the base of the horizontal output transistor 40, by the bias unit 30 When the voltage drop signal is applied to the base, the horizontal output transistor 40 is turned on / off so that a predetermined sawtooth wave deflection current flows through the horizontal deflection coil H.DY.

Here, the bias unit 30 is a voltage distribution resistor (R1) and the voltage distribution resistor (R1) connected between the secondary winding of the horizontal drive transformer 20 and the base of the horizontal output transistor (40). ) Is a bias resistor (R2) connected in parallel with the base current (i _B ) applied to the base of the horizontal output transistor 40 through the voltage distribution resistor (R1) and the bias resistor (R2) As shown in (a) of FIG. 2, the on / off operation of the horizontal output transistor 40 will be described in detail as follows.

When the horizontal output transistor 40 is turned on, the base current i _B of the horizontal output transistor 40 becomes a saturation current equal to Ib level, as shown in FIG. 2A, and the horizontal output transistor 40 When (40) is off, the base current (i _B ) of the horizontal output transistor (40) is the accumulation time required until the collector current value is lowered to 90% level in saturation when the horizontal output transistor (40) is turned on. When (Ts; storage time) has elapsed, it is lowered to a negative level, and then, when the falling time (Tf; falling time) required until the collector current value is lowered from 90% to 10% level elapses, the level becomes zero level.

However, when the horizontal output transistor 40 is switched on / off as described above, a heat loss is generated by the switching operation, which is the fall time when the horizontal output transistor 40 is turned off. As the Tf decreases, the fall time Tf decreases as the base current i _B saturates when the horizontal output transistor 40 is turned on, as shown in FIG. It changes according to the Ib level value. That is, even if the Ib level value in the predetermined video mode is predetermined as an optimal value for the frequency of the horizontal drive signal, the Ib level value increases when the video mode is changed and the frequency of the horizontal drive signal increases, thus the fall time Tf. If this becomes larger, the heat loss generated as the horizontal output transistor 40 performs the switching operation increases, which causes the horizontal output transistor 40 to be damaged.

Accordingly, in order to solve the above problem, the present invention changes the base current of the horizontal output transistor when the video mode is changed so that the horizontal output transistor is not damaged by the heat loss generated by the switching operation. It is an object of the present invention to provide a horizontal deflection circuit of a multi-mode monitor.

In order to achieve the above object, the present invention includes a horizontal drive transistor which is turned on / off when a horizontal drive signal (H.drive) whose frequency is changed according to a video mode is input; A horizontal driving transformer configured to amplify and output the horizontal driving signal through the secondary winding when the horizontal driving transistor is turned on / off to change a predetermined power applied to the primary winding; A bias unit for dropping the voltage of the horizontal drive signal amplified by the horizontal drive transformer to a predetermined bias voltage; When the signal output from the bias unit is applied to the base, the horizontal deflection of the multi-mode monitor characterized in that it comprises a horizontal output transistor which is turned on / off and a predetermined sawtooth deflection current flows in the horizontal deflection coil (H.DY) 10. A circuit, comprising: a voltage divider (R1) connected between the secondary winding of the horizontal drive transformer and the base of the horizontal output transistor; A first bias resistor R21 connected in parallel with the voltage distribution resistor R1; A second bias resistor R22 connected in series with the first bias resistor R21; A third bias resistor R23 connected in series with the second bias resistor R22; A fourth bias resistor R24 connected in series with the third bias resistor R23; When the S correction control signal output from CS1, the S correction control signal output terminal of the microcomputer, which outputs the S correction control signal for controlling the amount of current flowing in the horizontal deflection coil according to the video mode is applied to the base, the collector is turned on. A first bias transistor Q1 connected to the connection point of the bias resistor R23 and the fourth bias resistor R24; A second bias transistor, which is turned on when the S correction control signal output from CS2, the S correction control signal output terminal of the microcomputer, is applied to the base, and the collector is connected to the connection point of the second bias resistor R22 and the third bias resistor R23. Q2 and; A third bias transistor, which is turned on when an S correction control signal output from CS3, the S correction control signal output terminal of the microcomputer, is applied to the base, and a collector is connected to a connection point of the first bias resistor R21 and the second bias resistor R22. It is characterized by including the Q3.

The circuit according to the present invention configured as described above is connected in parallel with the voltage distribution resistor R1 connected to the base of the horizontal output transistor when the bias transistors Q1, Q2, and Q3 are turned on or off when the video mode is changed. The base current is controlled by the horizontal output transistor by varying the total resistance values of the bias resistors R21, R22, R23, and R24.

1 is a view showing a conventional horizontal deflection circuit,

2A is a waveform diagram of a base current of the horizontal output transistor shown in FIG. 1;

FIG. 2B is a graph showing the correlation between the base current and polling time shown in FIG.

3 illustrates a horizontal deflection circuit of a multi-mode monitor according to the present invention.

* Explanation of symbols for the main parts of the drawings *

10: horizontal drive transistor 20: horizontal drive transformer

30, 31: bias section 40: horizontal output transistor

50: Micom R1, R2, R21, R22, R23, R24: Resistance

Q1, Q2, Q3: transistor

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 illustrates a horizontal deflection circuit of a multi-mode monitor according to the present invention.

As shown in FIG. 3, an embodiment according to the present invention includes a horizontal drive transistor 10; Horizontal drive transformer 20; A bias portion 31; And a horizontal output transistor 40, and the bias unit 31 includes a voltage distribution resistor connected between the secondary winding of the horizontal driving transformer 20 and the base of the horizontal output transistor 40. R1); A first bias resistor (R21) connected in parallel with the voltage distribution resistor (R1); A second bias resistor R22 connected in series with the first bias resistor R21; A third bias resistor R23 connected in series with the second bias resistor R22; A fourth bias resistor R24 connected in series with the third bias resistor R23; When the S correction control signal outputted from CS1, the S correction control signal output terminal of the microcomputer 50 that outputs the S correction control signal for controlling the amount of current flowing in the horizontal deflection coil according to the video mode, is turned on, the collector is turned on. A first bias transistor Q1 connected to the connection point of the third bias resistor R23 and the fourth bias resistor R24; When the S correction control signal output from CS2, the S correction control signal output terminal of the microcomputer 50, is applied to the base, the collector is connected to the connection point of the second bias resistor R22 and the third bias resistor R23. A second bias transistor Q2; When the S correction control signal output from CS3, the S correction control signal output terminal of the microcomputer 50, is applied to the base, the collector is connected to the connection point of the first bias resistor R21 and the second bias resistor R22. The third bias transistor Q3 is provided.

The operation of the embodiment according to the present invention configured as described above is as follows.

First, in the embodiment according to the present invention, since the operation of the horizontal drive transistor 10, the horizontal drive transformer 20, and the horizontal output transistor 40 is the same as in the prior art, detailed description thereof will be omitted. The operation of the microcomputer 50 and the bias unit 31 will be described.

In the multi-mode monitor, the capacitance of the S correction capacitor, which is adjusted to prevent the screen from appearing in the circuit constant of the horizontal deflection circuit, is increased compared to the center portion according to the video mode, the capacitance of the S correction control signal of the microcomputer 50 is adjusted. It is changed by the S correction control signal output through the output stages CS1, CS2, CS3, and the S correction control signal output by the microcomputer 10 through the S correction control signal output stage to change the S correction capacitance is shown in the following table. As shown in Fig. 1, the frequency varies depending on the frequency of the horizontal synchronous signal whose frequency varies depending on the video mode.

Horizontal Sync Signal Frequency S correction control signal CS1 CS2 CS3 33 KHz LOW LOW LOW 34KHz to 46KHz HIGH LOW LOW 47KHz ~ 52KHz HIGH HIGH LOW 53KHz- HIGH HIGH HIGH

As shown in FIG. 3 and Table 1, the base current i _B applied to the base of the horizontal output transistor 40 through the voltage distribution resistor R1 is the frequency of the horizontal synchronization signal as the video mode is changed. Since the value increases as the value increases and decreases as the frequency of the horizontal synchronization signal decreases, the base current i _B increases to decrease the current level Ib when the base current i _B becomes saturated. As shown, in order to increase the bias current i _B1 flowing to the bias resistors R21, R22, R23, and R24, and to increase the current level Ib when the base current i _B becomes saturated, the bias current ( i _B1 ).

For example, when the frequency of the horizontal synchronization signal is a low frequency of 33 KHz or less, since the S correction control signals output through the S correction control signal output terminals CS1, CS2, and CS3 of the microcomputer 10 go low, the first bias transistor Q1. And both the second bias transistor Q2 and the third bias transistor Q3 are turned off. Accordingly, the bias resistance value for controlling the amount of the bias current i _B1 is the sum of the first bias resistor R21, the second bias resistor R22, the third bias resistor R23, and the fourth bias resistor R24 (R21 + R22 +). Since it becomes equal to R23 + R24, the bias resistance value reaches a maximum value, so that the bias current i _B1 flows to a minimum value, and conversely, the base current i _B flows to a maximum value.

However, when the video mode is changed and the frequency of the horizontal synchronization signal is 34 KHz to 46 KHz, the S correction control signals output through the S correction control signal output terminals CS1, CS2, and CS3 of the microcomputer 10 are HIGH, LOW, and LOW, respectively. Therefore, only the first bias transistor Q1 is turned on, and both the second bias transistor Q2 and the third bias transistor Q3 are turned off. Therefore, the bias resistance value for controlling the amount of bias current i _B1 becomes equal to the sum of the first bias resistor R21, the second bias resistor R22, and the third bias resistor R23 (R21 + R22 + R23). The bias resistance value is obtained by subtracting the value of the fourth bias resistor R24 from the maximum value, so that the bias current i _B1 increases and flows to a predetermined value relative to the minimum value. On the contrary, the base current i _B is a predetermined value compared to the maximum value. Decreases and flows.

Similarly, when the video mode is changed and the frequency of the horizontal synchronization signal is 47 KHz to 53 KHz, only the first bias transistor Q1 and the second bias transistor Q2 are turned on, the third bias transistor Q3 is turned off, and the amount of bias current i _B1 is decreased. The bias resistor value to be controlled is equal to the sum of the first bias resistor R21 and the second bias resistor R22 (R21 + R22), so the bias resistor value is obtained by subtracting the third bias resistor R23 and the fourth bias resistor R24 from the maximum value. As a result, the bias current i _B1 increases and flows to a predetermined value relative to the minimum value, and conversely, the base current i _B decreases and flows to a predetermined value relative to the maximum value.

Finally, when the video mode is changed and the frequency of the horizontal synchronization signal is higher than 54 KHz, the first bias transistor Q1, the second bias transistor Q2, and the third bias transistor Q3 are all turned on and the amount of the bias current i _B1 is increased. Since the bias resistance value for controlling is equal to the resistance value R21 of the first bias resistor R21, the bias resistance value is obtained by subtracting the values of the second bias resistor R22, the third bias resistor R23, and the fourth bias resistor R24 from the maximum value. The bias current i _B1 flows to the maximum value, while the base current i _B flows to the minimum value.

If the frequency of the horizontal synchronization signal is 31KHz, the horizontal output transistor 40 when the base current (i _B ) of the current level Ib is saturated to 0.8A, the horizontal output signal when the frequency of the 54KHz horizontal output When the current level Ib at which the base current i _B of the transistor 40 is saturated is 1A, an optimum current level designated to minimize heat loss generated by the switching of the horizontal output transistor 40 is performed. Ib is 0.8 A, and the resistance value (R21 + R22) obtained by adding up the resistance value of the voltage distribution resistor R1, the first bias resistor R21, the second bias resistor R22, the third bias resistor R23, and the fourth bias resistor R24. Assuming that + R23 + R24) is known, resistance values of the first bias resistor R21, the second bias resistor R22, the third bias resistor R23, and the fourth bias resistor R24 are designated as predetermined values, respectively, Bias Transistor Q1 A second bias transistor Q2, the third because the bias switching transistor Q3 in accordance with the written video mode may change the value of which was 1A current level Ib when the frequency of the horizontal synchronizing signal 54KHz to 0.8A. That is, as shown in the bias unit 31 of FIG. 3, assuming that the voltage at point a is V1 and the voltage at point b is V2, the amount of the base current i _B is proportional to the voltage of V2. Therefore, if the voltage of V2 is made 0.8 times the voltage of V1, the current level Ib, which is 1A when the frequency of the horizontal synchronization signal is 54KHz, can be changed to 0.8A.

A method of designating the resistance values of the first bias resistor R21, the second bias resistor R22, the third bias resistor R23, and the fourth bias resistor R24 to a predetermined value to make the voltage V2 0.8 times that of the voltage V1, respectively. For example, as follows.

First, since the voltage V2 is always a constant value, the voltage V2 can be obtained by the following equation.

Accordingly, when the resistance value of the first bias resistor R21 is obtained in order to obtain a voltage V2 that is 0.8 times the voltage of V1 by Equation 1, the resistance value of the voltage divider resistor R1 and the first bias resistor R21 Since the second bias resistor R22, the third bias resistor R23, and the fourth bias resistor R24 are added together, the resistance value (R21 + R22 + R23 + R24) is known, and the resistance value of the first bias resistor R21 is expressed by the following equation. Can be obtained by

After obtaining the resistance value of the first bias resistor R21 by Equation 2, the second bias resistor R22, the third bias resistor R23, and the fourth bias resistor are changed while changing the video mode from the higher frequency to the lower frequency of the horizontal synchronization signal. When the resistance values of R24 are sequentially obtained, the voltage V2 may be 0.8 times the voltage of V1, and the current level Ib, which is 1A when the frequency of the horizontal synchronization signal is 54KHz, may be changed to 0.8A.

As described above, when the video mode is changed according to the present invention, the bias transistors Q1, Q2, and Q3 are turned on or off and connected in parallel to the voltage distribution resistor R1 connected to the base of the horizontal output transistor. By controlling the base current of the horizontal output transistor by varying the overall resistance of the bias resistors R21, R22, R23, and R24, the horizontal output transistor has an effect of preventing the horizontal output transistor from overheating and being damaged. have.

Claims (1)

A horizontal drive transistor 10 which is turned on / off when a horizontal drive signal H.drive whose frequency is changed according to the video mode is input; A horizontal driving transformer 20 which amplifies and outputs the horizontal driving signal through the secondary winding when the horizontal driving transistor 10 is turned on / off to change a predetermined power applied to the primary winding; A bias unit 31 for dropping the voltage of the horizontal drive signal amplified by the horizontal drive transformer 20 to a predetermined bias voltage; When the signal output from the bias unit 31 is applied to the base is characterized in that it comprises a horizontal output transistor 40 to turn on / off and a predetermined sawtooth deflection current flows in the horizontal deflection coil (H.DY) In the horizontal deflection circuit of a multi-mode monitor, The bias unit 31, A voltage distribution resistor (R1) connected between the secondary winding of the horizontal drive transformer (20) and the base of the horizontal output transistor (40); A first bias resistor (R21) connected in parallel with the voltage distribution resistor (R1); A second bias resistor R22 connected in series with the first bias resistor R21; A third bias resistor R23 connected in series with the second bias resistor R22; A fourth bias resistor R24 connected in series with the third bias resistor R23; When the S correction control signal outputted from CS1, the S correction control signal output terminal of the microcomputer 50 that outputs the S correction control signal for controlling the amount of current flowing in the horizontal deflection coil according to the video mode, is turned on, the collector is turned on. A first bias transistor Q1 connected to the connection point of the third bias resistor R23 and the fourth bias resistor R24; When the S correction control signal output from CS2, the S correction control signal output terminal of the microcomputer 50, is applied to the base, the collector is connected to the connection point of the second bias resistor R22 and the third bias resistor R23. A second bias transistor Q2; When the S correction control signal output from CS3, the S correction control signal output terminal of the microcomputer 50, is applied to the base, the collector is connected to the connection point of the first bias resistor R21 and the second bias resistor R22. And a third bias transistor (Q3).