KR200150312Y1 - Display apparatus having cathode ray tube protection function - Google Patents

Abstract

The cathode ray tube (CRT) display device according to the present invention is characterized by the horizontal line appearing on the screen of the CRT 6 when the circuits related to horizontal deflection are normally operated but the vertical deflection circuit is damaged and no vertical deflection signal is generated. To prevent the fluorescent film from burning out and damaging the CRT, the collector voltage of the transistor Q1 in the grid voltage control circuit 20 is detected, and the vertical deflection signal is abnormal when the detected voltage is a voltage below a predetermined level. The CRT protection circuit 100 is provided to generate the power cutoff control signal to determine that the power supply circuit 9 of the CRT display device operates in the power cutoff mode.

Description

DISPLAY APPARATUS WITH CATHODE RAY TUBE PROTECTION FUNCTION

The present invention relates to a cathode ray tube (CRT) display device such as a monitor device or a television receiver, which is connected to a host such as a main unit of a personal computer system, a game device, an image device, or the like, and mainly displays image information. In particular, the present invention relates to a CRT display device having a function of preventing the CRT from being damaged due to abnormal operation of circuits related to vertical deflection.

1 schematically shows the circuit configuration of a monitor device for a computer system as a typical example of a CRT display monitor device.

Referring to FIG. 1, a CRT display monitor apparatus includes a video signal processing circuit 1, a horizontal / vertical synchronization signal processing circuit 2, a main control circuit 3, an on-screen display control circuit 4, and a video. The mixer circuit 5, the cathode ray tube 6, the adjustment panel 7, the video adjustment circuit 8, and the power supply circuit 9 are provided.

Currently, most monitor devices have an OSD function, which refers to displaying menus or adjustment functions in a small independent window, usually on the screen of the CRT 6.

In the monitor device having the above configuration, the main control circuit 3 receives the monitor driving information from the host, and the control signals necessary for processing the R (red), G (green), and B (bule) signals, and the horizontal Outputs control signals necessary for processing the vertical synchronization signals Hsync and Vsync, and a diaplay power management signaling (DPMS) control signal for performing a power saving function of the monitor apparatus.

The main control circuit 3 typically consists of a microcomputer or microprocessor.

The video signal processing circuit 1 amplifies each of the R, G, and B video signals input from the host by the control signal output from the main control circuit 3.

The video signals amplified by this circuit 1 are provided via the video mixer circuit 5 to the R, G and B electron guns of the CRT 6 respectively.

The horizontal / vertical sync signal processing circuit 2 converts the horizontal / vertical sync signals Hsync and Vsync input from the host to control signals input from the main control circuit 3 so as to have predetermined polarities, respectively. And horizontal and vertical deflection circuits (not shown) having the function of controlling the horizontal and vertical deflection of the electron beam irradiated from the electron guns using them.

The main control circuit 3 provides the OSD output data to the OSD control circuit 4 in response to the input of the adjustment keys provided in the front control panel 7, whereby the OSD control circuit 4 is configured to display the OSD R, The G and B video signals are output to the video mixer circuit 5.

The video mixer circuit 5 mixes the outputs of the video signal processing circuit 1 with the outputs of the OSD control circuit 4 and provides them to the CRT 6.

The image adjustment circuit 8 according to the information output by the main control circuit 3 in response to the user pressing the buttons of the front control panel 7, the contrast, the brightness, the vertical / horizontal size of the image, the horizontal / vertical Position, vertical linearity, horizontal / vertical focus, degauss, video cutoff, video gain, tilt, parallelism (parallelogrem), trapezoidal distortion ( trapezoid).

Although not shown in the figure, it is well known that most monitor devices have audio amplification circuits that receive amplified sound signals from a host and output them to a speaker.

The power supply circuit 9 of most modern monitor devices operates in the DPMS manner established by the Video Electronics Standard Association (VESA).

As is well known, the DPMS scheme is divided into a normal mode, a standby mode, a suspend mode, and a power-off mode.

When no video signals are input from the host, the power supply circuit 9 enters the standby mode, and when the vertical synchronization signal Vsync is not input, the power supply circuit 9 enters the pause mode, and the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync. The power down mode is entered when none is input.

In addition, power consumption is specified for each mode.

As is well known, the power supply circuit 9 generally includes a fullwave rectifier unit for converting alternating current (AC) into direct current (DS), a pulse width modulation (PWM) control unit, Multiple secondary windings transformer, a voltage output for rectifying the voltages respectively derived from the secondary windings or coils of the transformer and outputting a plurality of regulated voltages And a feedback control unit for controlling the feedback of the pulse width modulation unit, and a DPMS control unit for controlling power saving according to a predetermined DPMS control signal provided from the main control circuit 3. .

FIG. 2 schematically shows the configuration of a vertical deflection circuit which is one component of the horizontal / vertical synchronization signal processing circuit 2, and the waveforms of the vertical deflection voltage Vout and the current are schematically shown in FIGS. 3A and B, respectively. Is shown.

Referring to FIG. 2, the vertical deflection circuit includes a vertical oscillation unit 10 generating a vertical deflection signal by oscillation, a vertical amplification unit or a vertical driver 12 amplifying the deflection signal, and a vertical deflection yoke 18. The vertical pull-out part 14 which supplies a current signal (refer FIG. 3B), and the waveform correction part 16 which corrects the distortion of a sawtooth wave signal are provided.

When a vertical deflection signal Vout having a waveform as shown in FIG. 3A is generated from the vertical deflection circuit, a vertical deflection current having a waveform as shown in FIG. 3B flows to the vertical deflection yoke 18 by this signal. .

One period of the vertical deflection signal is, as is well known, composed of the scanning section Ts and the retrace section Tr (see FIG. 3). During the scanning section Ts, the deflection of the electron beams from the top to the bottom of the CRT screen is changed. During the retrace period Tr, the electron beams are moved from the bottom to the top of the CRT screen for the next deflection.

The retrace period Tr is shorter than the scan period Ts, and during this period Tr, the beams do not need to be displayed on the CRT screen because the electron beams are moved to the top of the CRT for the next deflection.

The circuit for this is the grid voltage control circuit 20 shown in FIG. 2.

This circuit 20 supplies a predetermined negative voltage (e.g.-30 V) to the grid G1 of the CRT during the retrace period so that electron beams are not transferred from the electron guns to the fluorescent film of the CRT.

However, in the conventional CRT display monitor device, if the horizontal deflection circuit is normal but the vertical deflection circuit is damaged, no vertical deflection signal is generated, and the horizontal deflection of the electron beams is normal, but the vertical deflection is not performed. A horizontal line will appear at.

If this condition persists for a long time, the fluorescent film in the area where the transverse line has appeared burns out and the CRT becomes unusable.

The present invention has been made to solve such a conventional problem, and an object thereof is to prevent burnout of a CRT due to abnormal operation of a circuit related to vertical deflection in a CRT display device.

1 is a block diagram schematically showing the configuration of a circuit of a cathode ray tube display monitor device.

2 is a block diagram schematically showing the configuration of a vertical deflection circuit of a cathode ray tube display monitor device according to the prior art.

3 is a schematic waveform diagram of vertically polarized voltage and current.

4 is a circuit diagram showing a cathode ray tube protection circuit according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

6 cathode ray tube 10 vertical oscillation part

12: vertical amplifier 14: vertical output

16 waveform correction unit 18 vertical yoke

20: grid voltage control unit 100: cathode ray tube protection circuit

According to a feature of the present invention for achieving the above object, it has an electron guns for irradiating electron beams, a fluorescent film, and at least one control grid for selectively transferring the electron beams from the electron guns to the fluorescent film A CRT display device having a CRT includes: receiving a vertical deflection signal and supplying a predetermined first control voltage to the control grid during a vertical scanning period of the vertical deflection signal to allow the electron beams to be delivered to the fluorescent film; Grid voltage control means for supplying a predetermined second control voltage during the vertical retrace period of the vertical deflection signal to block transmission of the electron beams to the fluorescent film; CRT protection means for detecting whether the vertical deflection signal has a normal waveform and outputting a power off control signal when the vertical deflection signal does not have a normal waveform; The power supply circuit may be configured to operate in a power shutdown mode to cut off power supply to a display device in response to the power shutdown control signal.

In the CRT display device, The grid voltage control means; Section detecting means for detecting the scanning section and the retrace section; Resistance means connected to the first power supply voltage; A first terminal connected to said resistance means, a second terminal connected to a second power supply voltage, and a control terminal connected to said detecting means, and being OFF when said interval detecting means detects said scanning interval; And switching means for turning on when the detection means detects the retrace section.

In the apparatus, the CRT protection means; Voltage detection means for detecting a voltage of the first terminal of the switching means; And a power control means for generating the power cutoff control signal by determining that the vertical deflection signal is abnormally generated when the voltage detection means detects a voltage below a predetermined level.

In the apparatus, the voltage detecting means; A first capacitor having one terminal connected to the first terminal of the switching means; A zener diode having a cathode connected to the other terminal of the first capacitor; And a second capacitor having one terminal connected to the anode of the zener diode and the other terminal connected to the second power supply voltage.

In the apparatus, the power control means; First resistance means connected to one terminal of the zener diode by the anode; Second resistance means having one terminal connected to said anode of said zener diode; Third resistor means for connecting one terminal to the third power supply voltage; A node for outputting the power cutoff control signal; Fourth resistance means connected between the node and the second power supply voltage; A first terminal connected to the other terminal of the third resistance means, a second terminal connected to the node, and a control terminal connected to the first resistance means, wherein the voltage of the anode of the zener diode is Another switching means is turned on when the voltage is below the level and turned off when the voltage is above the predetermined level.

EXAMPLE

Next, a preferred embodiment of a CRT display device having a CRT protection circuit according to the present invention will be described in detail with reference to FIG. 4.

The novel CRT display device of the present invention protects the CRT by preventing the transverse line from appearing in the fluorescent film of the CRT by causing the CRT display device to operate in a power cut mode when a vertical deflection signal is not generated due to any cause.

Referring to FIG. 4, a CRT display device according to the present invention includes a grid voltage control circuit 20 connected to an output 14 of a vertical deflection circuit, and a circuit voltage between the circuit 20 and a power supply circuit 9. The CRT protection circuit 100 is provided.

The power supply circuit 9 supplies the power of the CRT display.

The grid voltage control circuit 20 includes a zener diode ZD1, resistors R1 to R6, NPN transistor Q1, diodes D1 and D2, capacitors C1 to C4, and a variable resistor ( VR1), and the CRT protection circuit 100 includes capacitors C5 and C6, a zener diode ZD2, resistors R7 to R10, and a PNP transistor Q2.

The specific configuration thereof is as follows.

First, in the grid voltage control circuit 20, the cathode of the zener diode ZD1 is connected to the vertical deflection signal Vout output from the output 14 of the vertical deflection circuit.

One terminal of the resistor R1 and one terminal of the capacitor 1 are commonly connected to an anode of the zener diode ZD1.

One terminal of the capacitor C2 and one terminal of the resistor R2 and the base of the MPN transistor Q1 are commonly connected to the other terminal of the resistor R1.

One terminal of the resistor R3 is connected to the collector of the transistor Q1, and the other terminal of the resistor R3 is connected to the power supply voltage V _CC 1.

The other power supply voltage, the ground voltage GND, is connected to another terminal of the capacitor C1, another terminal of the capacitor C2, another terminal of the resistor R2, and an emitter of the transistor Q1, respectively.

The cathode of diode D1 is connected to the collector of transistor Q1, and its anode is connected to ground voltage GND.

One terminal of the capacitor C3 is also connected to the collector of the transistor Q1, the other terminal thereof is connected to the grid G1 of the CRT 6D, and the variable resistor VR1 is variable through the resistor R4. Connected to the terminal.

A resistor R5 is connected between one terminal of the variable resistor VR1 and the ground voltage GND, and a resistor R6 and a capacitor C4 are connected between the other terminal of the variable resistor VR1 and the ground voltage GND. ) Are connected in series.

An anode of the diode D2 is connected to the connection node of the resistor R6 and the capacitor C4, and the cathode of the diode D2 is connected to a negative power supply voltage (-V _BB ).

The resistors R4 to R6, the variable resistor VR1, the capacitor C4, the diode D2, and the power supply voltage −V _BB are those for varying the voltage range of the node N2.

Next, in the CRT protection circuit 100, one terminal of the capacitor C5 is connected to the collector of the transistor Q1, that is, the node N1, and the other terminal thereof is connected to the cathode of the zener diode ZD2. . One terminal of each of the capacitor C6 and the resistors R7 and R10 is connected to the anode of the zener diode ZD2.

The other terminal of the resistor R7 is connected to the base of the PNP transistor Q2, and its emitter and collector are connected to the resistors R8 and R9, respectively.

The other terminal of the resistor R8 is connected to another power supply voltage V _CC 2, and the other terminal of each of the capacitor C6 and the resistor R9 and the resistor R10 is connected to the ground voltage GND. )

The collector of the transistor Q2 and the connection node N3 of the resistor R9 are connected to a DPMS controller (not shown) in the power supply circuit 9.

In the CRT display device according to the present invention having the above configuration, the zener diode ZD1, the capacitors C1 and C2, and the resistors R1 and R2 detect the scan section Ts and the retrace section Tr. Acts as a section detection section.

The transistor Q1 acts as a switch that is turned off when the section detection units ZD1, C1, C2, R1, and R2 detect the scan section, and is turned on when the retrace section is detected.

As shown in Fig. 3A, the vertical deflection signal Vout is maintained at a higher voltage in the retrace period Tr than in the scan period Ts.

The vertical deflection signal voltage in the scan period Ts is not detected by the zener diode ZD1, but the voltage in the retrace period Tr is detected by the zener diode ZD1. Since the vertical deflection signal voltage is not detected by the zener diode ZD1 during the scan period Ts, the base of the transistor Q1 is in an open state, so that the transistor Q1 is turned off.

Therefore, at this time, the voltage of the node N1 is at a high level, that is, Vcc1-I × R3 (where I is a current flowing through R3). On the other hand, during the retrace period, the vertical deflection signal voltage is detected by the zener diode ZD1, and the detected voltage is applied to the base of the transistor Q1. As a result, the transistor Q1 is turned on.

Therefore, the voltage at the node N1 is at a low level, that is, the ground voltage GND.

As a result, when the vertical deflection signal Vout of the waveform as shown in FIG. 3A is continuously supplied to the grid voltage controller 20, the voltage of the node N1 alternately becomes high level and low level.

On the other hand, as is well known, the grid G1 is for controlling the amount of electrons generated from the electron gun.

The variable range of grid G1 voltage typically ranges from -30V to 0V.

When the voltage of the grid G1 becomes maximum within the variable range, the amount of electrons generated by the electron gun is maximum, and when it is minimum, the amount of electrons is minimum.

As such, the amount of electrons emitted from the electron guns is adjusted by adjusting the variable range of the grid G1 voltage.

The regulation of the grid G1 voltage is used for two purposes. The first is to adjust the brightness of the screen. The brightness of the screen is adjusted by adjusting the resistance of the variable resistor VR1. When the resistance value of the variable resistor VR1 is adjusted, the range in which the voltage of the grid G1 is variable is adjusted.

That is, the variable range of the grid G1 voltage is made high or low as a whole. When the maximum value of the grid G1 voltage is set high, the screen becomes bright, and when set low, the screen becomes dark. Second, in the scanning period Ts, the grid G1 voltage becomes the maximum within the variable range so that the electron beam is normally output from the electron gun. In the retrace period Tr, the grid G1 voltage is minimum so that the electron beam is not output. It is.

Subsequently, as described above, in order to adjust the amount of electrons emitted from the electron guns of the CRT 6, the voltage of the grid G1 is varied, and typically the voltage of the grid G1 is -30 to 0V. It is variable within the range of.

That is, in the scanning period Ts, the voltage of the node N2 is maintained at almost 0 V, and the normal electron beam is scanned. During the retrace period Tr, the voltage of the node N2 becomes almost -30 V, so that the CRT 6 The electron beams do not appear on the screen.

This operation is described as follows.

As is well known, a capacitor has the property that no direct current component is transferred to its next stage but alternating current component. The capacitor C3 serves to transfer the alternating voltage of the node N1 to the node N2. That is, during the scan period Ts, the node N1 maintains a high level voltage (V _CC 1-I × R3 and V _CC = 30V). Node N2 maintains a voltage of approximately 0V. Then, when the retrace period Tr is reached, the voltage of the node N1 is changed to the ground voltage GND, and accordingly, the voltage level of the node N2 is reduced to almost -30 by the voltage drop as much as the change amount of the node N1. do. When the voltage is changed back to the scan period Ts, the node N1 is changed back to a high level voltage, and thus the node N2 voltage is also changed to almost 0V. This process is repeated continuously when the vertical deflection signal Vout is normally output.

As described above, when the vertical deflection circuit operates normally, the node N1 repeatedly has a high level voltage and a low level voltage. At this time, the capacitors C5 and C6 and the zener diode ZD2 in the CRT protection circuit 100 serve as a voltage detector for detecting the collector voltage of the node N1, that is, the transistor Q1.

On the other hand, the resistors R7 to R10 and the PNP transistor Q2 in the CRT protection circuit 100 determine whether the vertical deflection signal is abnormally generated by the output voltages of the voltage detectors C5, C6, and ZD2. And acts as a power control section for providing a power off control signal for the DPMS of the power supply circuit 9 to a DPMS controller (not shown) in accordance with the determination. The operation principle of the CRT protection circuit 100 will be described in detail as follows.

First, when the vertical deflection circuit of the CRT display device operates normally, that is, when the vertical deflection signal Vout of the normal waveform as shown in FIG. 3A is output from the vertical output unit 14, The voltage goes high during the scan period Ts of the vertical deflection signal and low during the retrace period Tr. The high level voltage during the scan period Ts charges the capacitor C6. During the retrace period Tr, the voltage of the capacitor C6 is slightly discharged through the resistor R10, but the voltage of the capacitor C6 is maintained above the ground voltage GND. The voltage of the capacitor C6 is applied to the base of the PNP transistor Q2 through the resistor R6. Thus, the transistor Q2 is non-conducting.

In this way, when the vertical deflection signal is normally generated, the transistor Q2 is turned off, so that the node N3 and the DPMS controller (not shown) of the power supply circuit 9 are electrically opened. As a result, the CRT 6 is normally powered from the power supply circuit 9.

Next, when the vertical synchronization signal is not provided from the host to the CRT display device, or when the vertical deflection signal is not generated due to a malfunction of the synchronization signal processor integrated circuit of the CRT or a failure of the vertical deflection integrated circuit, the node N1 may be disconnected. The voltage will continue to be at a high level. In other words, the DC voltage is supplied to the node N1. Therefore, the voltage of the node N1 is not transferred to the capacitor C6 by the capacitor C5. At this time, the voltage charged in the capacitor C6 is discharged through the resistor R10, and the ground voltage is applied to the base of the transistor Q2.

As such, when the circuit related to the vertical deflection operates normally but is abnormally operated by an external factor, the resistor R10 quickly discharges the voltage charged in the capacitor C6 so that the power supply circuit 9 quickly enters the power disconnect mode. do. In this way, the transistor Q2 is turned on so that the high level voltage of the node N3 is provided to the DPMS controller of the power supply circuit 9 as a power off control signal. Therefore, the power supply circuit 9 operates in the power interruption mode so that the overall power supply of the CRT 6 and the display device is interrupted. As a result, no raster is generated on the screen of the CRT 6 and the CRT is protected.

Although the present invention has been described using a monitor device for a computer system as an example, it will be understood that the present invention can be applied to any display device using a CRT.

As described above, according to the present invention, the horizontal deflection circuit is normal, but when the vertical deflection circuit is damaged and no vertical deflection signal is generated, the horizontal film appearing on the screen of the CRT causes the fluorescent film of the CRT to burn out, thereby damaging the CRT. Can be prevented.

Claims (6)

CRT display having a CRT 6 having electron guns for irradiating electron beams, a fluorescent film and at least one control grid G1 for selectively transferring the electron beams from the electron guns to the fluorescent film Receive a vertical deflection signal Vout and supply a predetermined first control voltage to the control grid G1 during the vertical scan period Ts of the vertical deflection signal to cause the electron beams to be delivered to the fluorescent film. And grid voltage control means for supplying a predetermined second control voltage during the vertical retrace period Tr of the vertical deflection signal to block transmission of the electron beams to the fluorescent film; CRT protection means for detecting whether the vertical deflection signal Vout has a normal waveform and outputting a power off control signal when the vertical deflection signal does not have a normal waveform; And a power supply circuit (9) for operating in a power off mode for interrupting power supply to a display device in response to the power off control signal. The method of claim 1, wherein the grid voltage control means; Section detecting means for detecting the scan section, the scan section, and the retrace section; A resistance means connected to a first power supply voltage V _CC 1, a first terminal connected to the resistance means, a second terminal connected to a second power supply voltage GND, and a control terminal connected to the detection means. And switching means which is turned off when said section detection means detects said scanning section and turns on when said detection means detects said retrace section. The method of claim 2, wherein the CRT protection means; Voltage detection means for detecting a voltage of the first terminal of the switching means; And power control means for generating the power cutoff control signal by judging that the vertical deflection signal is abnormally generated when the voltage detection means detects a voltage below a predetermined level. 4. The apparatus of claim 3, wherein the voltage detecting means comprises: A first capacitor (C5) having one terminal connected to the first terminal of the switching means; A zener diode (ZD2) having a cathode connected to the other terminal of the first capacitor; And a second capacitor (C6) having one terminal connected to an anode of the zener diode and the other terminal connected to the second power supply voltage. 5. The apparatus of claim 4, wherein the power control means; First resistance means (R7) having one terminal connected to the anode of the zener diode; A terminal connected to the anode of the zener diode (R10); Third resistance means (R8) having one terminal connected to the third power supply voltage (V _CC 2); A node for outputting the power cutoff control signal; Fourth resistance means (R9) connected between said node and said second power supply voltage; A first terminal connected to the other terminal of the third resistance means, a second terminal connected to the node, and a control terminal connected to the first resistance means, the anode of the zener diode ZD2 And another switching means (Q2) which is turned on when the voltage is below the predetermined level and turned off when the voltage is above the predetermined level. 6. The PNP of claim 5, wherein the other switching means has an emitter connected to the other terminal of the third resistance means, a collector connected to the node, and a base connected to the first resistance means. A CRT display device comprising a transistor.