KR100285934B1 - Spot killer circuit of a video display appliance - Google Patents

Abstract

PURPOSE: A spot killer circuit of a video display device is provided to detect a mode variation or transient effect in the video display device to reduce a control grid voltage of a CRT, thereby removing spots on a screen. CONSTITUTION: A spot killer circuit of a video display device includes a transistor(Q1) that is connected to a DPM terminal of a microcomputer(2) and switched according to a spot control signal output from the DPM terminal, and a transistor(Q2) that is connected to a mute terminal of the microcomputer and an unlock terminal of a deflection driving IC(3) and switched according to spot control signals inputted from the microcomputer or deflection driving IC. The spot killer circuit further includes a transistor(Q3) that is connected to a common connection node(C) of the two transistors and operates according to the outputs of the transistors to output a switching control signal, and a spot removal unit(5) for controlling the voltage of the first grid terminal(G1) of a CRT(1) according to the switching control signal to remove spotting phenomenon of the CRT.

Description

Spot killer circuit of video display equipment {SPOT KILLER CIRCUIT OF A VIDEO DISPLAY APPLIANCE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spot killer circuit of a video display device. In particular, a spot killer of a video display device that removes a spot phenomenon by detecting a mode change or a transient phenomenon of the video display device and controlling the control grid voltage of the SALTI. It is about a circuit.

In general, a video display device is directly connected to a first grid terminal of a CRT (CRT = Cathod ray tude) such as a CRT at a secondary side end of a flyback transformer. A spot, a phenomenon in which the scanning beam emitted from the electron gun is concentrated, is generated. At this time, if the spot phenomenon persists, the phosphor applied on the screen of the cialty is burned, thereby shortening the lifetime of the cialty. Therefore, SALTI is usually used to install a separate spot killer circuit for removing the spot phenomenon as described above.

1 is a circuit diagram of a conventional spot killer circuit as described above. Referring to FIG. 1, a conventional spot killer circuit includes a video signal amplifier 70 for amplifying an input video signal and a screen for displaying a screen according to the video signal input from the video signal amplifier 70. 71 and a spot control unit 71 for controlling the operation of the video signal amplifying unit 70 to eliminate spot phenomenon of the CALTI 71.

The video signal amplifier 70 is configured to output transistors Q1 and Q2 to amplify the input video signal and to output the video signals amplified by the transistors Q1 and Q2 to the CLT 71. The transistor Q3 amplifies to a level, and the transistor Q4 controls the operations of the transistors Q1 and Q2.

Here, diodes D1 and D2 are connected in series between the collector of transistor Q1 and the base of transistor Q3, and the resistor R1 between the emitter of transistor Q3 and the collector of transistor Q4. R2 is connected in series, and resistors R3 and R4 are connected in parallel between the emitter of the transistor Q2 and ground. In addition, the emitter of the transistor Q3 is connected to the cathode of the SALTY 71 via the resistor R5, the output terminal of the spot remover 72 is connected to the base of the transistor Q4, The emitter of transistor Q4 is connected to the collector of transistor Q1.

On the other hand, the operation of the conventional spot killer circuit as described above is as follows.

First, when an image signal is input to the base terminal of the transistors Q1 and Q2 from the image signal processing unit (not shown) of the CALTI 71, the transistors Q1 and Q2 convert the input image signal into a set amplification factor. Is amplified and output to the transistor Q3. The transistor Q3 amplifies the video signals inputted from the transistors Q1 and Q2 to a predetermined output level and outputs them to the SALTI 71 through the resistor R5.

At this time, the spot removing unit 72 detects whether the horizontal and vertical synchronization signals are normally input, and applies the spot control signal to the base of the transistor Q4.

For example, when the horizontal and vertical synchronization signals are normally input, the spot removing unit 72 applies a 'high' signal to the base of the transistor Q4 of the image signal amplifier 70. As the transistor Q4 is turned on, the transistor Q3 continuously outputs an image signal to the cathode of the seed tee 71, and accordingly the seed tee 71 displays an image on the screen.

However, if the automatic power saving mode is executed in the image display device and none of the horizontal and vertical synchronizing signals are input to the spot removing unit 72 or both are not input, the spot removing unit 72 is the transistor Q4. The low signal is applied to the base. Thus, this transistor Q4 is turned off, and accordingly the transistor Q3 is also turned off. Therefore, since the video signal applied to the cathode of the CALTI 71 is blocked, the spot phenomenon does not appear on the screen of the CALTI 71.

However, the spot killer circuit of the conventional video display device cuts the signal voltage of the video signal applied to the cathode of the CALTI 71 to remove the spot phenomenon, and the voltage applied to the cathode is adjusted. Since the range is very limited, there is a disadvantage that the spot phenomenon cannot be completely removed. In addition, since the spot killer circuit is directly connected to the cathode of the CALTI 71, there is a problem that noise is introduced through the cathode.

An object of the present invention is to solve the above-mentioned problems, the spot of the video display device is to remove the screen spot phenomenon by reducing the control grid voltage of the CRT by detecting the mode change or transient phenomenon of the video display device It is to provide a killer circuit.

Another object of the present invention is to provide a spot killer circuit of a video display device that can minimize the error rate of the spot killer circuit by controlling the control grid voltage of the CRT by the horizontal unlock terminal of the horizontal deflection IC before the mute stage of the microcomputer. To provide.

In order to achieve the above object, the spot killer circuit of the video display device according to the present invention determines the abnormal state of the video display device and generates a spot control signal through the mute terminal and the DM terminal, A deflection driver IC which operates according to an operation control signal and generates a spot control signal through an unlock terminal in the event of an abnormal state of the video display device, and at least one of an unlock terminal of the bias drive IC, a mute terminal and a DM terminal of a microcomputer. A spot switching unit for generating a switching signal when a spot control signal is input from the terminal and a spot agent for removing spot phenomena of the spot by controlling the voltage of the first grid terminal of the STI according to the switching control signal of the spot switching unit. Consists of denial.

1 is a conventional spot killer circuit

2 is a spot killer circuit of the present invention.

(A)-(e) is a waveform diagram of each part of the circuit of FIG.

<Explanation of symbols for main parts of drawing>

1: CALTI

2: Micom

3: deflection drive IC

4: Spot elimination switching unit

5: Spot removal circuit part

6: power circuit

7: Grid level adjustment circuit

D1-D5: Diode

Q1-Q4: Transistor

R1-R6: resistance

C1, C2: Capacitor

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the spot killer circuit of the image display device according to the present invention includes the CALTI 1 for displaying an image signal, and the operation of the image display device including the operation of the SALTI 1. In general, the microcomputer 2 generates spot control signals through the mute terminal and the display power management (DPM) terminal, and determines the abnormal state. A deflection driving IC (3) for driving a deflection coil (not shown) to deflect the emitted electron beam and generating a spot control signal through an UNLOCK terminal in case of an abnormal state of an image display device; A spot switching unit 4 for generating a switching control signal when a spot control signal is input from at least one of an unlock terminal of the deflection driving IC 3 and a mute terminal and a DM terminal of the microcomputer 2; Spots The spot removing unit 5 adjusts the voltage of the first grid terminal G1 of the STI 1 according to the switching control signal of the switching unit 4 to eliminate spot phenomenon of the STI 1.

The spot switching unit 4 is connected to the DM terminal of the microcomputer 2 and is switched according to the spot control signal output from the DM terminal, and is operated by the transistor Q1 and the mute terminal of the microcomputer 2. A transistor Q2 connected to the unlock terminal of the deflection driving IC 3 via diodes D1 and D2, respectively, and switched according to a spot control signal input from the microcomputer 2 or the deflection driving IC 3; And a transistor Q3 connected to the common connection point C of the transistors Q1 and Q2 and operated according to the outputs of the transistors Q1 and Q2 to output a switching control signal.

Here, the diode D3 is connected to the collector terminal of the transistor Q1 in the reverse direction, and the base of the transistor Q3 is connected to the anode of the diode D3 via the resistor R1. A power unit 6 for controlling the operating power supply of the circuit in the power saving mode is connected to the collector of Q1. A bias voltage VCC1 is connected to a base of the transistor Q3 via a resistor R1 and a reverse diode D4, and a bias voltage VCC1 is connected to an emitter of the transistor Q3 with a forward diode D5) is connected via a resistor R2, and a capacitor C1 is connected to the collector of this transistor Q3. In addition, a bias voltage VCC2 is connected to the collector of the transistor Q1 via a resistor R3.

In addition, the spot removing unit 5 is connected to the collector terminal of the transistor Q3 via a resistor R4, and according to the spot switching signal input from the transistor Q3, the first grid of the SALTI 1 is connected. It consists of a transistor Q4 for adjusting the negative voltage VCC4 applied to (G1). Here, a resistor R5 and a capacitor C2 are connected to the base of the transistor Q4, a resistor R6 is connected to an emitter of the transistor Q4, and a collector of the transistor Q4 is connected to the base of the transistor Q4. The bias voltage VCC3 is connected.

In an embodiment of the present invention, the transistors Q1, Q2, and Q4 are PNP type transistors, and the transistor Q3 is an NPN type transistor.

The grid level adjusting unit 7 for adjusting the voltage level of the first grid terminal G1 is connected between the collector of the transistor Q4 and the first grid terminal G1 of the first terminal.

The operation of the circuit of the present invention configured as described above is described in detail.

First, when the power supply voltage is initially supplied from the power unit 6 to the CALTI 1, the microcomputer 2 is decoded for a period t1 as shown in (a), (b) and (d) of FIG. A 'high' signal is input to the bases of the transistors Q1 and Q2 through the terminal and the mute terminal. Then, the transistors Q1 and Q2 are turned on, so that the bias voltage VCC1 applied to the base of the transistor Q3 is transferred to the transistors Q1 and Q2 via the resistor R1 and the diode D3. Will flow. Accordingly, this PNP type transistor Q3 is turned on, so that a bias voltage VCC1 is applied to the base of the transistor Q4 via the transistor Q3 and the resistor R4. As a result, the transistor Q4 is turned on in accordance with the output voltage of the transistor Q3, and thereby greatly increases the negative voltage VCC4 applied to the first grid terminal G1 of the STI 1. . For example, as shown in (e) of FIG. 3, the grid level adjusting unit 7 temporarily drops the first grid voltage applied to −20 [V] during the t1 period to −120 [V]. The screen of the CTI 1 is momentarily dark so that no spot phenomenon occurs.

When the microcomputer 2 is in the normal state during the operation, the 'high' signal applied to the DM terminal and the mute terminal is converted into the 'low' signal. Accordingly, as the 'low' signal is output from the DM terminal and the mute terminal of the microcomputer 2, the transistors Q1 and Q2 are turned off and thus the transistors Q3 and Q4 are turned off. Therefore, the grid level adjustment unit 7 supplies the normal grid voltage to the first grid terminal G1 of the central terminal 1 at the set grid voltage level so that the central terminal 1 operates normally. At this time, the deflection drive IC (3) controls the electron beam deflection action of the CALTI (1) according to the control signal of the microcomputer (2).

However, if an abnormal state such as a power saving mode is set, a screen mode is changed, or a power signal is turned on or off occurs in the video display device, the microcomputer 2 determines this and executes the spot removal function. .

For example, when the mode is changed in the normal state, since the horizontal and vertical synchronous frequencies are different, the screen of the CTI (1) is instantaneously collapsed. In this case, the microcomputer 2 does not display the phenomenon on the screen. By judging, the 'high' signal is applied to the base of the transistor Q2 during the t4 period as shown in (b) of FIG. 3 through the mute terminal. Here, the microcomputer 2 needs a predetermined time, for example, a time t2 of FIG. 3 in order to determine an abnormal state according to the mode conversion, wherein the deflection driving IC 3 is connected to the unlock terminal of FIG. As shown in Fig. 2), the 'high' signal is applied to the base of the transistor Q2 by t3 faster than the 'high' signal output from the mute terminal of the microcomputer 2. This makes the transient of the screen faster on the screen of the CALTI 1.

Accordingly, according to the 'high' signal output from the unlock terminal of the deflection driving IC 3 and the 'high' signal output from the mute terminal of the microcomputer 2, the transistor (for the period t5 shown in FIG. Q2) is turned on. As the transistor Q2 is turned on, the bias voltage VCC1 applied to the base of the transistor Q3 flows to the transistor Q2 via the resistor R1. Accordingly, the PNP transistor Q3 is turned on and an output voltage of the transistor Q3 is applied to the base of the transistor Q4 via the resistor R4. Accordingly, the transistor Q4 is turned on in accordance with the output voltage of the transistor Q3, thereby rapidly increasing the negative voltage VCC4 applied to the first grid terminal G1 of the STI 1. . For example, as shown in (e) of FIG. 3, the grid level adjusting unit 1 temporarily drops the first grid voltage applied to −20 [V] during the t5 period to −120 [V]. As a result, the screen of the CTI 1 is momentarily dark and no spot phenomenon occurs.

Here, the capacitor C1 connected to the emitter of the transistor Q3 is charged in normal operation, but when powered off, the charge voltage of the capacitor C1 is discharged to the base of the transistor Q3 via the resistor R6. do. Therefore, even when the power is turned off, since the transistor Q3 is turned off while the capacitor C1 is being discharged, the normal grid voltage is supplied to the first grid terminal G1 of the CALTI 1. Therefore, the spot phenomenon of the cialty 1 is prevented even at power-off.

Here, the transistors Q1 to Q3 are configured in the form of an OR gate, so that the transistor Q3 is turned on even when only one signal of the microcomputer 2 or the deflection driver IC 3 is input.

As described above, the present invention detects a mode change or a transient phenomenon of an image display device to reduce the control grid voltage of the CRT, thereby eliminating the spot phenomenon of the screen, and of the horizontal deflection IC before the mute stage of the microcomputer. Since the horizontal unlock stage controls the control grid voltage of the CRT, the error rate of the spot killer circuit can be minimized.

Claims (4)

The microcomputer 2 generates a spot control signal through the mute terminal and the DM terminal by judging the abnormal state of the video display device, and operates according to the operation control signal of the microcomputer 2, and unlocks the abnormal state of the video display device. In the spot killer circuit of a video display device having a deflection drive IC (3) for generating a spot control signal through a terminal, A transistor Q1 connected to the DM terminal of the microcomputer 2 and switching according to a spot control signal output from the DM terminal; A transistor Q2 connected to the mute terminal of the microcomputer 2 and the unlock terminal of the deflection driver IC 3 and switching according to a spot control signal input from the microcomputer 2 or the deflection driver IC 3; , A transistor Q3 connected to the common connection point C of the transistors Q1 and Q2 and operated according to the outputs of the transistors Q1 and Q2 to output a switching control signal; And a spot removing unit 5 which controls the voltage of the first grid terminal G1 of the CT 1 to remove the spot phenomenon of the CT 1 according to the switching control signal. Spot killer circuit of equipment. The spot removing unit (5) is connected to the collector of the transistor (Q3) and applied to the first grid terminal of the STI (1) according to the spot switching signal input from the transistor (Q3). A spot killer circuit of a video display device, characterized in that it comprises a transistor (Q4) for adjusting the voltage. The spot killer circuit of claim 2, wherein the transistors (Q1, Q2) are NPN transistors, and the transistors (Q3) are PNP transistors. The spot killer circuit of claim 2, wherein the transistors (Q1-Q3) are connected in an OR gate form.