KR19990026124A - Metal contact method for landing pad - Google Patents

Abstract

The present invention relates to a metal contact forming method, and more particularly, to a metal contact forming method of a semiconductor memory device having a landing pad. In the metal contact method of a highly integrated semiconductor memory device, a first layer is formed on a semiconductor substrate. And forming a second layer connected to the semiconductor substrate under the first layer, and then forming a metal contact with the second layer, which is the pad poly.

Description

Metal contact method about landing pad

The present invention relates to a method for forming a contact hole in a highly integrated semiconductor memory device, and more particularly, to a method for forming a contact hole using a landing pad.

As the density of memory devices increases day by day, the design rules required by the devices are gradually decreasing from about 1 μm to about 0.15 μm in the era of dynamic random access memory (DRAM). On the other hand, the area in which cell capacitors can be made is decreasing, and methods for obtaining desired cell capacitance have been proposed. In addition, as much wiring as desired using the reduced design rule increases the number of interlayer wirings, which makes it difficult to make a metal contact (MC) to the final active region. Therefore, a problem arises in that a metal contact process having an aspect ratio of 5 or more must be stably performed. That is, the area of the contact hole, which is an electrical contact portion for silicon, is gradually decreasing, and the aspect ratio also tends to increase gradually as a 3D capacitor is manufactured and used in the vertical direction.

In addition, when the aspect ratio is large, a large amount of etching is required to form a contact hole when the step is large when etching for the metal contact.In this case, a silicon junction due to overetching is required when forming a low step contact hole. There is a problem that can not prevent the loss of). If there is a method to fill the metal after performing the etch, it also becomes difficult. Instead, the active layer is turned on in advance with a conductive layer (eg, bit line) before filling the metal, and then the metal process is used to form only the metal contacts in the corresponding areas, but this also reduces design rules. It is difficult to deal with the problem.

1 shows a layout of a DRAM memory cell.

Referring to FIG. 1, in order to convert a metal contact into a direct contact (dc), a spacer is required on both sides between bit lines, such as A, and between bit lines B / L a and B / L a '. One bit line pad B / L pad and one metal contact MC are required. In this case, a metal contact is formed on the bit line pad 100.

FIG. 2A illustrates a metal contact of portion A of FIG. 1, wherein bit line pads exist between bit lines, and metal contacts with the active region 14 of the substrate are formed through the bit line pad 100. Looking at it in the y-y 'direction it is possible to obtain a cross-sectional view as shown in FIG. A bit line pad 100 for an active region is formed on the semiconductor substrate between the bit lines a-a ′, and a metal contact with the bit line pad 100 is made. However, the spacer design rules between the bit lines are difficult to guarantee, and at the same time, the bit line pad 100 that connects the semiconductor substrate and the metal is not sufficient, so that the bit line to DC overlap margin or A problem arises in that metal contact to bit line overlap margin cannot be secured stably.

Accordingly, an object of the present invention is to prevent over-etching at the time of low step contact etching due to the deep step metal contact by the metal contact method.

1 shows a layout of a DRAM memory cell:

2A shows a metal contact according to the prior art:

Figure 2b shows a cross section of figure 2a:

3A through 3C are process drawings sequentially showing a pad poly forming method:

4A illustrates a metal contact according to an embodiment of the present invention:

4b is a sectional view showing a cross section of FIG. 4a:

* Explanation of symbols for main parts of the drawings

10 semiconductor substrate 12 field oxide film

14 active region 16 gate electrode

18: interlayer insulating film 20, 200: pad poly

(Configuration)

According to one feature for achieving the above object, in the metal contact method of a highly integrated semiconductor memory device, the first layer is formed on the semiconductor substrate, and the pad poly is connected to the semiconductor substrate below the first layer After forming the second layer, a metal contact to the second layer is formed.

In a preferred embodiment, the first layer and the second layer is characterized in that the connection with the substrate is different depending on the concentration of the surface of the semiconductor substrate.

In an exemplary embodiment, the first layer is positioned in a region where metal contact is made with the p + doped substrate, and the second layer is positioned in an region where metal contact is made with the n + doped substrate.

In a preferred embodiment, the first layer is a bit line corresponding to the semiconductor substrate doped at a first concentration.

In a preferred embodiment, the second layer is characterized in that the pad poly corresponding to the semiconductor substrate doped at a second concentration different from the first concentration.

In a preferred embodiment, the second layer is inserted between the first layer and the semiconductor substrate.

By this method, even with a reduced design rule, the overlap margin between the metal contacts can be sufficiently secured.

(Example)

Reference to the preferred embodiment of the present invention will be described in detail based on Figures 3a to 3d and 4a to 4b.

Referring to FIG. 4B, in the method of forming a metal contact, the metal contact is made indirectly by using a layer instead of directly connecting the metal on the silicon substrate, thereby sufficiently securing the overlap margin between the contacts even if the design rule is reduced. have.

3A to 3C are views sequentially illustrating a method of forming a pad poly of a DRAM cell, and FIG. 3D is a view viewed from the top.

First, referring to FIG. 3A, a field oxide layer 12 is formed on the semiconductor substrate 10 to isolate or isolate elements, thereby defining an active region 14 and an inactive region of the semiconductor substrate 12. Next, the gate electrode 16 is formed on the substrate 12. Then, the interlayer insulating film 18 is formed over the semiconductor substrate.

Subsequently, in FIG. 3B, after etching for the contact holes in the remaining regions except for the gate electrode on the semiconductor substrate 10, the pad poly 20 is deposited.

In FIG. 3C, unnecessary polys are removed through photolithography and etching. This forms a poly pattern. Since the photo process and the etching process are well known to those skilled in the art, detailed descriptions thereof will be omitted below.

3D illustrates a top view of a poly pattern formed on a substrate, wherein pad polys 20 are connected to an active region 14 of a substrate between gate electrodes 16.

4A is a view illustrating a metal contact method, and FIG. 4B is a cross-sectional view of FIG. 4A viewed in the z-z 'direction.

Referring to FIG. 4A, a pad poly 200 and a metal contact therebetween are formed between the bit lines B / La and B / La '. Looking at this in the z-z 'direction, a pad poly 200 is formed in the active region of the semiconductor substrate with a bit line and a contact with the metal under the bit line, and the metal contact is made to the pad poly 200. In this case, the width of the pad poly 200 can be adjusted by the flow rate to ensure sufficient overlap margin with the metal. Unlike all conventional metal contacts made to the bit line pad 100, the pad poly does not directly connect the metal and the semiconductor substrate by using the pad poly 200 used in the memory cell array. By forming a metal contact using the pad poly 200, a stable process may be performed along with securing a contact overlap margin.

Referring to FIG. 4B, a bit line is formed where a metal contact of p + is formed for a metal contact, and a pad poly for the metal contact is formed where a metal contact of n + is formed to connect the active region and the bit line. The larger the width of the landing pad 200 is, the more stable the process may be performed. The pad poly 200 is formed below the bit lines, not between the bit lines, ie, between the first layer, which is the bit lines, and the active region 14 of the semiconductor substrate. It is possible to prevent overetching due to the pad pulleys during low step contact etching with respect to the city.

In the present invention, by forming a pad poly in the memory cell array on the semiconductor substrate instead of the direct contact between the semiconductor substrate and the metal, the overlap margin of the contact can be secured, and the over etching of the low step can be prevented when the deep step is etched. It has an effect.

Claims (6)

A metal contact method of a highly integrated semiconductor memory device, comprising: forming a first layer over a semiconductor substrate, forming a second layer connected to the semiconductor substrate under the first layer, and then forming a second layer and a metal A metal contact method of a semiconductor memory device, characterized in that forming a contact. The method of claim 1, And the first layer and the second layer are connected to the substrate according to the concentration of the surface of the semiconductor substrate. The method of claim 2, And the first layer is located in a region where metal contact is made with the p + doped substrate and the second layer is in a region where metal contact is made with the n + doped substrate. The method of claim 1, And the first layer is a bit line corresponding to the semiconductor substrate doped at a first concentration. The method of claim 1, And wherein the second layer is a pad poly corresponding to a semiconductor substrate doped at a second concentration different from the first concentration. The method of claim 1, And the second layer is interposed between the first layer and the semiconductor substrate.