KR19990024816A - Interlayer insulating layer formation method using spin on glass layer - Google Patents

Abstract

A method of forming an interlayer insulating layer using a spin on glass (SOG) layer is disclosed. The present invention forms a conductive pattern on the first insulating layer. Thereafter, a second SOG layer covering the conductive pattern is formed on the first insulating layer. Thereafter, the second SOG layer is cured with an electron beam. Subsequently, a first SOG layer is formed on the cured second SOG layer. Next, the first SOG layer is cured with an electron beam. Alternatively, a third insulating layer is formed on the cured second SOG layer. Thereafter, the cured second SOG layer and the first SOG layer or the second SOG layer and the third insulating layer are planarized. In this case, the planarization may be performed by polishing the second SOG layer and the first SOG layer or the second SOG layer and the third insulating layer which are cured by a chemical mechanical polishing method. Further, after the planarizing step, a second insulating layer is further formed on the planarized first SOG layer and the second SOG layer or the third insulating layer and the second SOG layer.

Description

Interlayer insulating layer formation method using spin on glass layer

The present invention relates to a method for forming an interlayer insulating layer of a semiconductor device, and more particularly to a method for forming an interlayer insulating layer using a spin on glass (hereinafter referred to as SOG) layer.

As semiconductor devices have been highly integrated, there has been a demand for multilayer metal wiring structures in wiring. Increasing the step by the multi-layered metal wiring structure is required global planarization, the use of chemical mechanical polishing (hereinafter referred to as CMP) method as a global planarization method. Accordingly, there is a need for a method for forming an interlayer insulating layer that is easy to apply the CMP method. In addition, as the integration of the semiconductor device is increased, the distance between metal wirings is narrowing. There is a need for a method for forming an interlayer insulating layer that can effectively fill such a narrow gap. In addition, as the operation speed of the semiconductor device is required to increase, an interlayer insulating layer capable of suppressing or reducing the size of parasitic capacitance generated between the multilayer metal wirings is required.

An interlayer insulating layer forming method using a spin on glass (SOG) layer has been proposed as an interlayer insulating layer forming method that satisfies the above requirements. Among these SOG layers, the low dielectric inorganic SOG layer and the organic SOG layer, which exhibit low dielectric properties, can implement a reduction in parasitic capacitance occurring between metal wirings. In addition, since the SOG layer is formed by a spin coating method, the SOG layer is excellent in gap-filling ability to fill a narrow metal interconnect. Therefore, there is an advantage that can easily fill the narrow metal wiring. However, the SOG layer has a very high etching rate when the dry etching process or the wet etching process is applied. Therefore, in the etching process, it is difficult to control the etching process. In addition, the material itself is not robust due to the characteristics of the SOG layer. Therefore, when the CMP method is applied, defects such as micro-scratch may occur in the SOG layer. In addition, when the cleaning is performed after applying the CMP method, a defect in which the SOG layer is etched may be caused by severe chemicals, that is, being severely invaded by the cleaning liquid. In addition, bowing of the SOG layer may occur when via contact is formed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of forming an interlayer insulating layer of a semiconductor device using an SOG layer, which prevents the above-mentioned problem from occurring and realizes planarization using a CMP method.

1 to 7 are cross-sectional views illustrating a method of forming an interlayer insulating layer according to a first embodiment of the present invention.

8 to 10 are cross-sectional views illustrating a method of forming an interlayer insulating layer according to a second embodiment of the present invention.

In order to achieve the above technical problem, the present invention forms a conductive pattern on the first insulating layer. Thereafter, a first SOG layer covering the conductive pattern is formed on the first insulating layer. In this case, before the forming of the first SOG layer, a second SOG layer covering the conductive pattern is further formed, and the second SOG layer is further cured with an electron beam. In addition, the first SOG layer and the second SOG layer are formed of an organic SOG layer or an inorganic SOG layer. Next, the first SOG layer is cured with an electron beam. Thereafter, the cured first SOG layer is planarized. At this time, the cured second SOG layer below the cured first SOG layer is also planarized. In addition, the planarization step is performed by polishing the cured first SOG layer or the cured first SOG layer and the cured second SOG layer by a chemical mechanical polishing method. Further, after the planarizing, the method may further include forming a second insulating layer on the planarized first SOG layer. In this case, the second insulating layer is formed of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a combination thereof.

In addition, in order to achieve the above technical problem, the present invention forms a conductive pattern on the first insulating layer. Subsequently, a second SOG layer covering the conductive pattern is formed on the first insulating layer. In this case, the second SOG layer is formed of an organic SOG layer or an inorganic SOG layer. Next, the second SOG layer is cured with an electron beam. Thereafter, a third insulating layer is formed on the second SOG layer. Subsequently, the third insulating layer and the cured second SOG layer are planarized. In this case, the planarizing of the third insulating layer and the second SOG layer may be performed by polishing the third insulating layer and the second SOG layer by a chemical mechanical polishing method. The third insulating layer may be formed of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a combination thereof. In addition, after the planarizing of the third insulating layer, a second insulating layer is further formed on the planarized third insulating layer and the second SOG layer. The second insulating layer may be formed of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a combination thereof.

According to the present invention described above, after forming the SOG layer, such as the first SOG layer and the second SOG layer, the SOG layer is cured with an electron beam. By introducing the cured SOG layer as described above, it is possible to prevent the occurrence of defects such as minute scratches and intrusion in the cured SOG layer, and to planarize the SOG layer by the CMP method. In addition, in the cleaning step following the application of the CMP method, it is possible to prevent the occurrence of intrusion in the planarized SOG layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are cross-sectional views illustrating a method of forming an interlayer insulating layer according to a first embodiment of the present invention.

1 illustrates a step of forming a conductive pattern 300 on the first insulating layer 200.

Specifically, a first insulating layer 200 is formed on the semiconductor substrate 100, and a conductive film is formed on the first insulating layer 200. Thereafter, the conductive film is patterned to form a conductive pattern 300. At this time, the conductive pattern 300 is a metal layer pattern used as the wiring structure of the semiconductor device. For example, the metal layer pattern is made of an aluminum (Al) layer, a copper (Cu) layer, a tungsten (W) layer, or the like. The conductive pattern 300 is electrically connected to the semiconductor substrate 100 through a contact hole (not shown) formed in the first insulating layer 200. Or devices connected to the semiconductor substrate 100 such as capacitors (not shown) or transistors (not shown).

2 illustrates a step of forming a second SOG layer 400 covering the conductive pattern 300.

Specifically, an organic SOG layer or an inorganic SOG layer having a low dielectric constant is formed on the conductive pattern 300 using a spin coating method or the like. In this way, the second SOG layer 400 covering the conductive pattern 300 is formed. In addition, an insulating layer (not shown) may be further formed as a lower layer of the second SOG layer 400 to a thickness of about 500 GPa or less. In addition, the second SOG layer 400 may be formed at a time up to a thickness required for subsequent global planarization, but in the present embodiment, the second SOG layer 400 is formed by implementing the thickness required by forming the SOG layer twice. do.

3 illustrates a step of curing the second SOG layer 400.

Specifically, the second SOG layer 400 is cured by multiple exposure of an electron beam by a plasma method to the surface of the second SOG layer 400. In this case, the energy of the electron beam is adjusted so that only a part of the second SOG layer 400 formed on the conductive pattern 300 is cured. That is, a portion of the second SOG layer 400 filling the conductive patterns 300 is not cured. As such, by curing only up to a partial thickness on the surface or the surface of the second SOG layer 400, a portion of the second SOG layer 400 filling the conductive patterns 300 may maintain low dielectric properties. Accordingly, generation of conventional parasitic capacitance and increase in the amount of the conductive pattern 300, that is, between the metal wirings can be further suppressed.

In this way, the second SOG layer 400 is cured by the electron beam, and the film quality thereof is modified. Such a curing method using an electron beam may modify the film quality of the second SOG layer 400 more firmly than a baking or alloy method, which is a curing method by heat treatment. . By such modification of the film quality, the etching rate, especially the wet etching rate, is lowered, and it is possible to prevent the occurrence of warping during the formation of the via contact. Thereby, process control in the subsequent etching process becomes easy. In addition, it is possible to prevent the occurrence of defects such as fine scratches in the planarization step by the CMP method later. Therefore, since the planarization by the CMP method can be applied, a reduction in the process time for the planarization can be realized. In addition, since the etch rate of the second SOG layer 400 may be reduced, the occurrence of defects due to chemical intrusion in the cleaning step following the planarization step by the CMP method may be prevented.

4 illustrates forming a first SOG layer 500 on a second SOG layer 400.

Specifically, the first SOG layer 500 is formed on the second SOG layer 400. In this case, the first SOG layer 500 is formed by a spin coating method or the like. In this manner, the first SOG layer 500 and the second SOG layer 400 have a thickness sufficient to compensate for and overcome the step difference of the conductive pattern 300. In this embodiment, the case in which the SOG layer is formed twice such as the first SOG layer 500 and the second SOG layer 400 is considered. However, in some cases, the first SOG layer 500 is formed once. By introducing only the step of, the step of the conductive pattern 300 may be overcome. Alternatively, a method of introducing two or more SOG layer forming processes may be possible.

5 illustrates a step of curing the first SOG layer 500.

Specifically, the surface of the first SOG layer 500 formed on the second SOG layer 400 is irradiated with an electron beam to cure the first SOG layer 500. In this case, the electron beam approaches the inside of the first SOG layer 500 as much as the thickness of the first SOG layer 500. Therefore, the entirety of the first SOG layer 500 is cured entirely by the electron beam. As described above, the entirety of the film quality of the first SOG layer 500 is cured by the electron beam, so that the film quality is more firmly modified. By such modification of the film quality, the etching rate, especially the wet etching rate, is lowered, and it is possible to prevent the occurrence of warping during the formation of the via contact. Therefore, the process control of the subsequent etching process becomes easier. In addition, it is possible to prevent the occurrence of defects such as fine scratches in the planarization step by the CMP method later. That is, it is possible to prevent the occurrence of intrusion during the polishing of the first SOG layer 500 by the CMP method, it is possible to apply the planarization process by the CMP method. Thus, a reduction in the process time for planarization can be realized. In addition, since the etching rate of the first SOG layer 500 may be reduced, it is possible to prevent the occurrence of chemical interference in the cleaning step following the planarization step by the CMP method. In this manner, the formation of the SOG film having a high flatness can be realized.

6 illustrates a step of planarizing the first SOG layer 500.

Specifically, by applying the CMP method, polishing is started from the surface of the first SOG layer 500. In this case, polishing may be performed to the second SOG layer 400 under the first SOG layer 500. As described above, the first SOG layer 500 is polished using the CMP method to planarize the curved surfaces of the first SOG layer 500 and the second SOG layer 400 due to the step of the conductive pattern 300. In this manner, the formation of the SOG layer having high flatness, that is, the planarized first SOG layer 500 and the second SOG layer 400 is realized.

At this time, since the first SOG layer 500 and the second SOG layer 400 are cured by an electron beam, when applying planarization by the CMP method, defects such as minute defects are more likely to occur than in the conventional case. Suppressed. That is, no damage occurs in the first SOG layer 500 and the second SOG layer 400 by polishing by the CMP method. As such, the planarization may be performed by the CMP method, thereby reducing the planarization process time, and realizing the global planarization having a higher flatness.

7 illustrates forming a second insulating layer 600 on the planarized first SOG layer 500 and the second SOG layer 400.

Specifically, a silicon oxide (SiO ₂ ) layer, a silicon oxynitride (SiON) layer, and silicon nitride (SiN) on the first SOG layer 500 and the second SOG layer 400 implemented by global planarization by the CMP method. An insulating layer such as a layer, a combination layer thereof, and the like are formed and used as the second insulating layer 600. In this manner, an interlayer insulating layer including the first SOG layer 500, the second SOG 400, and the second insulating layer 600 is formed.

As described above, by using the SOG layer having the low dielectric constant characteristic, that is, the first SOG layer 500 and the second SOG layer 400, generation of the parasitic capacitance between the conductive pattern 300, that is, the wiring can be prevented. have. In addition, the SOG layer, that is, the first SOG layer 500 and the second SOG layer 400 are cured by irradiating an electron beam, respectively, to harden the film quality of the first SOG layer 500 and the second SOG layer 400. Can be modified. In this way, the film quality is modified, and when performing the process of planarizing the first SOG layer 500 and the second SOG layer 400 by the CMP method, it is possible to prevent the occurrence of defects such as minute scratches and intrusion. It is also possible to reduce the etch rate, in particular the wet etch rate, to prevent the occurrence of erosion by chemicals, ie, cleaning liquids, in the cleaning step following the application of the CMP method. In this way, the occurrence of infringement and defects can be suppressed, and global planarization by the CMP method can be implemented, thereby reducing the process time. In addition, it is possible to implement excellent flatness.

8 to 10 are cross-sectional views illustrating a method of forming an interlayer insulating layer according to a second embodiment of the present invention.

In the second embodiment of the present invention, the same reference numerals as those in the above-mentioned first embodiment denote the same members. In addition, the method of forming the interlayer insulating layer according to the second embodiment is conceptually similar to the method of forming the interlayer insulating layer according to the first embodiment described above in that it includes forming an SOG layer and curing using an electron beam. same. However, the difference is that the CMP method can be applied to the cured SOG layer, and the planarization starts from the insulating layer.

Specifically, in the method for forming the interlayer insulating layer according to the second embodiment of the present invention, the conductive pattern 300 is formed on the first insulating layer 200 by the method described with reference to FIG. 1. Thereafter, the second SOG layer 400 covering the conductive pattern 300 is formed by the method described with reference to FIG. 2. Next, the second SOG layer 400 is cured by using an electron beam in the same manner as described with reference to FIG. 3. The film quality of the second SOG layer 400 is modified by such curing.

8 illustrates forming a third insulating layer 700 on the cured second SOG layer 400.

Specifically, on the cured second SOG layer 400, an insulating layer having a film quality that is applicable to polishing by the CMP method, that is, a film quality that is hard enough to be polished by the CMP method may be formed to form a third layer. It is used as the insulating layer 700. For example, an insulating layer formed by a chemical vapor deposition (hereinafter referred to as CVD) method is used as the third insulating layer 700. Examples of the insulating layer formed by the CVD method, that is, the CVD layer, include an insulating layer such as a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a combination layer thereof, and the like formed by the CVD method. In this case, the third insulating layer 700 has a thickness sufficient to compensate for and overcome the step difference of the conductive pattern 300.

9 illustrates a planarization of the third insulating layer 700 and the cured second SOG layer 400.

Specifically, polishing is started from the surface of the third insulating layer 700 by applying the CMP method. At this time, the cured second SOG layer 400, which is a lower layer of the third insulating layer 700, is also polished. As described above, the third insulating layer 700 and the second SOG layer 400 are polished by using the CMP method, and thus the third insulating layer 700 and the second SOG layer 400 due to the step difference of the conductive pattern 300 are polished. Planarized curved surface In this manner, the third insulating layer 700 and the second SOG layer 400 having high flatness are implemented.

At this time, when polishing by the CMP method extends to the cured second SOG layer 400, defect generation of the second SOG layer 400, such as a fine flaw, is suppressed, unlike in the conventional case. That is, since the second SOG layer 400 is cured by multiple irradiation of electron beams, the second SOG layer 400 is not infringed by polishing by the CMP method. As such, it is possible to apply a CMP method to prevent the occurrence of defects such as minute scratches and intrusions, thereby realizing a reduction in time of the planarization process, and to realize global planarization with higher flatness.

FIG. 10 illustrates forming a second insulating layer 600 on the planarized third insulating layer 700 and the second SOG layer 400.

Specifically, insulation such as a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a combination thereof, on the third insulating layer 700 and the second SOG layer 400 where global planarization is implemented by the CMP method. Form a layer. The insulating layer thus formed is used as the second insulating layer 600. As such, an interlayer insulating layer including the planarized second SOG layer 400, the planarized third insulating layer 700, and the second insulating layer 600 is formed.

As described above, by using the second SOG layer 400 having the low dielectric constant, generation of the parasitic capacitance between the conductive pattern 300, that is, the wiring can be prevented. In addition, by curing the second SOG layer 400 by irradiation with an electron beam, the film quality of the second SOG layer 400 may be hardly modified. In addition, by forming the third insulating layer 700 of a hard film quality on the cured second SOG layer 400, when the planarization process by the CMP method is performed, defects such as fine scratches and intrusions are prevented. You can prevent it. In addition, the etch rate of the second SOG layer 400 may be reduced, in particular, the wet etch rate, so that the intrusion of the flattened second SOG layer 400 may be prevented in the cleaning step following the application of the CMP method. You can prevent it. In this way, the occurrence of infringement and defects can be suppressed, and global planarization by the CMP method can be implemented, thereby reducing the process time. In addition, it is possible to implement excellent flatness.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, by using the SOG layer having the low dielectric constant as described above, it is possible to prevent the generation of the conductive pattern, that is, the parasitic capacitance between the wirings. In addition, the film quality can be hardly modified by irradiating and curing the SOG layer with an electron beam. As such, the film quality can be modified to reduce the occurrence of warping of the SOG layer when forming the via contact.

Accordingly, the cured SOG layer or the insulating layer formed on the cured SOG layer may be planarized by the CMP method. That is, when planarized by the CMP method, it is possible to prevent the occurrence of defects such as minute scratches and intrusions in the treated SOG layer. In addition, the etch rate of the SOG layer used, in particular, the wet etch rate, can be reduced, thereby preventing the occurrence of intrusion in the planarized SOG layer in the cleaning step following the application of the CMP method. That is, the generation of defects can be suppressed, and the SOG layer can be polished by the CMP method. In addition, the occurrence of infringement and defects can be suppressed as described above, and global flattening by the CMP method can be implemented, thereby reducing the processing time. In addition, better flatness can be achieved.

Claims (13)

Forming a conductive pattern on the first insulating layer; Forming a first SOG layer overlying the conductive pattern on the first insulating layer; Curing the first SOG layer with an electron beam; And Planarizing the cured first SOG layer. The method of claim 1, prior to forming the first SOG layer. Forming a second SOG layer covering the conductive pattern; And And curing the second SOG layer with an electron beam. The method of claim 2, wherein in the step of curing the second SOG layer with an electron beam, And only a partial thickness of the second SOG layer disposed on the conductive pattern is cured. 4. The method of claim 3, wherein curing the first SOG layer with an electron beam And the curing is applied to the entirety of the first SOG layer. The method of claim 2, wherein the first SOG layer and the second SOG layer are organic SOG layers or inorganic SOG layers. The method of claim 1, wherein the planarizing the cured first SOG layer comprises: A method of forming an interlayer insulating layer of a semiconductor device, characterized in that it is carried out by polishing the cured first SOG layer by a chemical mechanical polishing method. The method of claim 1, further comprising planarizing the cured first SOG layer. Forming a second insulating layer on the planarized first SOG layer. The method of claim 7, wherein the second insulating layer is formed of any one insulating layer selected from a group of insulating layers including a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a combination thereof. An interlayer insulating layer forming method of a semiconductor device. Forming a conductive pattern on the first insulating layer; Forming a second SOG layer covering the conductive pattern on the first insulating layer; Curing the second SOG layer with an electron beam; Forming a third insulating layer on the cured second SOG layer; And Planarizing the third insulating layer and the cured second SOG layer. 10. The method of claim 9, wherein in curing the second SOG layer with an electron beam And only a partial thickness of the second SOG layer disposed on the conductive pattern is cured. The semiconductor of claim 9, wherein the planarizing of the third insulating layer and the cured second SOG layer is performed by polishing the third insulating layer and the cured second SOG layer by a chemical mechanical polishing method. Method of forming an interlayer insulating layer of the device The method of claim 9, wherein the third insulating layer is formed of any one insulating layer selected from a group of insulating layers consisting of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer and a combination layer thereof. Method for forming an interlayer insulating layer of a semiconductor device. 10. The method of claim 9, further comprising planarizing the third insulating layer and the cured second SOG layer. And forming a second insulating layer on the planarized third insulating layer and the second SOG layer.