KR100850102B1 - Chemical-mechanical polishing process of an interlayer dielectric and apparatus for compensating a step of a chemical-mechanical polishing process thereof - Google Patents

Chemical-mechanical polishing process of an interlayer dielectric and apparatus for compensating a step of a chemical-mechanical polishing process thereof Download PDF

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KR100850102B1
KR100850102B1 KR1020060129380A KR20060129380A KR100850102B1 KR 100850102 B1 KR100850102 B1 KR 100850102B1 KR 1020060129380 A KR1020060129380 A KR 1020060129380A KR 20060129380 A KR20060129380 A KR 20060129380A KR 100850102 B1 KR100850102 B1 KR 100850102B1
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insulating film
wafer
interlayer insulating
cmp process
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KR20080056459A (en
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김활표
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers

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Abstract

본 발명은 층간절연막의 CMP 공정에 관한 것으로서, 층간절연막의 CMP 공정에 있어서, 웨이퍼에 메탈층의 갭필(gap fill)을 위하여 갭필용 절연막을 형성시키는 단계와, 갭필용 절연막이 형성된 웨이퍼의 에지부분에 단차 보상을 위하여 단차보상용 절연막을 형성시키는 단계와, 단차보상용 절연막이 형성된 웨이퍼에 층간절연막을 형성시키는 단계와, 층간절연막이 형성된 웨이퍼를 CMP에 의해 폴리싱하는 단계를 포함한다. 따라서, 본 발명은 층간절연막의 평탄화시 평탄도를 향상시키고, 웨이퍼의 에지부분에 위치하는 소자의 숏 패일(short fail)을 개선하며, 이로 인해 웨이퍼의 수율을 향상시키는 효과를 가지고 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMP process of an interlayer insulating film, comprising the steps of: forming a gapfill insulating film for a gap fill of a metal layer on a wafer; Forming a step compensation insulating film to compensate for the step difference, forming an interlayer insulating film on the wafer on which the step compensation insulating film is formed, and polishing the wafer on which the interlayer insulating film is formed by CMP. Accordingly, the present invention has the effect of improving the flatness during the planarization of the interlayer insulating film, and short short of the device located at the edge of the wafer, thereby improving the yield of the wafer.

Description

층간절연막의 ＣＭＰ 공정 및 이에 사용되는 단차 보상장치{CHEMICAL-MECHANICAL POLISHING PROCESS OF AN INTERLAYER DIELECTRIC AND APPARATUS FOR COMPENSATING A STEP OF A CHEMICAL-MECHANICAL POLISHING PROCESS THEREOF}CMP process of interlayer insulating film and step compensator used in it {CHEMICAL-MECHANICAL POLISHING PROCESS OF AN INTERLAYER DIELECTRIC AND APPARATUS FOR COMPENSATING A STEP OF A CHEMICAL-MECHANICAL POLISHING PROCESS THEREOF}

도 1a 내지 도 1d는 종래의 기술에 따른 층간절연막의 CMP 공정을 도시한 도면이고, 1A to 1D are diagrams illustrating a CMP process of an interlayer insulating film according to the related art.

도 2a 내지 도 2e는 본 발명에 따른 층간절연막의 CMP 공정을 도시한 도면이고,2A to 2E are diagrams illustrating a CMP process of an interlayer insulating film according to the present invention.

도 3은 본 발명에 따른 층간절연막의 CMP 공정에 사용되는 단차 보상장치를 도시한 개략도이다.3 is a schematic diagram showing a step compensation device used in a CMP process of an interlayer insulating film according to the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11 : 메탈층 12 : 갭필용 절연막11 metal layer 12 insulating film for gap fill

13 : 단차보상용 절연막 14 : 층간절연막13 insulating film for step compensation 14 interlayer insulating film

21 : 웨이퍼척 21a : 회전축21: wafer chuck 21a: rotation axis

22 : 회전수단 23 : SOG 공급노즐22: rotation means 23: SOG supply nozzle

24 : SOG 용액공급부24: SOG solution supply

본 발명은 층간절연막의 CMP 공정에 관한 것으로서, 보다 상세하게는 층간절연막의 평탄화시 평탄도를 향상시키는 층간절연막의 CMP 공정에 관한 것이다.The present invention relates to a CMP process of an interlayer insulating film, and more particularly, to a CMP process of an interlayer insulating film for improving flatness when the interlayer insulating film is planarized.

일반적으로, 반도체 소자를 제조하는 공정에서 웨이퍼상에 단차를 갖는 구조물이 형성되며, 층간의 절연과 이러한 구조물이 형성된 결과면의 전면을 평탄화하기 위한 목적으로 층간절연막(ILD; Interlayer Dielectric)을 형성하는데, 층간절연막을 형성한 직후에는 층간절연막 아래의 구조물이 갖는 표면 형태 즉, 단차가 그대로 층간절연막에도 나타난다. 따라서 층간절연막 또는 평탄화 목적의 물질층을 형성한 후에는 평탄화 공정을 실시한다.In general, in the process of manufacturing a semiconductor device, a structure having a step is formed on a wafer, and an interlayer dielectric (ILD) is formed for the purpose of insulating the interlayer and planarizing the entire surface of the resultant surface on which the structure is formed. Immediately after the formation of the interlayer insulating film, the surface form of the structure under the interlayer insulating film, that is, the step, appears in the interlayer insulating film as it is. Therefore, the planarization process is performed after the interlayer insulating film or the material layer for planarization is formed.

최근에는 웨이퍼가 대구경화됨에 따라 웨이퍼의 넓어진 면을 평탄화하기 위한 방법으로 화학적인 제거가공과 기계적인 제거가공을 하나의 가공방법으로 혼합한 화학적 기계적 연마(Chemical-Mechanical Polishing; 이하, "CMP"라고 함) 공정이 널리 이용되고 있다. Recently, as the wafer has been large-sized, chemical-mechanical polishing (CMP), which combines chemical removal processing and mechanical removal processing in one processing method, is used to planarize the widened surface of the wafer. The process is widely used.

CMP 공정이란 단차를 가진 웨이퍼 표면을 폴리싱패드 위에 밀착시킨 후 연마제와 화학물질이 포함된 슬러리(slurry)를 웨이퍼와 폴리싱패드 사이에 주입시켜서 웨이퍼의 표면을 평탄화시키는 방식이다.In the CMP process, a wafer surface having a step is brought into close contact with a polishing pad, and a slurry containing abrasive and chemical is injected between the wafer and the polishing pad to planarize the surface of the wafer.

종래의 기술에 따른 절연층의 CMP 공정을 첨부된 도면을 참조하여 설명하면 다음과 같다. 도 1a 내지 도 1d는 종래의 기술에 따른 층간절연막의 CMP 공정을 도시한 도면이다. 도시된 바와 같이, 층간절연막의 CMP 공정은 먼저, 도 1a에 도시된 바와 같이, 웨이퍼(W)에 메탈층(1)을 형성한 다음, 도 1b에 도시된 바와 같이, 메탈층(1)의 갭필(gap fill)을 위해서 갭필용 절연막(2)을 메탈층(1)사이에 증착시킨다.Referring to the accompanying drawings CMP process of the insulating layer according to the prior art as follows. 1A to 1D are diagrams illustrating a CMP process of an interlayer insulating film according to the related art. As shown, the CMP process of the interlayer insulating film is first formed of a metal layer 1 on the wafer W, as shown in FIG. 1A, and then, as shown in FIG. A gap fill insulating film 2 is deposited between the metal layers 1 for a gap fill.

웨이퍼(W)상에 갭필용 절연막(2)이 형성되면, 도 1c에 도시된 바와 같이 메탈층(1)과 갭필용 절연막(2)상에 TEOS(Tetraethly Orthosilicate)와 같은 층간절연막(3)을 증착에 의해 형성시킨다.When the gap fill insulating film 2 is formed on the wafer W, an interlayer insulating film 3 such as TEOS (Tetraethly Orthosilicate) is formed on the metal layer 1 and the gap fill insulating film 2 as shown in FIG. 1C. It is formed by vapor deposition.

웨이퍼(W)상에 층간절연막(3)이 형성되면 도 1d에 도시된 바와 같이, CMP에 의해 층간절연막(3)을 평탄화시킨다. When the interlayer insulating film 3 is formed on the wafer W, as shown in FIG. 1D, the interlayer insulating film 3 is planarized by CMP.

그러나, 이와 같은 종래의 층간절연막의 CMP 공정은 도 1d에 도시된 바와 같이, 웨이퍼의 에지부분(E)에는 메탈층(1)이 없기 때문에 층간절연막(3)의 두께가 작을 수 밖에 없으며, 이로 인해 CMP 공정 후 층간절연막(3)상에 적층되는 새로운 메탈층이 기존의 메탈층(1)과 서로 브릿지되어 숏 페일(short fail)과 같은 기능적인 결함을 발생시킴으로써 수율을 저하시키는 문제점을 가지고 있었다. 이러한 문제점은 메탈층과 폴리간의 브릿지로 인해서도 발현될 수 있으며, 특히, 도 1b에서 웨이퍼(W)의 에지부분(E)이 프로세싱되지 않도록 에지부분에 케미컬로 처리해 주는 EBR(Edge Bead Removal)을 실시하는 경우 이러한 메탈 에칭 EBR로 인하여 웨이퍼(W)의 에지부분(E)이 다른 부분에 비해 낮은 기하학적 형태를 가짐으로써 층간절연막(3)의 CMP 공정 후 웨이퍼(W)의 에지부분(E)에 대한 단차(d)가 현저하게 발생하는 상기한 바와 같은 문제점을 가지고 있었다.However, in the conventional CMP process of the interlayer insulating film, as shown in FIG. 1D, since the metal layer 1 is not present at the edge portion E of the wafer, the thickness of the interlayer insulating film 3 is inevitably small. Due to this, a new metal layer laminated on the interlayer insulating film 3 after the CMP process is bridged with the existing metal layer 1 to generate a functional defect such as a short fail, thereby lowering the yield. . This problem may also be caused by the bridge between the metal layer and the poly, and in particular, in FIG. 1B, the edge bead removal (EBR) is chemically applied to the edge part so that the edge part E of the wafer W is not processed. In this case, due to the metal etching EBR, the edge portion E of the wafer W has a lower geometric shape than the other portions, and thus the edge portion E of the wafer W after the CMP process of the interlayer insulating film 3 is formed. There was a problem as described above in which the step d was remarkably generated.

본 발명은 상술한 종래의 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 층간절연막의 평탄화시 평탄도를 향상시키고, 웨이퍼의 에지부분에 위치하는 소자의 숏 패일(short fail)을 개선하며, 이로 인해 웨이퍼의 수율을 향상시키는 층간절연막의 CMP 공정를 제공하는데 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to improve flatness during planarization of an interlayer insulating film, and to improve short fail of devices located at edge portions of a wafer. The present invention provides a CMP process of an interlayer insulating film that improves the yield of a wafer.

이와 같은 목적을 실현하기 위한 본 발명은, 층간절연막의 CMP 공정에 있어서, 웨이퍼에 메탈층의 갭필(gap fill)을 위하여 갭필용 절연막을 형성시키는 단계와, 갭필용 절연막이 형성된 웨이퍼의 에지부분에 단차 보상을 위하여 단차보상용 절연막을 형성시키는 단계와, 단차보상용 절연막이 형성된 웨이퍼에 층간절연막을 형성시키는 단계와, 층간절연막이 형성된 웨이퍼를 CMP에 의해 폴리싱하는 단계를 포함하는 것을 특징으로 한다.In the CMP process of the interlayer insulating film, the present invention provides a method for forming a gap fill insulating film for a gap fill of a metal layer on a wafer, and an edge portion of the wafer on which the gap fill insulating film is formed. Forming a step compensation insulating film for step compensation, forming an interlayer insulating film on the wafer on which the step compensation insulating film is formed, and polishing the wafer on which the interlayer insulating film is formed by CMP.

또한, 본 발명은 층간절연막의 CMP 공정시 웨이퍼의 단차를 보상하기 위한 장치로서, 웨이퍼를 척킹하는 웨이퍼척과, 웨이퍼척을 회전시키는 회전수단과, 웨이퍼척에 척킹된 웨이퍼의 일측에 설치되며, 회전수단에 의해 회전하는 웨이퍼 에지부분에 SOG 용액을 공급하는 SOG 공급노즐을 포함하는 것을 특징으로 한다.In addition, the present invention is a device for compensating the step of the wafer during the CMP process of the interlayer insulating film, the wafer chuck to chuck the wafer, the rotation means for rotating the wafer chuck, the wafer is installed on one side of the wafer chucked to the wafer chuck, the rotation And an SOG supply nozzle for supplying the SOG solution to the rotating wafer edge portion by the means.

이하, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 본 발명의 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 더욱 상세히 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

도 2a 내지 도 2e는 본 발명에 따른 층간절연막의 CMP 공정을 도시한 도면이다. 도시된 바와 같이, 본 발명에 따른 층간절연막의 CMP 공정은 갭필용 절연막을 형성시키는 단계와, 단차보상용 절연막을 형성시키는 단계와, 층간절연막을 형성시키는 단계와, 폴리싱하는 단계를 포함한다.2A to 2E are diagrams illustrating a CMP process of an interlayer insulating film according to the present invention. As shown, the CMP process of the interlayer insulating film according to the present invention includes forming a gap fill insulating film, forming a step compensation insulating film, forming an interlayer insulating film, and polishing.

갭필용 절연막을 형성시키는 단계는 도 2a에 도시된 웨이퍼(W)에 형성된 메탈층(11)(또는 폴리(poly))의 갭필(gap fill)을 위하여 도 2b에 도시된 바와 같이, 웨이퍼(W)상에 갭필용 절연막(12)을 증착 공정에 의해 형성시키게 되는데, 이러한 갭필용 절연막(12)은 SOG(Spin on glass)막이 사용되거나, HDP(High Density Plasma Oxide)를 이용한 TEOS(Tetraethly Orthosilicate) 필름 등이 사용될 수 있다. The forming of the gap fill insulating film may include forming the gap fill insulating film for the gap fill of the metal layer 11 (or poly) formed on the wafer W shown in FIG. 2A, as shown in FIG. 2B. The gap fill insulating film 12 is formed by a deposition process, and the gap fill insulating film 12 is formed using a spin on glass (SOG) film or a tetraethly orthosilicate (TEOS) using high density plasma oxide (HDP). Films and the like can be used.

도 2c에 도시된 바와 같이, 단차보상용 절연막을 형성시키는 단계는 갭필용 절연막(12)이 형성된 웨이퍼(W)의 에지부분에 폴리싱 후에 발생하게 될 단차(d; 도 1d에 도시)의 보상을 위하여 단차보상용 절연막(13)을 형성시킨다. 이 때, 단차보상용 절연막(13)은 SOG(Spin on glass)막임이 바람직하다.As shown in FIG. 2C, forming the step compensation insulating film compensates for the step (d; shown in FIG. 1D) that will occur after polishing on the edge portion of the wafer W on which the gap fill insulating film 12 is formed. In order to form the step compensation insulating film 13. At this time, the step compensation insulating film 13 is preferably a SOG (Spin on glass) film.

한편, 단차보상용 절연막(13), 예컨대 SOG막의 최대 두께는 인접한 메탈층(11)(또는 폴리(poly)) 두께의 60% 이상 100% 이하임이 바람직하다. On the other hand, it is preferable that the maximum thickness of the step compensation insulating film 13, for example, the SOG film, is 60% or more and 100% or less of the thickness of the adjacent metal layer 11 (or poly).

도 2d에 도시된 바와 같이, 층간절연막을 형성시키는 단계는 단차보상용 절연막(13)이 에지부분에 형성된 웨이퍼(W) 전면에 걸쳐서 층간절연막(14)을 증착 공정에 의해 형성시킨다.As shown in FIG. 2D, in the forming of the interlayer insulating film, the interlayer insulating film 14 is formed by the deposition process over the entire surface of the wafer W in which the step compensation insulating film 13 is formed at the edge portion.

폴리싱하는 단계는 층간절연막(14)이 형성된 웨이퍼(W)를 CMP 장비를 사용하여 슬러리가 공급됨과 아울러 회전하는 폴리싱패드에 밀착시켜서 회전시킴으로써 도 2e에 도시된 바와 같이, 평탄화시킨다. In the polishing step, as shown in FIG. 2E, the wafer W on which the interlayer insulating film 14 is formed is rotated in contact with a rotating polishing pad while being supplied with a slurry using a CMP apparatus.

한편, 도 3은 본 발명에 따른 층간절연막의 CMP 공정에 사용되는 단차 보상장치를 도시한 개략도이다. 도시된 바와 같이, 본 발명에 따른 층간절연막의 CMP 공정에 사용되는 단차 보상장치(20)는 단차보상용 절연막(13)을 형성시키는 단계에 사용되어 층간절연막(14)의 CMP 공정시 웨이퍼(W)의 단차(d; 도 1d에 도시)를 보상하기 위한 장치로서, 웨이퍼척(21)과, 웨이퍼척(21)을 회전시키기 위한 회전수단(22)과, SOG 용액을 공급하는 SOG 공급노즐(23)을 포함한다.On the other hand, Figure 3 is a schematic diagram showing a step compensation device used in the CMP process of the interlayer insulating film according to the present invention. As shown, the step compensation device 20 used in the CMP process of the interlayer insulating film according to the present invention is used to form the step compensating insulating film 13 so that the wafer W during the CMP process of the interlayer insulating film 14 is formed. An apparatus for compensating for the step (d (shown in FIG. 1D)) of a wafer), a wafer chuck 21, a rotating means 22 for rotating the wafer chuck 21, and an SOG supply nozzle for supplying a SOG solution ( 23).

웨이퍼척(21)은 상측에 로딩되는 웨이퍼(W)를 외부로부터 공급되는 진공에 의해 흡착함으로써 척킹하고, 하측에 회전을 위한 회전축(21a)이 마련되며, 회전수단(22)에 의해 회전하게 된다.The wafer chuck 21 is chucked by absorbing the wafer W loaded on the upper side by vacuum supplied from the outside, and a rotating shaft 21a for rotation is provided on the lower side, and rotated by the rotating means 22. .

회전수단(22)은 모터를 비롯한 회전력을 발생시키는 수단으로서, 웨이퍼척(21)의 회전축(21a)에 회전력을 전달하여 웨이퍼척(21)에 척킹된 웨이퍼(W)를 회전시킨다. The rotating means 22 is a means for generating a rotating force including a motor, and transmits a rotating force to the rotating shaft 21a of the wafer chuck 21 to rotate the wafer W chucked to the wafer chuck 21.

SOG 공급노즐(23)은 웨이퍼척(21)에 척킹된 웨이퍼(W)의 일측에 설치되며, 외부의 SOG 용액공급부(24)로부터 SOG 용액을 공급받아 회전수단(22)에 의해 회전하는 웨이퍼(W)의 에지부분에 SOG 용액을 공급시킴으로써 갭필용 절연막(12)이 형성된 웨이퍼(W)의 에지부분에 단차(d : 도 1d에 도시)의 보상을 위한 단차보상용 절연막(13), 즉 SOG막을 형성시킨다.The SOG supply nozzle 23 is installed at one side of the wafer W chucked to the wafer chuck 21, and receives the SOG solution from the external SOG solution supply unit 24 and rotates by the rotating means 22 ( By supplying the SOG solution to the edge portion of W), the stepped compensating insulating film 13, i.e., SOG, for compensating the step (d: shown in FIG. 1D) at the edge portion of the wafer W on which the gap fill insulating film 12 is formed. Form a film.

이와 같은 구조로 이루어진 층간절연막의 CMP 공정 및 이에 사용되는 단차 보상장치의 작용은 다음과 같이 이루어진다.The CMP process of the interlayer insulating film having such a structure and the action of the step compensating device used therein are performed as follows.

웨이퍼(W)상에 메탈층(11) 갭필(gap fill)을 위하여 갭필용 절연막(12)을 증 착시킨 다음 도 3에 도시된 단차 보상장치(20)를 사용하여 웨이퍼(W)의 에지부분에 단차보상용 절연막(13)을 형성시킨다. The gap fill insulating film 12 is deposited on the wafer W for the gap fill of the metal layer 11, and then the edge portion of the wafer W is formed by using the step compensator 20 shown in FIG. 3. The step compensation insulating film 13 is formed on the substrate.

즉, 갭필용 절연막(12)이 증착된 웨이퍼(W)를 웨이퍼척(21)에 척킹하여 회전수단(22)의 구동에 의해 회전시키고, 회전하는 웨이퍼(W)의 에지부분에 SOG 공급노즐(23)로부터 SOG 용액을 공급시킴으로써 웨이퍼(W) 에지부분에 단차보상용 절연막(12)을 형성시키게 된다.That is, the wafer W on which the gap-fill insulating film 12 is deposited is chucked to the wafer chuck 21 to be rotated by the driving of the rotating means 22, and the SOG supply nozzle is formed at the edge portion of the rotating wafer W. By supplying the SOG solution from 23, the insulating film 12 for the step compensation is formed on the edge portion of the wafer W. As shown in FIG.

그러므로, 층간절연막(14)을 형성시키는 단계에서 웨이퍼(W) 에지부분에 메탈층(11)의 부재로 인하여 다른 부위에 비해 얇게 형성됨으로 인해 발생되는 단차(d; 도 1d에 도시)를 단차보상용 절연막(12)이 보상한다. 이로 인해, CMP 공정에 의한 폴리싱시 웨이퍼(W) 에지부분에 대한 단차를 없애고, 균일한 평탄화를 가능하도록 한다. 따라서, CMP 공정 후 층간절연막(14)상에 적층되는 새로운 메탈층이 기존의 메탈층(11)과 서로 브릿지되어 숏 페일(short fail)과 같은 기능적인 결함이 발생하는 것을 방지하며, 수율 증가를 가져온다. Therefore, in the step of forming the interlayer insulating film 14, step difference compensation (d (shown in FIG. 1D)) caused by being formed thinner than other parts due to the absence of the metal layer 11 at the edge portion of the wafer W is formed. The insulating film 12 for compensation compensates. This eliminates the step on the edge portion of the wafer W during polishing by the CMP process, and enables uniform planarization. Accordingly, a new metal layer stacked on the interlayer insulating film 14 after the CMP process is bridged with the existing metal layer 11 to prevent functional defects such as short fail from occurring and to increase yield. Bring.

특히, 도 2b에 도시된 바와 같이, 웨이퍼(W)의 에지부분(E)에 대한 EBR(Edge Bead Removal)을 실시하는 경우라도 단차보상용 절연막(13)에 의해 웨이퍼(W)의 에지부분과 중심부의 높이차가 최소화됨으로써 층간절연막(14)의 CMP 공정 후 웨이퍼(W)의 에지부분에 대한 단차 발생을 방지한다.In particular, as shown in FIG. 2B, even when Edge Bead Removal (EBR) is performed on the edge portion E of the wafer W, the edge portion of the wafer W and the edge portion of the wafer W are formed by the step compensation film 13. By minimizing the height difference in the center part, it is possible to prevent the generation of a step to the edge portion of the wafer W after the CMP process of the interlayer insulating film 14.

한편, 단차보상용 절연막(13), 예컨대, SOG막은 그 형성시 두께가 인접한 메탈층(11)(또는 폴리(poly)) 두께의 60% 이상 100% 이하가 되며, 이로 인해 SOG막의 형성시 SOG 용액이 메탈층(11)을 넘어서 웨이퍼(W)의 중심부로 침범하지 않도록 함과 동시에 SOG막 형성 후 웨이퍼(W)의 에지부분이 다른 부분에 비하여 두꺼운 막을 형성하지 않도록 함으로써 CMP 공정시 평탄도를 높일 수 있다.On the other hand, the step compensation film 13, for example, the SOG film is 60% or more and 100% or less of the thickness of the adjacent metal layer 11 (or poly) when the thickness thereof is formed, thereby SOG when forming the SOG film The solution does not invade the center of the wafer W beyond the metal layer 11 and at the same time, after forming the SOG film, the edge portion of the wafer W does not form a thick film compared to other portions, thereby improving flatness in the CMP process. It can increase.

상술한 바와 같이, 본 발명에 따른 층간절연막의 CMP 공정은 웨이퍼 에지부분의 단차를 보상함으로써 층간절연막의 평탄화시 평탄도를 향상시키고, 웨이퍼의 에지부분에 위치하는 소자의 숏 패일(short fail)을 개선하며, 이로 인해 웨이퍼의 수율을 향상시키는 효과를 가지고 있다. As described above, the CMP process of the interlayer insulating film according to the present invention improves the flatness during the planarization of the interlayer insulating film by compensating for the step difference of the wafer edge portion, and prevents the short fail of the device located at the edge portion of the wafer. This has the effect of improving the yield of the wafer.

이상에서 설명한 것은 본 발명에 따른 층간절연막의 CMP 공정을 실시하기 위한 하나의 실시예에 불과한 것으로서, 본 발명은 상기한 실시예에 한정되지 않고, 이하의 특허청구범위에서 청구하는 바와 같이 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능한 범위까지 본 발명의 기술적 정신이 있다고 할 것이다.What has been described above is only one embodiment for carrying out the CMP process of the interlayer insulating film according to the present invention, and the present invention is not limited to the above-described embodiment, and as claimed in the following claims, Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (4)

층간절연막의 CMP 공정에 있어서,In the CMP process of the interlayer insulating film, 웨이퍼에 메탈층의 갭필(gap fill)을 위하여 갭필용 절연막을 형성시키는 단계와,Forming an insulating film for gap fill on the wafer for a gap fill of the metal layer; 상기 갭필용 절연막이 형성된 웨이퍼의 에지부분에 단차 보상을 위하여 단차보상용 절연막을 형성시키는 단계와, Forming a step compensation insulating film on an edge portion of the wafer on which the gap fill insulating film is formed, for step compensation; 상기 단차보상용 절연막이 형성된 웨이퍼에 층간절연막을 형성시키는 단계와,Forming an interlayer insulating film on the wafer on which the step compensation insulating film is formed; 상기 층간절연막이 형성된 웨이퍼를 CMP에 의해 폴리싱하는 단계Polishing the wafer on which the interlayer insulating film is formed by CMP; 를 포함하고,Including, 상기 단차보상용 절연막의 형성단계는,The step of forming the step compensation insulating film, 상기 단차보상용 절연막이 메탈층 두께의 60% 이상 100% 이하의 두께를 가지도록 형성시키는 것Wherein the step compensation insulating film is formed to have a thickness of 60% or more and 100% or less of the thickness of the metal layer 을 특징으로 하는 층간절연막의 CMP 공정.CMP process of the interlayer insulating film, characterized in that. 제 1 항에 있어서, The method of claim 1, 상기 단차보상용 절연막의 형성단계는,The step of forming the step compensation insulating film, 상기 단차보상용 절연막이 SOG막인 것The step compensation insulating film is an SOG film 을 특징으로 하는 층간절연막의 CMP 공정.CMP process of the interlayer insulating film, characterized in that. 삭제delete 삭제delete
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KR19990024816A (en) * 1997-09-08 1999-04-06 윤종용 Interlayer insulating layer formation method using spin on glass layer
JPH11260822A (en) * 1998-03-13 1999-09-24 Seiko Epson Corp Semiconductor device and its manufacture
KR20050050876A (en) * 2003-11-26 2005-06-01 동부아남반도체 주식회사 Method for planarizing dielectric layer of semiconductor device

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Publication number Priority date Publication date Assignee Title
KR19990024816A (en) * 1997-09-08 1999-04-06 윤종용 Interlayer insulating layer formation method using spin on glass layer
JPH11260822A (en) * 1998-03-13 1999-09-24 Seiko Epson Corp Semiconductor device and its manufacture
KR20050050876A (en) * 2003-11-26 2005-06-01 동부아남반도체 주식회사 Method for planarizing dielectric layer of semiconductor device

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Publication number Priority date Publication date Assignee Title
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