KR100272261B1 - Planarization method of semiconductor - Google Patents
Planarization method of semiconductor Download PDFInfo
- Publication number
- KR100272261B1 KR100272261B1 KR1019960057827A KR19960057827A KR100272261B1 KR 100272261 B1 KR100272261 B1 KR 100272261B1 KR 1019960057827 A KR1019960057827 A KR 1019960057827A KR 19960057827 A KR19960057827 A KR 19960057827A KR 100272261 B1 KR100272261 B1 KR 100272261B1
- Authority
- KR
- South Korea
- Prior art keywords
- sog
- temperature
- film
- layer
- sog film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 11
- 239000011521 glass Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000013036 cure process Methods 0.000 abstract 1
- 238000005336 cracking Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
본 발명은 반도체 소자의 평탄화 방법에 관한 것으로, 보다 상세하게는, 다층 금속 배선 구조를 갖는 반도체 소자에서 SOG막을 사용하여 하부층을 평탄화시키는 방법에 관한 것이다.The present invention relates to a planarization method of a semiconductor device, and more particularly, to a method of planarizing a lower layer using an SOG film in a semiconductor device having a multilayer metal wiring structure.
반도체 소자가 고집적화됨에 따라, 다층 금속 배선 및 고밀도의 상호연결(interconnection) 구조가 이용되고 있으며, 아울러, 금속 배선 사이를 동공(void)없이 메꾸면서, 높은 에스펙트 비(aspect ratio)를 갖는 비아홀을 형성하기 위한 여러가지 방법도 제안되고 있다. 상기 다층 금속 배선 기술에서는 하층 배선의 표면 요철 때문에 발생되는 배선들 사이의 단선 및 쇼트 문제를 최소화하기 위하여, 층간절연물로서 SOG(spin on glass)막 또는 BPSG(boron-phosphorus silicate glass)막 등과 같은 복합 수지 물질들을 플로우(flow)시켜 하부층을 평탄화시킨다.As semiconductor devices have been highly integrated, multilayer metal interconnections and high-density interconnect structures have been used, and via holes with high aspect ratios can be filled, without filling voids between metal interconnections. Various methods for forming are also proposed. In the multi-layered metal wiring technology, in order to minimize the disconnection and short problems between the wirings caused by the surface irregularities of the lower layer wiring, a complex such as a spin on glass (SOG) film or a boron-phosphorus silicate glass (BPSG) film as an interlayer insulating material. The resin materials are flowed to planarize the lower layer.
한편, 층간절연막(inter dielectric film)을 형성하는데 있어서는, 스텝 커버리지(step coverage), 표면 민감도(surface sensitivity), 수분 함유(moisture content), 절연 강도(dielectric strength), 및 막 응력(film stress)과 같은 소자 신뢰성에 영향을 미치는 요소를 반드시 고려하여야 한다.On the other hand, in forming an inter dielectric film, step coverage, surface sensitivity, moisture content, dielectric strength, film stress, Factors affecting the same device reliability must be considered.
제1도는 평탄화막으로서 SOG막을 이용하는 종래 기술에 따른 반도체 소자의 평탄화 방법을 설명하기 위한 단면도로서, 이를 설명하면 다음과 같다.FIG. 1 is a cross-sectional view for explaining a planarization method of a semiconductor device according to the related art using an SOG film as a planarization film.
트랜지스터(도시안됨)가 구비된 반도체 기판(1) 상에 제1층간절연막(2)을 형성하고, 상기 제1층간절연막(2) 상에 금속배선(3)을 형성한다. 그런다음, 상기 금속배선(3)을 덮도록, 상기 제1층간절연막(2)의 전면 상에 제2층간절연막(4)을 형성한다. 그리고나서, 상기 제2층간절연막(4) 상에 평탄화막으로서 SOG막(5)를 도포한 후, 상기 SOG막(5)의 표면 평탄화가 이루어지도록, 상기 SOG막(5)을 400 내지 500℃ 온도에서 30 내지 60분 동안 큐어링(curing)한다.A first interlayer insulating film 2 is formed on the semiconductor substrate 1 provided with a transistor (not shown), and a metal wiring 3 is formed on the first interlayer insulating film 2. Then, a second interlayer insulating film 4 is formed on the entire surface of the first interlayer insulating film 2 so as to cover the metal wiring 3. Then, after the SOG film 5 is applied as the planarization film on the second interlayer insulating film 4, the SOG film 5 is 400 to 500 DEG C so that the surface of the SOG film 5 is planarized. Curing at temperature for 30 to 60 minutes.
그러나, 상기와 같은 종래 기술은, 상기 SOG막의 큐어링시, 상기 SOG막에 함유된 H2O가 외부로 방출되는 것에 기인하여, 상기 SOG막에 균열(6)이 발생되는 현상이 초래되고, 이에 따라, 반도체 소자의 제조수율 및 신뢰성이 저하되는 문제점이 있다.However, in the conventional technique as described above, due to the release of H 2 O contained in the SOG film to the outside during curing of the SOG film, a phenomenon occurs in which the crack 6 occurs in the SOG film. Accordingly, there is a problem that the manufacturing yield and reliability of the semiconductor device is lowered.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 상기 SOG막에 함유된 H2O가 외부로 방출되는 것이 방지되도록, 상기 SOG의 큐어링을 온도 구배를 두어 3단계로 나누어 실시함으로써, 상기 H2O의 외부 방출에 기인된 균열의 발생없이, 상기 SOG의 평탄화 특성을 향상시킬 수 있는 반도체 소자의 평탄화 방법을 제공하는데, 그 목적이 있다.Accordingly, the present invention has been made in order to solve the above problems, the curing of the SOG is divided into three steps with a temperature gradient so that the H 2 O contained in the SOG film is prevented from being released to the outside. It is therefore an object of the present invention to provide a planarization method of a semiconductor device capable of improving the planarization characteristics of the SOG without generation of cracks caused by external emission of the H 2 O.
제1도는 종래 기술에 따른 반도체 소자의 평탄화 방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a planarization method of a semiconductor device according to the prior art.
제2도는 본 발명에 따른 반도체 소자의 평탄화 방법을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a planarization method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 제1층간 절연막11 semiconductor substrate 12 first interlayer insulating film
13 : 금속 배선 14 : 제2층간 절연막13 metal wiring 14 2nd interlayer insulation film
15 : SOG막15: SOG film
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 평탄화 방법은, 금속배선이 형성된 반도체 기판을 제공하는 단계; 상기 금속배선을 덮도록, 상기 반도체 기판의 전면 상에 층간절연막을 형성하는 단계; 상기 층간절연막 상에 평탄화막으로서 SOG막을 도포하는 단계; 및 상기 SOG막을 온도 구배를 두어 3차례에 걸쳐 큐어링하는 단계를 포함하여 이루어지며, 상기 SOG막을 큐어링하는 단계는, 제1온도에서 프리베이크하는 제1공정과, 상기 제1온도 보다 높은 제2온도에서 가열하는 제2공정, 및 상기 제2온도 보다 높은 제3온도에서 가열하는 제3공정으로 구성되는 것을 특징으로 한다.The planarization method of the semiconductor device of the present invention for achieving the above object comprises the steps of: providing a semiconductor substrate with a metal wiring; Forming an interlayer insulating film on an entire surface of the semiconductor substrate so as to cover the metal wiring; Applying an SOG film as a planarization film on the interlayer insulating film; And curing the SOG film three times at a temperature gradient, wherein the curing of the SOG film comprises: a first process of prebaking at a first temperature; And a third step of heating at a second temperature, and a third step of heating at a third temperature higher than the second temperature.
본 발명에 따르면, 3차례에 걸친 큐어링에 의해, SOG막이 구조적으로 무기질 상태가 되며, 특히, 구조적인 변화로 인하여, H2O의 외부 방출이 억제되기 때문에, 상기 SOG막에서의 균열은 방지되고, 이에 따라, 상기 SOG막의 평탄화 특성이 향상된다.According to the present invention, by curing three times, the SOG film becomes a structurally inorganic state, and in particular, since the external emission of H 2 O is suppressed due to the structural change, cracking in the SOG film is prevented. As a result, the planarization characteristic of the SOG film is improved.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명의 실시예에 따른 반도체 소자의 평탄화 방법을 설명하기 위한 단면도로서, 이를 설명하면 다음과 같다.2 is a cross-sectional view illustrating a planarization method of a semiconductor device in accordance with an embodiment of the present invention.
트랜지스터(도시안됨)와 같은 하부 패턴이 구비된 반도체 기판(11) 상에 제1층간절연막(12)을 형성하고, 공지된 공정을 통해, 상기 제1층간절연막(12) 상에 금속배선(13)을 형성한다. 그런다음, 상기 금속배선(13)을 덮도록, 상기 제1층간절연막(12) 상에 제2층간절연막(14)을 형성한다.A first interlayer insulating film 12 is formed on a semiconductor substrate 11 having a lower pattern such as a transistor (not shown), and a metal line 13 is formed on the first interlayer insulating film 12 through a known process. ). Then, a second interlayer insulating film 14 is formed on the first interlayer insulating film 12 so as to cover the metal wiring 13.
다음으로, 상기 제2층간절연막(14) 상에 평탄화막으로서 모노머(monomer)상태의 SOG와 솔벤트로 이루어진 SOG 용액을 도포하여 S0G막을 도포한 후, 상기 도포된 SOG막을 큐어링하여, 최종적으로, 표면 평탄화가 이루어진 SOG막(15)을 얻는다. 이때, 상기 도포된 SOG막(15)을 큐어링함에 있어서, 본 발명의 실시예에서는 상기 SOG막(15)에 함유된 H2O 성분이 외부로 방출되는 것이 방지되도록, 온도 구배를 두어 3차례에 나누어 수행한다.Next, a SOG solution composed of SOG in a monomer state and a solvent is applied onto the second interlayer insulating film 14 to apply a SOG solution, and then the applied SOG film is cured. An SOG film 15 having a surface planarized is obtained. At this time, in curing the coated SOG film 15, in the embodiment of the present invention, the temperature gradient is three times so that the H 2 O component contained in the SOG film 15 is prevented from being released to the outside. Perform divided on.
즉, 본 발명의 실시예에서는 상기 SOG(15)막을 큐어링을, 먼저, 도포된 SOG막을 100 내지 150℃ 온도에서 30 내지 60분 동안 프리베이크(prebake)하고, 그런다음, 프리베이크된 SOG막을 250 내지 350℃ 온도에서 30 내지 60분 동안 가열한 후, 그리고나서, 가열된 SOG막을 350 내지 600℃ 온도에서 30 내지 60분 동안 재차 가열한다.That is, in the embodiment of the present invention, the SOG 15 film is cured, first, the applied SOG film is prebaked at 100 to 150 ° C. for 30 to 60 minutes, and then the prebaked SOG film is After heating for 30 to 60 minutes at a temperature of 250 to 350 ° C., the heated SOG film is then heated again for 30 to 60 minutes at a temperature of 350 to 600 ° C.
이 결과, 3차례에 걸쳐 큐어링이 실시된 SOG막(15)은 구조적으로 무기질 상태가 되고, 특히, 이러한 3차례에 걸친 큐어링에 의한 구조적인 변화로, 상기 SOG막에 함유된 H2O 성분의 외부 방출이 방지되기 때문에, H2O 성분의 외부 방출에 기인된 SOG막의 균열 발생은 억제되고, 이에 따라, 상기 SOG막(15)의 평탄화 특성은 향상된다.As a result, the SOG film 15 subjected to three times of curing becomes a structurally inorganic state, and in particular, due to the structural change caused by the three times of curing, the H 2 O contained in the SOG film. Since the external emission of the component is prevented, the occurrence of cracking of the SOG film caused by the external emission of the H 2 O component is suppressed, whereby the planarization characteristic of the SOG film 15 is improved.
이상에서와 같이, 본 발명의 반도체 소자의 평탄화 방법은 SOG막의 큐어링 공정을 온도 구배를 두어 3차례에 걸쳐 나누어 수행함으로써, 균열이 없는 SOG막을 얻을 수 있으며, 이에 따라, 상기 SOG의 평탄화 효과를 증대시킬 수 있는 것에 기인하여, 반도체 소자의 제조수율 및 신뢰성을 확보할 수 있다.As described above, according to the planarization method of the semiconductor device of the present invention, the curing process of the SOG film is divided into three times with a temperature gradient, so that an SOG film without cracks can be obtained, and accordingly, the planarization effect of the SOG can be obtained. Due to being able to increase, the manufacturing yield and reliability of a semiconductor element can be ensured.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960057827A KR100272261B1 (en) | 1996-11-27 | 1996-11-27 | Planarization method of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960057827A KR100272261B1 (en) | 1996-11-27 | 1996-11-27 | Planarization method of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980038887A KR19980038887A (en) | 1998-08-17 |
| KR100272261B1 true KR100272261B1 (en) | 2000-12-01 |
Family
ID=19483728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960057827A KR100272261B1 (en) | 1996-11-27 | 1996-11-27 | Planarization method of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100272261B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100468688B1 (en) * | 1997-09-08 | 2005-05-19 | 삼성전자주식회사 | Manufacturing method of inter dielectric layer by using spin on glass layer for semiconductor device |
-
1996
- 1996-11-27 KR KR1019960057827A patent/KR100272261B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980038887A (en) | 1998-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4665007A (en) | Planarization process for organic filling of deep trenches | |
| US6261944B1 (en) | Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect | |
| US5710460A (en) | Structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric | |
| KR100272261B1 (en) | Planarization method of semiconductor | |
| JP2003068845A (en) | Semiconductor device and its manufacturing method | |
| US6239034B1 (en) | Method of manufacturing inter-metal dielectric layers for semiconductor devices | |
| JPH03246937A (en) | Manufacture of semiconductor device | |
| KR100240269B1 (en) | Method of manufacturing semiconductor device | |
| KR100212710B1 (en) | Method of manufacturing semiconductor device | |
| KR100230386B1 (en) | Formation method of inter-metal dielectric layer | |
| KR100620153B1 (en) | Method for forming inter-layer dielectrics of semiconductor device | |
| JPH0878528A (en) | Formation of wiring for semiconductor device | |
| JP3328430B2 (en) | Method for forming multilayer wiring of semiconductor device | |
| JPH0226053A (en) | Manufacture of semiconductor device | |
| KR100235954B1 (en) | A fabrication method of semiconductor device | |
| KR100260356B1 (en) | Method for forming multi metal interconnection | |
| JPH10214892A (en) | Manufacture of semiconductor device | |
| KR100244801B1 (en) | Method for manufacturing semiconductor device | |
| KR100434713B1 (en) | Method of manufacturing semiconductor device with corrosion-free metal line and defect-free via hole | |
| KR100447983B1 (en) | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE TO PREVENT CORROSION OF LOWER METAL LINE USING SiON LAYER INSTEAD OF SiO2 LAYER | |
| KR19980016862A (en) | Interlayer insulating film planarization method to prevent voids | |
| KR20070001744A (en) | Method for manufacturing inter metal dielectric layer of semiconductor device | |
| KR100652294B1 (en) | Method for forming inter-layer dielectrics of semiconductor device | |
| US20030052411A1 (en) | Semiconductor device and method for manufacturing the same | |
| KR940007067B1 (en) | Planerizing method of interlayer insulating film using sog |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080728 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |