KR19990022951A - 다중처리 시스템내의 처리기 사이에 메시지를 전송하는 장치 및방법 - Google Patents
다중처리 시스템내의 처리기 사이에 메시지를 전송하는 장치 및방법 Download PDFInfo
- Publication number
- KR19990022951A KR19990022951A KR1019970709421A KR19970709421A KR19990022951A KR 19990022951 A KR19990022951 A KR 19990022951A KR 1019970709421 A KR1019970709421 A KR 1019970709421A KR 19970709421 A KR19970709421 A KR 19970709421A KR 19990022951 A KR19990022951 A KR 19990022951A
- Authority
- KR
- South Korea
- Prior art keywords
- queue
- outgoing
- free
- incoming
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/490,651 US5925099A (en) | 1995-06-15 | 1995-06-15 | Method and apparatus for transporting messages between processors in a multiple processor system |
| US8/490,651 | 1995-06-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19990022951A true KR19990022951A (ko) | 1999-03-25 |
Family
ID=23948942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970709421A Ceased KR19990022951A (ko) | 1995-06-15 | 1996-06-17 | 다중처리 시스템내의 처리기 사이에 메시지를 전송하는 장치 및방법 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US5925099A (enExample) |
| EP (1) | EP0840935B1 (enExample) |
| JP (1) | JP3884073B2 (enExample) |
| KR (1) | KR19990022951A (enExample) |
| CN (1) | CN1099078C (enExample) |
| AU (1) | AU6180196A (enExample) |
| DE (1) | DE69636781D1 (enExample) |
| WO (1) | WO1997000533A1 (enExample) |
Families Citing this family (86)
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| WO1998040850A2 (en) * | 1997-03-13 | 1998-09-17 | Whitney Mark M | A system for, and method of, off-loading network transactions from a mainframe to an intelligent input/output device, including off-loading message queuing facilities |
| US6477584B1 (en) * | 1997-03-21 | 2002-11-05 | Lsi Logic Corporation | Message FIFO empty early warning method |
| US6105119A (en) * | 1997-04-04 | 2000-08-15 | Texas Instruments Incorporated | Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems |
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| JP4236729B2 (ja) * | 1998-05-07 | 2009-03-11 | 株式会社リコー | データ処理装置 |
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| US6173307B1 (en) * | 1998-08-20 | 2001-01-09 | Intel Corporation | Multiple-reader multiple-writer queue for a computer system |
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| US6182182B1 (en) * | 1998-10-28 | 2001-01-30 | Adaptec, Inc. | Intelligent input/output target device communication and exception handling |
| US6212543B1 (en) | 1998-12-10 | 2001-04-03 | Intel Corporation | Asymmetric write-only message queuing architecture |
| US6209054B1 (en) | 1998-12-15 | 2001-03-27 | Cisco Technology, Inc. | Reliable interrupt reception over buffered bus |
| US6256699B1 (en) * | 1998-12-15 | 2001-07-03 | Cisco Technology, Inc. | Reliable interrupt reception over buffered bus |
| US6381663B1 (en) * | 1999-03-26 | 2002-04-30 | Hewlett-Packard Company | Mechanism for implementing bus locking with a mixed architecture |
| NO312926B1 (no) * | 1999-07-20 | 2002-07-15 | Ericsson Telefon Ab L M | Kommunikasjon over multimaster buss |
| US6976260B1 (en) * | 1999-09-24 | 2005-12-13 | International Business Machines Corporation | Method and apparatus for serializing a message queue in a multiprocessing environment |
| US6772097B1 (en) * | 1999-09-30 | 2004-08-03 | Intel Corporation | Retrieving I/O processor performance monitor data |
| US6918044B1 (en) | 1999-10-15 | 2005-07-12 | Cisco Technology, Inc. | Password protection for high reliability computer systems |
| US6467049B1 (en) | 1999-10-15 | 2002-10-15 | Cisco Technology, Inc. | Method and apparatus for configuration in multi processing engine computer systems |
| US6484224B1 (en) | 1999-11-29 | 2002-11-19 | Cisco Technology Inc. | Multi-interface symmetric multiprocessor |
| US6609171B1 (en) * | 1999-12-29 | 2003-08-19 | Intel Corporation | Quad pumped bus architecture and protocol |
| US6611882B1 (en) * | 1999-12-31 | 2003-08-26 | Intel Corporation | Inbound and outbound message passing between a host processor and I/O processor local memory |
| GB2368247A (en) * | 2000-10-18 | 2002-04-24 | Power X Ltd | Method and apparatus for regulating process state control messages |
| US6988160B2 (en) * | 2001-02-12 | 2006-01-17 | P-Cube Ltd. | Method and apparatus for efficient messaging between memories across a PCI bus |
| US6836480B2 (en) * | 2001-04-20 | 2004-12-28 | International Business Machines Corporation | Data structures for efficient processing of multicast transmissions |
| US6799217B2 (en) * | 2001-06-04 | 2004-09-28 | Fujitsu Limited | Shared memory multiprocessor expansion port for multi-node systems |
| US6760817B2 (en) * | 2001-06-21 | 2004-07-06 | International Business Machines Corporation | Method and system for prefetching utilizing memory initiated prefetch write operations |
| US7454753B2 (en) * | 2001-06-27 | 2008-11-18 | International Business Machines Corporation | Semaphore management subsystem for use with multi-thread processor systems |
| US7089555B2 (en) | 2001-06-27 | 2006-08-08 | International Business Machines Corporation | Ordered semaphore management subsystem |
| US6801976B2 (en) | 2001-08-27 | 2004-10-05 | Intel Corporation | Mechanism for preserving producer-consumer ordering across an unordered interface |
| US7406690B2 (en) * | 2001-09-26 | 2008-07-29 | International Business Machines Corporation | Flow lookahead in an ordered semaphore management subsystem |
| US7143414B2 (en) | 2001-09-26 | 2006-11-28 | International Business Machines Corporation | Method and apparatus for locking multiple semaphores |
| US7054925B2 (en) * | 2001-11-21 | 2006-05-30 | International Business Machines Corporation | Efficient method for determining record based I/O on top of streaming protocols |
| US20030110232A1 (en) * | 2001-12-11 | 2003-06-12 | International Business Machines Corporation | Distributing messages between local queues representative of a common shared queue |
| US7290127B2 (en) * | 2001-12-26 | 2007-10-30 | Intel Corporation | System and method of remotely initializing a local processor |
| US6813658B2 (en) * | 2002-03-27 | 2004-11-02 | Intel Corporation | Dynamic data queuing mechanism for packet networks |
| US20040006635A1 (en) * | 2002-04-19 | 2004-01-08 | Oesterreicher Richard T. | Hybrid streaming platform |
| US20040006636A1 (en) * | 2002-04-19 | 2004-01-08 | Oesterreicher Richard T. | Optimized digital media delivery engine |
| US7899924B2 (en) * | 2002-04-19 | 2011-03-01 | Oesterreicher Richard T | Flexible streaming hardware |
| US20040107240A1 (en) * | 2002-12-02 | 2004-06-03 | Globespan Virata Incorporated | Method and system for intertask messaging between multiple processors |
| US7013355B2 (en) * | 2003-01-09 | 2006-03-14 | Micrel, Incorporated | Device and method for improved serial bus transaction using incremental address decode |
| DE102004012516A1 (de) * | 2004-03-15 | 2005-10-13 | Infineon Technologies Ag | Computersystem zur elektronischen Datenverarbeitung |
| EP1772016A2 (en) * | 2004-07-23 | 2007-04-11 | Beach Unlimited LLC | Trickmodes and speed transitions |
| US20070276973A1 (en) * | 2004-09-30 | 2007-11-29 | Intel Corporation | Managing queues |
| US8117620B2 (en) * | 2005-03-21 | 2012-02-14 | Intel Corporation | Techniques for implementing a communication channel with local and global resources |
| EP1715405A1 (en) * | 2005-04-19 | 2006-10-25 | STMicroelectronics S.r.l. | Processing method, system and computer program product for dynamic allocation of processing tasks in a multiprocessor cluster platforms with power adjustment |
| JP5188493B2 (ja) * | 2006-03-30 | 2013-04-24 | シリコン イメージ,インコーポレイテッド | 可変のポート速度を有するマルチポート・メモリ・デバイス |
| CN100538690C (zh) * | 2006-04-10 | 2009-09-09 | 中国科学院研究生院 | 一种多cpu系统及cpu之间消息传递的方法 |
| US9274859B2 (en) * | 2006-05-25 | 2016-03-01 | Nvidia Corporation | Multi processor and multi thread safe message queue with hardware assistance |
| US7818489B2 (en) * | 2006-11-04 | 2010-10-19 | Virident Systems Inc. | Integrating data from symmetric and asymmetric memory |
| US20090248919A1 (en) * | 2008-03-25 | 2009-10-01 | Jerzy Szwagrzyk | Method for external fifo acceleration |
| US8566930B2 (en) * | 2009-02-27 | 2013-10-22 | Science Applications International Corporation | Monitoring module |
| US20100262979A1 (en) * | 2009-04-08 | 2010-10-14 | Google Inc. | Circular command queues for communication between a host and a data storage device |
| US8745291B2 (en) * | 2011-10-04 | 2014-06-03 | Qualcomm Incorporated | Inter-processor communication apparatus and method |
| US10157060B2 (en) | 2011-12-29 | 2018-12-18 | Intel Corporation | Method, device and system for control signaling in a data path module of a data stream processing engine |
| US10331583B2 (en) | 2013-09-26 | 2019-06-25 | Intel Corporation | Executing distributed memory operations using processing elements connected by distributed channels |
| CN104022963B (zh) * | 2014-01-02 | 2017-06-13 | 烽火通信科技股份有限公司 | 多种通信方式并存的通信方法及装置 |
| CN107153580B (zh) * | 2016-03-04 | 2020-08-18 | 北京忆恒创源科技有限公司 | 获取队列精确状态的装置及其方法 |
| TWI588657B (zh) * | 2016-03-25 | 2017-06-21 | 晨星半導體股份有限公司 | 雙處理器系統及其控制方法 |
| US10496577B2 (en) * | 2017-02-09 | 2019-12-03 | Hewlett Packard Enterprise Development Lp | Distribution of master device tasks among bus queues |
| CN108664335B (zh) * | 2017-04-01 | 2020-06-30 | 北京忆芯科技有限公司 | 通过代理进行队列通信的方法与装置 |
| US11086816B2 (en) | 2017-09-28 | 2021-08-10 | Intel Corporation | Processors, methods, and systems for debugging a configurable spatial accelerator |
| US10528077B2 (en) * | 2017-11-21 | 2020-01-07 | The Boeing Company | Instruction processing alignment system |
| US11307873B2 (en) | 2018-04-03 | 2022-04-19 | Intel Corporation | Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging |
| US10891240B2 (en) | 2018-06-30 | 2021-01-12 | Intel Corporation | Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator |
| US10853073B2 (en) | 2018-06-30 | 2020-12-01 | Intel Corporation | Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator |
| US11200186B2 (en) | 2018-06-30 | 2021-12-14 | Intel Corporation | Apparatuses, methods, and systems for operations in a configurable spatial accelerator |
| CN109491948B (zh) * | 2018-11-19 | 2021-10-29 | 郑州云海信息技术有限公司 | 一种针对固态硬盘双端口的数据处理方法和装置 |
| US11030144B2 (en) * | 2018-12-14 | 2021-06-08 | Texas Instruments Incorporated | Peripheral component interconnect (PCI) backplane connectivity system on chip (SoC) |
| US11016684B1 (en) * | 2018-12-28 | 2021-05-25 | Virtuozzo International Gmbh | System and method for managing data and metadata where respective backing block devices are accessed based on whether request indicator indicates the data or the metadata and accessing the backing block devices without file system when the request indicator is not included in request |
| CN109918024B (zh) * | 2019-02-28 | 2022-07-05 | 深圳和而泰数据资源与云技术有限公司 | 存储管理方法、装置、单片机设备和可读存储介质 |
| US10915471B2 (en) | 2019-03-30 | 2021-02-09 | Intel Corporation | Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator |
| US10817291B2 (en) | 2019-03-30 | 2020-10-27 | Intel Corporation | Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator |
| US11037050B2 (en) | 2019-06-29 | 2021-06-15 | Intel Corporation | Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator |
| CN111314244B (zh) * | 2020-02-13 | 2022-09-13 | 北京天拓智领科技有限公司 | 一种基于消息队列的数据收发方法 |
| US12086080B2 (en) | 2020-09-26 | 2024-09-10 | Intel Corporation | Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4445176A (en) * | 1979-12-28 | 1984-04-24 | International Business Machines Corporation | Block transfers of information in data processing networks |
| US4682284A (en) * | 1984-12-06 | 1987-07-21 | American Telephone & Telegraph Co., At&T Bell Lab. | Queue administration method and apparatus |
| US4914653A (en) * | 1986-12-22 | 1990-04-03 | American Telephone And Telegraph Company | Inter-processor communication protocol |
| US4956771A (en) * | 1988-05-24 | 1990-09-11 | Prime Computer, Inc. | Method for inter-processor data transfer |
| EP0365731B1 (en) * | 1988-10-28 | 1994-07-27 | International Business Machines Corporation | Method and apparatus for transferring messages between source and destination users through a shared memory |
| US5161156A (en) * | 1990-02-02 | 1992-11-03 | International Business Machines Corporation | Multiprocessing packet switching connection system having provision for error correction and recovery |
| US5459839A (en) * | 1991-09-05 | 1995-10-17 | International Business Machines Corporation | System and method for managing queue read and write pointers |
| US5428766A (en) * | 1992-12-01 | 1995-06-27 | Digital Equipment Corporation | Error detection scheme in a multiprocessor environment |
| US5581705A (en) * | 1993-12-13 | 1996-12-03 | Cray Research, Inc. | Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system |
| US5619687A (en) * | 1994-02-22 | 1997-04-08 | Motorola Inc. | Queue system having a time-out feature and method therefor |
| US5530933A (en) * | 1994-02-24 | 1996-06-25 | Hewlett-Packard Company | Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus |
| US5546546A (en) * | 1994-05-20 | 1996-08-13 | Intel Corporation | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
| US5925099A (en) * | 1995-06-15 | 1999-07-20 | Intel Corporation | Method and apparatus for transporting messages between processors in a multiple processor system |
-
1995
- 1995-06-15 US US08/490,651 patent/US5925099A/en not_active Expired - Lifetime
-
1996
- 1996-06-17 JP JP50339997A patent/JP3884073B2/ja not_active Expired - Fee Related
- 1996-06-17 AU AU61801/96A patent/AU6180196A/en not_active Abandoned
- 1996-06-17 KR KR1019970709421A patent/KR19990022951A/ko not_active Ceased
- 1996-06-17 EP EP96919466A patent/EP0840935B1/en not_active Expired - Lifetime
- 1996-06-17 DE DE69636781T patent/DE69636781D1/de not_active Expired - Lifetime
- 1996-06-17 WO PCT/US1996/010466 patent/WO1997000533A1/en not_active Ceased
- 1996-06-17 CN CN96196279A patent/CN1099078C/zh not_active Expired - Fee Related
-
1999
- 1999-06-03 US US09/324,744 patent/US6134619A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO1997000533A1 (en) | 1997-01-03 |
| EP0840935B1 (en) | 2006-12-20 |
| DE69636781D1 (de) | 2007-02-01 |
| JP3884073B2 (ja) | 2007-02-21 |
| CN1099078C (zh) | 2003-01-15 |
| CN1193410A (zh) | 1998-09-16 |
| EP0840935A1 (en) | 1998-05-13 |
| JPH11514113A (ja) | 1999-11-30 |
| HK1010940A1 (en) | 1999-07-02 |
| EP0840935A4 (en) | 1998-12-23 |
| AU6180196A (en) | 1997-01-15 |
| US5925099A (en) | 1999-07-20 |
| US6134619A (en) | 2000-10-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0105 | International application |
Patent event date: 19971215 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19971215 Comment text: Request for Examination of Application |
|
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20000228 Patent event code: PE09021S01D |
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| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20000525 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20000228 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |