KR19990021785A - Linear Synchronous Pulse Phase Shifter of Camera - Google Patents

Abstract

The present invention digitally implements functions of temperature sensitive elements such as monostable multivibrators, variable resistors, resistors, and capacitors in a synchronous pulse phase variable circuit synchronized with a power supply frequency to change phases due to temperature of various line lock pulses. It relates to a linear synchronous pulse phase shifter of a camera to remove the. The linear synchronous pulse phase shifter of the camera of the present invention comprises: means for providing a pulse synchronized with a power frequency; Means for providing a clock pulse having a predetermined frequency; Means for providing a desired phase control value of the sync pulse within a predetermined range; And means for delaying the phase of the sync pulse for a time period obtained by multiplying the provided phase control value by one period of the clock pulse.

Description

Linear Synchronous Pulse Phase Shifter of Camera

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear synchronous pulse phase shifter of a camera, and in particular, by digitally varying the phase of a synchronous signal used in a line lock system, which is one of the methods of vertical synchronization simultaneously when using multiple surveillance cameras. The present invention relates to a linear synchronous pulse phase shifter of a camera that can correct an image distortion between each other.

When only the power is connected in a system that operates multiple surveillance cameras such as a closed circuit TV system, each camera operates independently. Accordingly, the synchronization signals included in the video signals output from these cameras are controlled. Phase and frequency are also different and operate without correlation.

However, when the signals of the cameras are displayed at the same time by dividing one monitor screen, independent movement of the synchronization signal may be a problem. That is, the screen may be crushed, shifted in phase, or splashed.

In order to solve this problem, an apparatus for generating a specific reference signal from the outside and adjusting the oscillation frequency or phase of the internal pulse of the camera so that the synchronization signals of all the connected cameras meet the reference signal is required. Among these devices, there is a simple locking technology applied to low-cost products such as kemares used in closed circuit TV systems, such as line lock, which uses a power signal as an external reference signal. Doing. In general, NTSC (National Television System Committee) uses 60 (Hz) as the power frequency. In line lock, this power frequency is similar to the vertical sync signal frequency of the video signal. The clock frequency and phase of the pulse generator are interrupted so that the frequency is 60 Hz.

1 is a block diagram showing the overall configuration of a line lock system of a conventional camera. As shown in Fig. 1, in most analog cameras employing the line lock function, a monostable multivibrator is generated after a synchronization pulse SA2 of a TTL level is synchronized using a 60 power supply frequency. Enter in (1). The pulse SA2 input as described above is a pulse whose width and phase are adjusted by resistors R1, R2, variable resistor VR1, capacitors C1, and C2 connected to the monostable multivibrator 1. It becomes (SA1) and is input to the phase comparator 11 of the PLL (Phase Loop Lock) circuit part 10. FIG.

Next, the phase comparator 11 compares the input pulse SA3 with the vertical driving pulse VD of the camera and outputs a signal SA4 according to the phase difference, and the integrator 12 outputs the output signal ( DC is applied to the voltage controlled oscillator (Voltage Controlled Oscillator, hereinafter referred to as VCO) 13. The VCO 13 generates the necessary center pulse SA5 throughout the camera. The pulse generator 14 uses the pulse SA5 to generate various pulses including the vertical driving pulse VD, and among these pulses, The vertical driving pulse VD is fed back to the phase comparator 11 to form a repeating loop of the PLL.

The vertical drive pulse VD produced by the above-described configuration is synchronized to 60 kHz, which is an external power supply frequency, but the line lock is not completed by itself. In a system where several cameras are linelocked at the same time, when only vertical synchronization is achieved, deviations may occur in the vertical phase between the cameras. In this case, when two or more cameras are switched to an indicator such as a monitor while the deviation occurs, the screen shakes during switching. In the above-described configuration, the variable resistor VR1 is prepared for such a case, so that the phase of the vertical driving pulse VD can be adjusted by varying the phase of the pulse SA3, resulting in vertical driving of another camera. This can be matched with the phase of the pulse VD.

However, since the width required to vary the phase is so large that it is a number (msec) to a decade (msec), the capacity of the resistor, capacitor, and variable resistor for determining the phase width is increased. According to the change in the internal environment of the capacitor, the fluctuation range of the capacitance, such as the capacitor is also increased, the phase of the reference pulse and the vertical driving pulse fluctuate, there was a problem that the phase difference between the video signal of the cameras again.

Moreover, in the case of surveillance cameras, since they are usually installed at a high position, there is an inconvenience of using a specially made tool to adjust the variable resistance. As a result, there has been a problem in that it cannot cope with the current trend of camera technology such as digitalization of image signal processing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and digitally implements the functions of temperature-sensitive devices such as monostable multivibrators, variable resistors, resistors, and capacitors in a synchronous pulse phase variable circuit synchronized with power frequency. It is therefore an object of the present invention to provide a linear synchronous pulse phase shifter of a camera capable of eliminating phase changes due to the temperature of various line lock pulses.

Another object of the present invention is to adjust the phase fluctuation range of the line lock pulse by floating the OSD (On Screen Display) on the display using a microprocessor or the like, thereby eliminating the inconvenience of adjustment. To provide a variable device.

In accordance with another aspect of the present invention, there is provided a linear synchronous pulse phase shifter of a camera, comprising: means for providing a pulse synchronized with a power source frequency; Means for providing a clock pulse having a predetermined frequency; Means for providing a desired phase control value of the sync pulse within a predetermined range; And means for delaying the phase of the sync pulse for a time period obtained by multiplying the provided phase control value by one period of the clock pulse.

In the above-described configuration, the phase delay means includes: a reset pulse generator for generating a preset pulse and a reset pulse whose widths correspond to one period of the clock pulse in the vicinity of the rising edge and the falling edge of the synchronization pulse; A first variable modulo counter for outputting a pulse that is in a 'high' state only for one time of the clock pulse multiplied by the phase control value from a time point at which the ionization pulse is input; a time point at which the reset pulse is input Process the phase of the second variable modulo counter and the output of the first and second variable modulo counters to generate a pulse that becomes 'High' only for a period of time multiplied by the phase control value by one period of the clock pulse. It consists of a pulse output section for outputting a delayed sync pulse.

1 is a block diagram showing the overall configuration of a line lock system of a conventional camera;

Figure 2 is a block diagram showing a linear synchronous pulse phase variable device of the camera of the present invention,

3 is a detailed circuit diagram of FIG.

4 is an output waveform diagram in the main part of FIG.

Explanation of symbols on the main parts of the drawings

1: monostable multivibrator 10: PLL circuit section

11: phase comparator 12: integrator

13: voltage controlled oscillator 14: pulse generator

20: reset pulse generator 30, 40: modulo counter

50: line lock pulse output unit

R1, R2: resistors C1, C2: capacitors

VR: Variable resistor

INV1-INV5: Inverter AND: End Gate

EX1-EX3: Exclusive Ora GateNOR1-NOR16: Exclusive Noah Gate

CNT1, CNT2: Modulos counterFF1-FF4: Flip-flop

NAND1, NAND2: NAND Gate

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the linear synchronous pulse phase variable device of the camera of the present invention.

2 is a block diagram schematically showing a linear synchronous pulse phase variable device of the camera of the present invention.

First, the linear synchronous pulse phase variable apparatus of the camera of the present invention has a means for providing a pulse largely synchronized with a power supply frequency, a means for providing a clock pulse having a predetermined frequency, a desired phase control value of the synchronous pulse within a predetermined range. And means for delaying the phase of the sync pulse for a period of time by multiplying the provided phase control value by one period of the clock pulse.

In the above-described configuration, the clock pulse can be used as it is or appropriately divided by the clock used for synchronizing in the camera itself. Furthermore, the phase control value may be provided with means for inputting a control value to the outside of the camera, and the control value provided through the input means may be processed by a microprocessor provided in the camera itself to be transmitted to the phase delay means. In addition, in the case of a camera capable of OSD processing, the manipulation amount of these control values may be configured to be processed while viewing the screen.

As shown in Fig. 2, the phase delay means includes a reset pulse RP1 and a reset corresponding to one cycle of the clock pulse CLK in the vicinity of the rising edge and the falling edge of the 60-second synchronous pulse. The reset pulse generator 20 that generates the pulse RP2 and the high time only when the phase control value CO-C7 is multiplied by one period of the clock pulse CLK from the time when the reset pulse RP1 is input. The phase control value C0-C7 is set in one cycle of the clock pulse CLK from the time when the first variable modulo counter 30 and the reset pulse RP2 are outputted. Outputs SB1 of the second variable modulo counters 40 and the first and second variable modulo counters 30 and 40 for generating the pulse SB4 which becomes the 'High' state only during the multiplication time. And a pulse output unit 50 for processing the SB4) to output the phase delayed synchronous pulse LLP.

3 is a detailed circuit diagram of the linear synchronous pulse phase shifter of the camera of the present invention shown in FIG. As shown in FIG. 3, the reset pulse generator 20 sets the T-flip flop FF3 and the output F1 of the T-flip flop FF3, which divide the synchronization pulse into two, one clock cycle and two clocks, respectively. The output L1 and L2 of two cascaded D-flip-flops (FF4), (FF5), D-flip-flop (FF4), and (FF5) to be sequentially delayed by period. The exclusive OR gate EX2 for processing and outputting the reset pulse RP1 having one clock period CLK near the rising edge of the sync pulse, to the inverter gate INV4 and inverter gate INV4 for inverting the sync pulse. Two cascaded connections to sequentially delay the output of the T-flip flop (FF6) and the T-flip flop (FF6) that divide the inverted sync pulse by two by one clock period and two clock periods, respectively. D-Flip-Flops (FF7), (FF8) and D-Flip-Flops (FF7), (FF8) Output L3, (L4) are processed with exclusive OR logic to lower the sync pulse Exclusive oar gate EX3 for outputting the reset pulse RP2 having one clock period near the edge. In the above configuration, the 'high' signal is always input to the toggle terminals T of the respective T-flip flops FF3 and FF6.

The first modulo counter 30 has its contents reset by the reset pulse RP1, and when disabled, a predetermined bit, preferably an 8-bit parallel counter CNT1, which retains the counted contents as it is, Eight exclusive Noah gates (NOR1-NOR8) and respective exclusive Noah gates that process the output bit values Q0-Q7 of the counter CNT1 and the corresponding bits of the external phase control value C0-C7, respectively, with exclusive NOR logic. It consists of a NAND gate NAND1 which processes the output of (NOR1-NOR8) by NAND logic.

The second modulo counter 40 has its contents reset by the reset pulse RP2, and when disabled, a predetermined bit, preferably an 8-bit parallel counter CNT2, which retains the counted contents as it is, Eight exclusive NOR gates NOR9NOR16 and each exclusive NOR gate NOR9 each of which processes the output bit values Q0-Q7 of the counter CNT2 and the corresponding bits of the external phase control value C0-C7 with exclusive NOR logic, respectively. A NAND gate NAND2 which processes the output of NOR16 with NAND logic.

The pulse output unit 50 outputs inverter gates INV1, INV2, inverter gates INV1, and INV2 that invert the outputs SB1 and SB4 of the NAND gates NAND1 and NAND2, respectively. Outputs of two T-flip-flops FF1, FF2, and T-flip-flops FF1, FF2 that output two-divided signals with (SB2) and (SB5) as clocks, respectively, It consists of an exclusive oar gate EX1 which processes SB6 as an exclusive oar logic. In the above configuration, the 'high' signal is always input to the toggle terminals T of the respective T-flip flops FF1 and FF2. In addition to the pulse output unit 50, the output of the inverter gate INV3 and the inverter gate INV3 and the reset pulse RP1 that invert the state of the output SB3 of the T-flip flop FF1 are processed by AND logic. The AND gate AND is further provided, wherein the T-flip flop FF1 is reset when the camera is turned on, and the T-flip flop FF2 is reset by the output RP3 of the AND gate AND. Is set.

Hereinafter, the operation of the linear synchronous pulse phase variable device of the camera of the present invention will be described in detail.

4 is an output waveform diagram in the main part of FIG. As shown in Fig. 4, the reset pulse generator 20 divides the synchronization pulse synchronized with the power supply frequency 60 Hz by passing through the flip-flop FF3 to divide the frequency 30 Hz and 50% duty. Branches make a pulse F1. Next, the synchronous pulse is inverted through the inverter gate INV4 and then passed through the flip-flop FF6 to be divided into two to generate a pulse F2 having a frequency of 30 kHz and a 50% duty. Accordingly, the pulses F1 and F2 have a phase difference equal to the duty of the positive pulses.

Next, when the pulse F1 passes through the flip-flop FF4 and the flip-flop FF5 sequentially, the signal L1 is delayed by one cycle of the clock pulse CLK and the signal L2 is delayed by two cycles. When the delayed signals L1 and L2 pass through the exclusive OR gate EX2, a pulse RP1 having a width δt of one cycle of the clock pulse CLK near the rising edge of the synchronization pulse is obtained. You lose.

Similarly, when the pulse F2 passes through the flip-flop FF7 and the flip-flop FF8 sequentially, the signal L3 is delayed by one cycle of the clock pulse CLK and the signal L4 is delayed by two cycles. When the delayed signals L3 and L4 pass through the exclusive OR gate EX3, a pulse RP2 having a width δt of one cycle of the clock pulse CLK is obtained near the falling edge of the synchronization field. You lose.

The counters CNT1 and CNT2, which are 8-bit counters, count when the state of the enable terminal EN is 'High' and stop counting in that state when the low level is 'Low'. (Q0-Q7) will maintain the state when it stopped. When the reset pulse RP1 is input to the counter CNT1, the output values Q1-Q7 and the control values C0-C7 are different so that the output signal SB1 of the NAND gate AND1 is 'High'. As a result, the counter CNT1 counts again. When the counter CNT1 counts and the output value Q0-Q7 becomes equal to the control value C0-C7, the signal SB1 is inverted to a 'low' state to disable the counter CNT1. Until the reset pulse RP is input, the output value Q0-Q7 and the control value C0-C7 of the counter CNT1 remain the same, but the width of the signal SB1 is to be delayed. Corresponds to time.

On the other hand, when the signal SB2 obtained by inverting the signal SB1 is input to the flip-flop FF1, the signal SB3 having a duty of 50% is produced at the output thereof. Subsequently, when the reset pulse RP2 is input to the counter CNT2, the output value Q1-Q7 and the control value C0-C7 of the counter CNT2 are different from each other so that the signal SB4 output from the NAND gate NAND2 is generated. In the High state, the counter CNT2 starts counting. In this way, if the output value Q0-Q7 becomes equal to the control value C0-C7 while the counter CNT2 is counting, the output signal SB4 of the NAND gate NAND2 becomes 'Low' state and the counter ( CNT2) is disabled. Next, the counter CNT2 maintains the same state as the output value Q0-Q7 and the control value C0-C7 until the reset pulse RP2 is input. Here, the pulse width of the signal SB4 corresponds to the time to be delayed.

On the other hand, if the signal SB4 is inverted by the inverter gate INV2, a signal SB5 is obtained. When the signal SB5 is inputted to the flip-flop FF2, a signal SB6 having a duty of 50% at its output is generated. Is made. The timing relationship between the signal SB3 and the signal SB6 made by the above-described process is as shown in Fig. 4, and the phase difference between these two signals SB3 and SB6 is the positive duty width δa of the sync pulse. ) Is equal to the time obtained by subtracting the error time by one period period δt of the maximum clock pulse CLK.

Next, when the signal SB3 and the signal SB6 thus produced are processed by the exclusive OR gate EX1, a line lock pulse LLP is finally obtained. The line lock pulse LLP is formed by the clock pulse CLK. Corresponding to the pulse obtained by delaying the sync pulse by adding a slight error to the period obtained by multiplying the time width δt by the control values C0-C7. As described above, the error time is generated because the sync pulse does not exactly match the clock pulse CLK, and the maximum value thereof is delayed by one cycle period δt of the clock pulse CLK. It is small compared to the time (δt * control value) and can be ignored.

In this way, the phase-locked line lock pulse LLP is then provided to the existing PLL circuitry and used to lock the phase of the sync pulse.

The linear synchronous pulse phase variable apparatus of the camera of the present invention is not limited to the above-described embodiment, and may be variously modified and implemented within the range permitted by the technical idea of the present invention.

According to the linear synchronous pulse phase variable apparatus of the camera of the present invention as described above, it is possible to prevent the characteristic change of the vertical synchronizing signal caused by the temperature change that occurred in the conventional analog type phase variable apparatus, The line lock phase adjustment by the variable resistor is performed on the basis of constant numerical data, so that it can be easily adjusted using a microprocessor or the like.

Furthermore, by making the entire processing into a single chip through the application specific integrated circuit (ASIC) of digital logic devices, the manufacturing cost and the number of parts can be reduced, thereby improving the reliability and productivity. have.

Claims (8)

Means for providing a pulse synchronized with a power supply frequency; Means for providing a clock pulse having a predetermined frequency; Means for providing a desired phase control value of the sync pulse within a predetermined range; And And a means for delaying the phase of said sync pulse for a time period obtained by multiplying said provided phase control value by one period of said clock pulse. The method of claim 1, wherein the phase delay means A reset pulse generator for generating an ionizing pulse and a reset pulse whose widths correspond to one period of the clock pulse in the vicinity of the rising edge and the falling edge of the synchronization pulse; A first variable modulo counter for outputting a pulse that is in a 'High' state only for a period of time when the ionization pulse is input by multiplying the phase control value by one period of the clock pulse; A second variable modulo counter for generating a pulse that becomes 'High' only for a period of time from which the preset pulse is input by multiplying the phase control value by one period of the clock pulse; And And a pulse output unit configured to process the outputs of the first and second variable modulo counters to output a phase delayed synchronous pulse. The method of claim 2, wherein the reset pulse generating unit The sync pulse is divided into two first T-flip flops; First and second D-flip flops that delay the output of the first T-flip flop aberration by one clock period and two clock periods, respectively; A first exclusive OR gate processing the outputs of the first and second D flip-flops with exclusive OR logic to output the ionizing pulse having the one clock period near the rising edge of the sync pulse; An inverter gate for inverting the sync pulse; A second T-flip flop that divides the inverted sync pulse into two; Third and fourth D-flip flops that sequentially delay the output of the second T-flip flop by one clock period and two clock periods, respectively; And And a second exclusive oar gate configured to process the outputs of the third and fourth D-flip flops with an exclusive oar logic to output the reset pulse having one clock period near the falling edge of the synchronous pulse. Linear synchronous pulse phase shifter of the camera. The method of claim 2 or 3, wherein the first modulo counter A predetermined bit counter for resetting the contents by the ionization pulse and maintaining the counted contents as it is when disabled; A first group of exclusive NOR gates for processing the output bit value of the counter and the corresponding bit value of the control value with exclusive NOR logic, respectively; And And a first NAND gate for processing the output of each exclusive NOR gate of the first group by NAND logic. The method of claim 4, wherein the second modulo counter A predetermined bit counter which resets its contents by the reset pulse and maintains the counted contents as it is when disabled; A second group of exclusive NOR gates for processing the output bit value of the counter and the corresponding bit value of the control value with exclusive NOR logic, respectively; And And a second NAND gate for processing the output of each exclusive NOR gate of the second group by NAND logic. The method of claim 4, wherein the pulse output unit First and second inverter gates inverting outputs of the first NAND gate and the second NAND gate, respectively; Fifth and sixth T-flip flops for outputting two divided signals using the outputs of the first and second inverter gates as clocks, respectively; And And an exclusive ora gate for processing the outputs of the fifth and sixth T-flip-flops with exclusive ora logic. The method of claim 6, wherein the pulse output unit A third inverter gate inverting the output of the fifth T-flip flop; And an AND gate for processing the output of the third inverter gate and the ionization pulse with AND logic, The fifth T-flip-flop is reset when the camera is powered on, And the sixth T-flip-flop is reset by the output of the AND gate. 3. The apparatus of claim 2, wherein the first and second counters are 8-bit parallel counters.