KR19990021771A - Digital signal processor - Google Patents

Abstract

The present invention relates to a DSP that can process data quickly by preventing time consumption during rounding of the data.

The DSP includes data input means for inputting N bits of data, rounding bit adding means for adding r-bit rounding bits smaller than N to N-bit data from the data input means, and high-order data of the rounding bit adding means. Guard bit adding means for adding g-bit guard bits to bits, arithmetic means for computing data from guard bit adding means, rounding / saturation processing means for saturating and rounding data from arithmetic means, and arithmetic operations; Rounding means for rounding the data from the means.

Description

Digital signal processor

The present invention relates to a digital signal processor (hereinafter referred to as a DSP) for processing various digital signals by software.

DSPs are a type of central processing unit (CPU) with arithmetic functions, originally developed by Texas Instruments, a US electronics company. This DSP has recently been applied to the processing of video and audio signals, and its use is increasing rapidly. In particular, among various processing methods of audio signals, Musicam, an audio compression algorithm established by MPEG (Moving Picture Expert Group) as an international standard, and AC-3, a digital audio compression and restoration algorithm of Dolby, etc. The DSPs that implement this are emerging rapidly. As a result, many of the world's leading companies, particularly in the West, are spurring the development of their own DSPs to increase their profits.

The DSP for audio signal processing has a longer word length for internal operation compared to T1's fixed-point DSP, which has been commonly used up to now. For example, the T1's TMS320C5x series of DSPs have a 16-bit data word length and a 32-bit Arithmatic Logic Unit (ALU), while MPEG's Musiccam and Dolby's AC Most recent DSPs developed to implement -3 have a data word length of more than 20 bits and an ALU of more than 48 bits. More specifically, Yamaha's YSS243, Motorola's DSP5600x, Crystal Semiconductor's CS2923 and Medianix Semiconductor's MED25201 are all Dolby's AC- A 56-bit ALU of 24-bit data word length is provided to decode an audio signal of 3. In addition, DSPs such as Zoran's ZR3800 and Fujitsu's MB86342 all have 20-bit data word lengths and 48-bit ALUs to decode Dolby's AC-3 audio signals.

The DSPs configured as described above operate two data having a length of N bits as shown in FIG. The first and second data 10, 12 are read from the memory and multiplied by a multiplier to generate third data that is the result of the multiplication. The first and second data 10, 12 both have a length of N bits and are composed of an integer part and a fractional part. The third data 14, which is a multiplication result of the multiplier, may have a maximum length of 2N bits, and is thus temporarily stored in a 2N bit multiplication register. Subsequently, the third data 14 is shifted by the barrel shifter by the number of bits of the integer part of the first and second data 10 and 12, for example, R bits, and thus the shift result is 2N. The fourth data 16 of the bit is calculated. The fourth data 16 is logically operated by the ALU to generate the fifth data 18. Overflow may occur in the fifth data 18 that is an operation result of the ALU. To deal with this overflow, the fifth data 18 is saturated in a DSP such as TMS320C5x of T1. In detail, when the fifth data 18 calculated by the ALU has a bit length that is difficult to be stored in the 2N bit accumulation register, that is, when the overflow occurs in the fifth data 18, the DSP of the TMS320C5x is generated. By saturating the five data 18 and storing the saturated fifth data 18 in the accumulation register, an error due to overflow is alleviated. In contrast, DSPs, such as Motorola's DSP5600x, add 8 bits to the accumulator register for overflow protection, as shown in FIG. In this case, both the ALU and the accumulation register have a length of 8 + 2N bits. Applying this overflow protection bit to the above-mentioned AC-3 dedicated DSPs, DSPs with 24-bit data word length have 56-bit accumulator and 20-bit data word length because the data is N = 24 bits. DSPs each contain 48 bits of accumulator because the data is N = 20 bits. The fifth data 18 to which the overflow protection bits are added is converted into sixth data 20 having the same bit length as the first and second data 10 and 12 stored in the memory by being saturated.

In order to perform the above series of operations, most DSPs had to have ALUs and cumulative registers having a large word length of 48 bits or more. These ALUs and accumulators, which have large word lengths of 48 bits or more, increase the die size on the DSP chip and increase the amount of propagation delay in the ALU. Therefore, the ALU and accumulator having a large word length not only increases the manufacturing cost of the DSP chip but also acts as a factor of decreasing the operation speed of the DSP.

Most DSPs support rounding operations before saturating the data. For example, Motorola's DSP converts 8 + 2N bits of data stored in the accumulator register into 8 + N bits of data by the rnd instruction. This rounded data is finally saturated with N bits of data and then stored in memory. For these rounding operations, most DSPs consume an additional instruction or clock period. This instruction or clock cycle consumes a lot of additional clock cycles when the rounding operation is applied to a code segment to which looping or block repeating is applied. This is greatly increased.

In addition, DSPs such as T1's TMS320C5x use a pre-scaling shifter located in front of the ALU to shift the binary data to be computed in the ALU to the left from 0 to 16 bits. At this time, the shift operation from the 0th bit to the 15th bit is generally used to scale binary data, but the shift operation up to the 16th bit is performed when a fixed point operation is performed instead of an integer operation. Used for This is because in the case of fixed-point arithmetic, 16-bit data read from memory must be aligned with the upper bits of the 32-bit accumulation register. Shift operations from the 0th bit to the 15th bit for scaling data may or may not be usefully used depending on a given algorithm, particularly depending on a coding scheme. When performing algorithms implemented in code where prescaling is not useful, the scaling shifter increases the DSP chip die size and increases propagation delay without much help. For example, the pre-scaling shifter included in Motorola's DSP is to shift data one bit to the left or to the right. Instead, Motorola's DSP provides different multiply instructions for floating-point and integer arithmetic, absorbing the T1's TMS3200C5x shifting data left by 16 bits.

Next, in DSP, it is important to know how fast each instruction can be executed. For fast execution of instructions, the period of instructions applied to the DSP should be shortened and as many instructions as possible should be processed in parallel. Shortening the former instruction cycle is a hardware-, circuit-related problem that shortens the circuit path by eliminating unnecessary blocks (e.g., the pre-scaling shifters already mentioned) possible in the DSP. The parallelism of the latter instruction comes from the fact that DSPs are used for video / audio decoding, which requires a lot of computation, and the sequential instruction execution method of the past does not have the necessary computational capability. Therefore, DSPs are equipped with special instructions capable of parallel processing. For example, the DSP21020, an analog device DSP, has special instructions for performing multiple complex expressions in a few clock cycles, such as a butterfly operation for FFT operations. To this end, the ADSP21020 has a register file consisting of at least 12 registers associated with the operation. Zoran's ZR38000 also performs many complex equations, such as butterfly for FFT, in just a few clock cycles. To this end, the ZR38000 has a register file consisting of eight registers and a structure that performs multiplication and addition and subtraction of the result in one clock cycle.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DSP capable of processing data quickly by preventing time consumption during rounding of data.

It is still another object of the present invention to provide a DSP capable of performing an operation including a scale of a logic value at a high speed.

1 is a diagram schematically showing a signal processing procedure of a conventional DSP.

2 is a block diagram of a DSP in accordance with an embodiment of the present invention.

FIG. 3 shows a part where rounding of data in FIG. 2 is performed;

Explanation of symbols for main parts of the drawings

30,40,44,48,64,66,76,78: first through eighth registers

32, 34, 82, 84: first to fourth bit sorter 38: guard bit adder

36,42,52,54,56,62,68,70,74,80,88: first to eleventh multiplexers

46: multiplier 38: beat controller

58,72: first and second ALU60: barrel shifter

86: rounding / saturation processor

In order to achieve the above object, the DSP according to the present invention is a data input means for inputting N bits of data, and a rounding bit addition means for adding a round bit of r bits smaller than N to N bit data from the data input means. Guard bit adding means for adding g-bit guard bits to the upper bits of the data from the rounding bit adding means, computing means for calculating data from the guard bit adding means, saturation processing of data from the computing means, Rounding / saturation processing means for rounding, and rounding means for rounding data from the calculation means.

The DSP according to the present invention includes data input means for inputting N bits of data, rounding bit addition means for adding r-bit rounding bits smaller than N to N-bit data from the data input means, and rounding bit addition means. A guard bit adding means for adding a g bit guard bit to an upper bit of the data of the data, temporarily storing the data from the guard bit adding means and the data from the feedback loop and the data from the operation logic means. A memory coupled to the feedback loop, scaling means for scaling data from guardbit adding means, selection means for selectively transferring data from the scaling means and data from the arithmetic logic means to the memory, and data from the memory; Rounding and saturating means for saturating and rounding And a rounding means for rounding the data from Li.

Other objects and advantages of the present invention other than the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to Figures 2 and 3 attached to an embodiment of the present invention will be described in detail.

Referring to FIG. 2, a first register 30 for inputting N bits of data from the first external bus 31 to the first external bus 31, and a first connected in parallel with the first register 30. A DSP according to an embodiment of the present invention having first and second bit aligners 32 and 34 is shown. The first external bus 31 is composed of N data lines commonly connected to a working memory (not shown), and is used as an N-bit first read data bus. The first register 30 temporarily stores N bits of data from the memory via the first external bus 31. The first and second bit sorters 32 and 34 serve to extend data from N bits to N + r bits by shifting N bits of data from the first register 30. In detail, the first bit sorter 32 shifts N bits of data to the left by r bits for fixed-point arithmetic. To this end, the first bit sorter 32 includes N-bit output lines of the first register 30 of the upper N input terminals of the first input port including N + r terminals of the first multiplexer 36. Wiring to be connected to each other. The second bit sorter 34 shifts the r bits right of the N bits of data for integer arithmetic. At this time, the upper r bits may be filled as sine (positive or negative) bits or filled with values of zero depending on the DSP's Sign-Extension Mode. To this end, the second bit sorter 34 includes N-bit output lines of the N-bit output lines of the first multiplexer 36 of the N input terminals of the N-bit output lines of the first register 30. Wiring to be connected to each other. The upper r bits are filled with either Sign bit or 0 as mentioned above. The first multiplexer 36 receives N + r bits of data on the first input port or N + r bits of data on the second input port according to the type of operation, that is, fixed-point / integer operation. ) Is supplied to the adder 38. This first guard bit adder 38 adds g bits of guard bits to the N + r bits of data from the first multiplexer 36. The gbit guard bits are either all set to zero or they extend the sign of the data. In detail, all g-bit guard bits have the same logic value as the sign bit of data when the sign-extension mode is set, and all logic values of 0 when the sign-extension mode is reset. The sign-extension mode is set or reset by a particular instruction. In order to add these g-bit guard bits to the N + r bit data, the first guard bit adder 38 connects the output port of the first multiplexer 36 consisting of N + r terminals to the first internal bus. The wirings are connected to the lower N + r lines among the g + N + r lines included in (35).

The DSP adds a second register 40 and a multiplier 46 connected in series to the first external bus 31 and a second multiplexer 42 connected to the first and second external buses 31 and 33. It is provided with. Like the first register 30, the second register 40 temporarily stores N-bit data from the memory input via the first external bus 31. The second external bus 33 is composed of N lines commonly connected to a program memory and a CPU (not shown) and is used as a second read-only data bus. The second multiplexer 42 includes N bit data from the first external bus 31 supplied to its first input port and N bit data from the second external bus 33 supplied to its second input port. One data is supplied to the third register 44. The third register 44 temporarily stores N-bit data from the second multiplexer 42. Multiplier 46 multiplies two data stored in second and third registers 40 and 44. The result multiplied by this multiplier 46 may have 2N bits. Accordingly, the fourth register 48 which temporarily stores data from the multiplier 46 has a length of 2N bits. The wiring controller 50 connected between the fourth register 48 and the second internal bus 37 converts 2N bits of data stored in the fourth register 48 into N + r bits of data smaller than 2N. A g-bit guard bit is added to the converted N + r-bit data.

The DSP includes third to fifth multiplexers 52 to 56 that are commonly connected to the first internal bus 35. The third multiplexer 52 has first to third input ports for inputting g + N + r bits of data from the first, second and fourth internal buses 35, 37 and 43, respectively. The third multiplexer 52 supplies any one of three data to the first ALU 58 from the first, second and fourth internal buses 35, 37, and 43. The fourth multiplexer 54 includes a first input port 39 for inputting a logic value of 0 and a second input for g + N + r bits of data from the first and third internal buses 35 and 41, respectively. And a third input port. The fourth multiplexer 54 supplies any one of three pieces of data on its first to third input ports to the first ALU 58. The first ALU 58 computes two data from the third and fourth multiplexers 52 and 54 and supplies the calculated result to the sixth multiplexer 62. The fifth multiplexer 56 also selectively outputs g + N + r bits of data from the first internal bus 35 and g + N + r bits of data from the third internal bus 41. To feed. The barrel shifter 60 scales the logical value of the data from the fifth multiplexer 56 and supplies the scaled data to the sixth multiplexer 62. In order to scale this data, the barrel shift 60 shifts the data from the fifth multiplexer 56 to the left or right direction by the number of bits corresponding to the scaling amount. In addition, since the barrel shifter 60 is connected in parallel with the first ALU 58, the propagation delay time of data can be minimized. Accordingly, the DSP can perform arithmetic operations, scaling and arithmetic operations including the same at high speed. The sixth multiplexer 62 selectively selects the fifth + sixth register 64 or 66 from the arithmetic data of g + N + r bits from the first ALU 58 and the scaled data from the barrel shift 60. Supplies). Data stored in the fifth or sixth register 64 or 66 is supplied to the third internal bus 41. The fifth and sixth registers 64 and 66 constitute a first accumulator together with the first ALU 58 as accumulation registers. Both the fifth and sixth registers 64 and 66 have a length of g + N + r bits to temporarily store g + N + r bits of data, and the third internal bus 41 also has g + N + r bits. It consists of two lines.

In addition, the DSP includes a seventh multiplexer 68 connected to the first internal bus 35 and the fourth internal bus 43, and an eighth multiplexer 70 connected to the first and second internal buses 35 and 37. ). The seventh multiplexer 68 includes a first input port 45 for inputting a logic value of zero and a second input data of g + N + r bits from the first and fourth internal buses 35 and 43, respectively. And a third input port. The seventh multiplexer 68 supplies any one of three pieces of data on its first to third input ports to the second ALU 72. The eighth multiplexer 70 has first and second input ports for inputting g + N + r bits of data from the first and second internal buses 35 and 73, respectively. The eighth multiplexer 70 supplies any one of two data from the first and second internal buses 35 and 73 to the second ALU 72. The second ALU 72 calculates two data from the seventh and eighth multiplexers 68 and 70 and supplies the calculated result to the ninth multiplexer 74. The ninth multiplexer 74 selectively stores the calculated data of the g + N + r bits from the second ALU 72 and the scaled data from the barrel shifter 60 to the seventh or eighth register 76 or 78. Supply. The seventh or eighth registers 76 and 78 are supplied with data from the ninth multiplexer 74 to the fourth internal bus 43. The seventh and eighth registers 76 and 78 form a second accumulator together with the second ALU 72 as a cumulative register, and the second accumulator is connected in parallel with the first accumulator so that two or more complex equations are parallel. To be calculated as Both the seventh and eighth registers 76 and 78 have a length of g + N + r bits to temporarily store g + N + r bits of data. In addition, the seventh and eighth registers 76 and 78, together with the fifth and sixth registers 64 and 66, allow multiple compound equations to be computed quickly.

Furthermore, the DSP is common to the tenth multiplexer 80 and the tenth multiplexer 80 for selecting two g + N + r bit data from the third and fourth internal buses 41 and 43. And a third and fourth bit sorter 82,84 and a rounding / saturation processor 82 connected to each other. The tenth multiplexer 80 includes g + N + r bits of data from the fifth or sixth registers 64 and 66 via the third internal bus 41 and the fourth through the internal bus 23. Any one of g + N + r bits of data from the seventh or eighth registers 76 and 78 is commonly supplied to the third and fourth bit sorters 82 and 84 and the rounding / saturation processor 86. do. The third and fourth bit sorters 82 and 84 extract only N bits from g + N + r bits of data from the tenth multiplexer 80 to extract the extracted N bits of data from the eleventh multiplexer 88. Supply to the first and second input ports respectively. In detail, the third bit sorter 82 extracts only N bits of data from the upper g + 1 th bit of the g + N + r bits from the tenth multiplexer 80 to extract the N bits of the extracted N bits. Data is supplied to the first input port of the eleventh multiplexer 88. For this purpose, the third bit sorter 82 may have N terminals from the upper g + 1 th terminal among the g + N + r output terminals of the tenth multiplexer 80, that is, the upper g terminals and the lower r. Wiring for connecting the remaining N terminals except for the N terminals to the first input port of the eleventh multiplexer 88 including N terminals is provided. Only by wiring, the third bit sorter 82 converts data of g + N + r bits into N bits of data. The fourth bit sorter 84 extracts only the lower N bits of the data of the g + N + r bits from the tenth multiplexer 80, and extracts the extracted N bits of data from the eleventh multiplexer 88. 2 Supply to the input port. For this purpose, the fourth bit sorter 84 may select N N terminals other than the lower N terminals, that is, the upper g + r terminals, among the g + N + r output terminals of the tenth multiplexer 80. And a wiring for connecting to the second input port of the eleventh multiplexer 88 consisting of four terminals. The fourth bit sorter 84, together with the first to third bit sorters 32, 34 and 82, is simply constituted by wiring so that no separate circuit block is required. Accordingly, the first to fourth bit sorters 32, 34, 82, and 84 can simplify the circuit configuration of the DSP and allow both fixed-point and integer operations to be performed at high speed.

The rounding / saturation processor 86 is driven in the rounding processing mode, the saturation processing mode, or the merge mode in response to a command from a controller (not shown). In the rounding mode, the rounding / saturation processor 86 selects N bits of data from the r + 1st lower bits in g + N + r bits of data from the 10th multiplexer 80 to generate the 11th multiplexer 88 data. 3 Supply to the input port. Next, in the saturation mode, the rounding / saturation processor 86 selects N bits of data from the e + 1st lower bits of the g + N + r bits from the 10th multiplexer 80 to select the 11th multiplexer 88. To the third input port. Next, in the saturation mode, the rounding / saturation processor 86 processes the data according to the logical value of the upper g + 1 bits in the g + N + r bit data from the tenth multiplexer 80. In detail, the rounding / saturation processor 86 performs the processing of the upper g + 1 bits (ie, g guard bits and one sign bit) in the g + N + r bits of data from the tenth multiplexer 80. It is determined whether overflow occurs according to whether all logic values are the same. When the logic values of the upper g + 1 bits are all the same, the rounding / saturation processor 86 performs the remaining N bits except for the upper g bit and the lower r bit among the g + N + r bits of data from the tenth multiplexer 80. Is supplied to the third input port of the eleventh multiplexer 88 as a result of the calculation. Conversely, when the logic values of the upper g + 1 bits are not all the same, the rounding / saturation processor 86 determines whether the logical value of the most significant bit of the g guard bits is 0 or 1. When the logic value of the most significant guard bit is 0, the rounding / saturation processor 86 considers that the data from the tenth multiplexer 80 is positive data in which an overflow has occurred. N bits of data (ie, 011... 11) of the maximum value having a logic value are supplied to the third input port of the eleventh multiplexer 88. On the contrary, when the logic value of the most significant guard bit is 1, the rounding / saturation processor 86 regards the data from the tenth multiplexer 80 as negative data having overflowed, and thus only the most significant bit. N bits of data (that is, 1000... 00) having a logic value of 1 are supplied to the third input port of the eleventh multiplexer 88. In this way, the saturation processor 86 can correctly process the saturation logic of the data calculated by the ALU 58 or 72 based on the logic values of the guard bits and the sine bits (that is, the logic value at which the overflow occurred). do. Finally, in merge mode, the rounding / saturation processor 86 performs the rounding process on the g + N + r bits of data from the tenth multiplexer 80 and then on the rounded g + N bits of data. The saturation processor is performed. The N-bit data rounded and saturated by the rounding / saturation processor 86 is supplied to the eleventh multiplexer 88. In this case, the rounding / saturation processor 86 performs rounding processing for the lower bits first, but does not consume a separate rounding processing time by performing the rounding and saturation processing in one clock period. Accordingly, the rounding / saturation processor 86 provides the advantage of rounding the data that has been fixed-point computed without consuming extra time. The eleventh multiplexer 88 transmits one of the three N-bit data from the third and fourth bit sorters 82 and 84 and the rounding / saturation processor 86 to the third external bus 47. The third external bus 47 is composed of N lines composed of a write data bus and a write address bus.

FIG. 3 is a diagram showing a part where rounding of data in FIG. 2 is performed. In Fig. 3, the first data D1 of g + N + r bits is temporarily stored in the accumulation register 64, 66, 76, 78 after being calculated by the ALU 58 or 72. In the first data D1, g is guard bits, N is source data from a memory (not shown), and r is rounding bits. The third bit sorter 82 does not consume additional processing time by converting the first data D1 into N bits of the second data D2 by the wiring as described in FIG. 2. The rounding / saturation processor 86 converts the first data D1 into N bits of second data D2 by rounding the first data D1 and then saturating the rounded data. The eleventh multiplexer 88 outputs a third bit or an output data of the rounding / saturation processor 86 according to whether the first data D1 should be saturated, that is, whether the first data D1 has overflowed. The output data of the sorter 82 is selected. In detail, the eleventh multiplexer 88 selects the output data of the rounding / saturation processor 86 when the first data D1 needs to be saturated, that is, when an overflow occurs in the first data D1. Choose. In contrast, when the first data D1 does not need to be saturated, that is, when no overflow occurs in the first data D1, the eleventh multiplexer 88 outputs the output data of the third bit sorter 82. Select. The rounding / saturation processor 86, the third bit sorter 82, and the eleventh multiplexer 88 prevent the DSP from spending extra time (i.e., clock period) for the rounding process of the data. Processing data at high speed.

As described above, the DSP of the present invention can shorten the lengths of the ALU and the accumulation register by adjusting the number of bits (i.e., word length) of data supplied to the ALU by wiring. In addition, the DSP according to the present invention can eliminate the time required for the rounding process of the data by performing the rounding of the data at the same time during the data saturation processing. Accordingly, the DSP according to the present invention can speed up signal processing.

In addition, in the DSP according to the present invention, since the bit sorters implemented as wirings are arranged at the front and rear ends of the accumulator, fixed-point and integer operations are performed quickly, and the circuit configuration is simplified.

Furthermore, the DSP according to the present invention can minimize the propagation delay time by connecting the barrel shifter to the ALU in parallel and can reduce the number of clocks required for the calculation. Accordingly, the DSP according to the present invention can perform calculations, scaling, and calculations including the same at high speed.

The DSP according to the present invention can compute a plurality of complex equations at high speed by computing two complex equations in parallel using a pair of ALUs connected in parallel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (13)

Data input means for inputting N bits of data; Rounding bit adding means for adding a round bit of r bits smaller than N to the N bit data from the data input means; Guard bit adding means for adding a g-bit guard bit to an upper bit of data from the rounding bit adding means; Calculating means for calculating data from the guard bit adding means; Rounding / saturation processing means for performing saturation and rounding of data from said computing means; And rounding means for rounding the data from said computing means. The method of claim 1, And said rounding / saturation processing means selectively performs said saturation processing and said rounding and saturation processing on the data to said computing means. The method of claim 2, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 3, The rounding / saturation processing means has N logic data of which only the most significant bit has a logic value of zero and only the most significant bit has a logic value of 1 when the logical values of the upper g + 1 bits of data from the computing means are different. A digital signal processor characterized by selectively generating N bits of data. The method of claim 4, wherein The rounding / saturation processing means generates N bits of data having only a logical value of 1 when only the most significant bit is 1 when the logical value of the most significant bit of the data from the computing means is 1, and the logical value of the most significant bit is 0. A digital signal processor, characterized in that only the most significant bit generates N bits of data having a logical value of zero. The method according to any one of claims 1 to 5, And the rounding means is implemented by wiring. The method according to any one of claims 1 to 5, And the guard bit adding means is implemented by wiring. Data input means for inputting N bits of data; Rounding bit adding means for adding a round bit of r bits smaller than N to the N bit data from the data input means; Guard bit adding means for adding a g-bit guard bit to an upper bit of data from the rounding bit adding means; Operation logic means for converting data from the guard bit adding means and data from the feedback loop; A memory for temporarily storing data from said operational logic means and connected to said feedback loop; Scaling means for scaling data from the guardbit adding means; Selecting means for selectively transferring data from the scaling means and data from the arithmetic logic means to the memory; Rounding / saturation processing means for saturating and rounding data from the memory; And rounding means for rounding the data from the memory. The method of claim 8, And said rounding / saturation processing means selectively performs said saturation processing and said rounding and saturation processing on data from said computing means. The method of claim 9, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 10, The rounding / saturation processing means generates N bits of data having only a logical value of 1 when only the most significant bit is 1 when the logical value of the most significant bit of the data from the computing means is 1, and the logical value of the most significant bit is 0. A digital signal processor, characterized in that only the most significant bit generates N bits of data having a logical value of zero. The method according to any one of claims 8 to 11, And the rounding means is implemented by wiring. The method according to any one of claims 8 to 11, And the rounding bit adding means is implemented by wiring.