KR19990012234A - Manufacturing method of semiconductor device for adjusting gap gap between patterns using spacer - Google Patents

Abstract

A method of manufacturing a semiconductor device in which a gap between patterns is controlled by using a spacer is disclosed. The present invention forms a first spacer on both sides of a first gate stack formed on a semiconductor substrate in an NMOS region and a second gate stack formed on a semiconductor substrate in a PMOS region. Thereafter, a first impurity region, that is, a first drain region and a first source region, is formed in the NMOS region using a first spacer as a mask. Next, a third insulating film is formed on the entire surface of the semiconductor substrate on which the first spacer is formed. Subsequently, a fourth insulating film having an etching rate different from that of the third insulating film is formed on the third insulating film. Thereafter, a second impurity region, that is, a second drain region and a second source region for the PMOS transistor, is formed in the semiconductor substrate of the PMOS region using the fourth insulating layer and the first spacer as a mask. Thereafter, the fourth insulating layer may be completely removed or partially removed to further secure a margin of a gap between the first gate stacks. Alternatively, the fourth insulating layer may be etched to form a second spacer on the first spacer, and a second impurity region for the PMOS transistor may be formed on the semiconductor substrate of the PMOS region using the first spacer and the second spacer as a mask. Subsequently, the second spacer may be removed as an etching end point to further secure a gap margin between the first gate stacks.

Description

Manufacturing method of semiconductor device for adjusting gap gap between patterns using spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a gap between patterns is controlled by using a spacer.

As semiconductor devices become more integrated, it is increasingly difficult to secure an operating area of an active device, such as a transistor. For example, in a semiconductor device including an N-channel metal oxide semiconductor transistor (NMOS transistor) and a P-channel metal oxide semiconductor transistor (PMOS transistor), the PMOS transistor may be formed of phosphorus (P) or an impurity used to form an NMOS transistor. It is formed by using boron (B) and boron difluoride (BF ₂ ), which are lighter impurities than arsenic (As). Therefore, to secure an effective channel length of a PMOS transistor from an impurity ion implantation process for forming a PMOS transistor or a subsequent diffusion of the impurity ions by a heat budget. Is difficult.

Accordingly, a double spacer is formed at both sides of the gate stack 20, 30, 40 of the transistor in a method of securing an effective channel length of the transistor, that is, a method of securing an operating region of the transistor. A method of forming is proposed. For example, as shown in FIG. 1, in order to secure the margin of the effective channel length of the PMOS transistor formed in the semiconductor substrate 10 of the PMOS region B of the peripheral circuit portion of the semiconductor substrate 10, A spacer having a thickness larger than that of the first spacer 50 satisfying the effective channel length required for the NMOS transistor formed in the semiconductor substrate 10 of the NMOS region A of the cell array part is required. .

Therefore, in the conventional semiconductor device manufacturing method, the first impurity region 71, i.e., the first drain region and the first impurity region 71 for the NMOS transistor, is masked by using a first spacer 50 that meets the effective channel length required for the NMOS transistor. One source region is formed. Thereafter, a second spacer 60 is formed on the first spacer 50. The second impurity region 75 for the PMOS transistor, i.e., the second drain region and the second spacer 60 and the first spacer 50 formed as described above, satisfying the effective channel length required by the PMOS transistor; The second source region is formed. In this way, the respective effective channel lengths required by the PMOS transistor and the NMOS transistor can be satisfied. Such a method using the double spacer is advantageous in setting the formation conditions of the NMOS transistor and the PMOS transistor in terms of drain engineering of the transistor.

However, as semiconductor devices become more highly integrated, the line width occupied by transistors in repeating patterns, such as cell array portions of semiconductor devices, becomes smaller. Therefore, when the spacer of the double layer is formed in consideration of the effective channel length required for the PMOS transistor of the peripheral circuit part, the gap margin, that is, the gap margin between the gate stacks 20, 30, and 40 of the NMOS transistor of the cell array part is formed. gap margin) is not secured. As a result, when filling the gap between the gate stacks 20, 30, and 40 of the NMOS transistor with an interlayer insulating film or the like, a filling defect such as a void occurs. That is, in the case of a 1 giga-class dynamic random access memory (DRAM) device, the aspect ratio of the gap between the gate stacks 20, 30, and 40 is 6 to 10, and thus the gap is determined. Peeling becomes difficult Therefore, it becomes impossible to introduce the double spacer. In other words, it is impossible to form a double spacer to secure the effective channel length required for the PMOS transistor.

The technical problem to be achieved by the present invention is to secure the gap margin between the gate stack of the NMOS transistor, and when filling the gap exposed by the gate stack, it is possible to suppress the occurrence of filling defects, such as voids, in the PMOS transistor The present invention provides a method of manufacturing a semiconductor device using a spacer capable of securing an effective effective channel length.

1 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

2 to 7 are cross-sectional views shown for explaining an example of a method of manufacturing a semiconductor device of the present invention.

8 is a cross-sectional view illustrating another example of the method of manufacturing the semiconductor device of the present invention.

9 is a cross-sectional view illustrating another example of the method of manufacturing the semiconductor device of the present invention.

In order to achieve the above technical problem, the present invention provides a first gate stack on a semiconductor substrate of the NMOS region of a semiconductor substrate including an NMOS region and a PMOS region, and a second gate stack on the semiconductor substrate of the PMOS region. To form. Next, first spacers are formed at both sides of the first gate stack and the second gate stack. In this case, after the forming of the first spacer, a first impurity region, that is, a first drain region and a first source region, is formed on a semiconductor substrate of an NMOS region adjacent to the first gate stack using the first spacer as a mask. And forming an NMOS transistor. Next, a third insulating film is formed on the entire surface of the semiconductor substrate on which the first spacer is formed. Subsequently, a second spacer is formed on the third insulating layer to have an etch rate different from that of the third insulating layer and to overlap the first spacer. In this case, the second spacer is formed using an oxide film and the third insulating film is formed of a nitride film. Next, a second impurity region, that is, a second drain region and a second source region, is formed in the semiconductor substrate of the PMOS region adjacent to the second gate stack with the second spacer as a mask to form a PMOS transistor. Thereafter, the second spacer is removed by using the third insulating layer as an etching end point.

In addition, another example of the present invention forms a first gate stack on the semiconductor substrate of the NMOS region of the semiconductor substrate including the NMOS region and the PMOS region and a second gate stack on the semiconductor substrate of the PMOS region. Subsequently, a first spacer covering both sides of the first gate stack and the second gate stack is formed. In this case, after the forming of the first spacer, a first impurity region, that is, a first drain region and a first source region, is formed on a semiconductor substrate of an NMOS region adjacent to the first gate stack using the first spacer as a mask. Forming an NMOS transistor. Subsequently, a third insulating film is formed on the entire surface of the semiconductor substrate on which the first spacer is formed, and a fourth insulating film having an etching rate different from that of the third insulating film is formed on the third insulating film. In this case, the third insulating film is formed of a nitride film and the fourth insulating film is formed of an oxide film. Next, a second impurity region, that is, a second drain region and a second source region, is formed in the semiconductor substrate of the PMOS region adjacent to the second gate stack to form a PMOS transistor. Next, the fourth insulating film is removed by using the third insulating film as an etching end point.

In addition, another example of the present invention forms a first gate stack on a semiconductor substrate of the NMOS region and a second gate stack on a semiconductor substrate of the PMOS region in a semiconductor substrate including an NMOS region and a PMOS region. . Next, first spacers are formed at both sides of the first gate stack and the second gate stack. In this case, after the forming of the first spacer, a first impurity region, that is, a first drain region and a first source region, is formed on a semiconductor substrate of an NMOS region adjacent to the first gate stack using the first spacer as a mask. NMOS transistors can be formed. Subsequently, a third insulating layer is formed on the entire surface of the semiconductor substrate on which the first spacer is formed. Next, a fourth insulating film having an etch rate different from that of the third insulating film is formed on the third insulating film. In this case, the fourth insulating film is formed using an oxide film and the third insulating film is formed of a nitride film. Subsequently, a second impurity region, that is, a second drain region and a second source region, is formed in the semiconductor substrate of the PMOS region adjacent to the second gate stack with a portion of the fourth insulating layer overlapping the first spacer after the mask. To form a PMOS transistor. Next, the fourth insulating film is removed to only a part of the thickness of the fourth insulating film to form a buffer film thinner than the thickness of the fourth insulating film.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

2 illustrates forming first gate stacks 250, 350, and 450 and second gate stacks 200, 300, and 400 on the semiconductor substrate 100.

Specifically, device isolation (not shown) is formed on the semiconductor substrate 100 including the NMOS region A and the PMOS region B to define the active region. Thereafter, a gate oxide film is formed on the semiconductor substrate 100. After that, a conductive film and an insulating film are sequentially formed on the gate oxide film. As the conductive film, a silicon film or a metal silicide layer doped with an impurity is used. Subsequently, the insulating layer and the conductive layer are sequentially patterned to form a first insulating layer pattern 450, a first gate electrode 350, and a first gate oxide layer pattern 250 on the semiconductor substrate 100 in the NMOS region A. FIG. To set the first gate stack 250, 350, and 450. At the same time, the second insulating layer pattern 400, the second gate electrode 300, and the second gate oxide layer pattern 200 are formed on the semiconductor substrate 100 in the PMOS region B to form the second gate stack 200 and 300. , 400).

FIG. 3 illustrates forming first spacers 500 on both sides of the first gate stacks 250, 350, and 450 and the second gate stacks 200, 300, and 400.

First, an insulating layer covering the first gate stack 250, 350, and 450 and also covering the second gate stack 200, 300, and 400 is formed. Subsequently, the insulating layer is formed on both sides of the first gate stack 250, 350, and 450 and both sides of the second gate stack 200, 300, and 400 by using a method such as an anisotropic etching method. The remaining spacers are etched to form a first spacer 500. In this case, the first spacer 500 is formed using an oxide film or a nitride film (SiN).

In addition, on the semiconductor substrate 100 on which the first spacer 500 is formed, an agent that exposes the semiconductor substrate 100 in the NMOS region A and shields the semiconductor substrate 100 in the PMOS region B is provided. The monoion shielding film pattern 600 is formed, for example, a photoresist pattern. Subsequently, impurities are implanted into the semiconductor substrate 100 adjacent to the first gate stacks 250, 350, and 450 using the first spacer 500 as a mask to form the first impurity region 710, that is, the first impurity. A drain region and a first source region are formed. In this manner, an NMOS transistor can be formed in the semiconductor substrate 100 in the NMOS region A. FIG.

4 illustrates a step of forming a third insulating film 800.

In detail, the third insulating layer 800 is formed on the entire surface of the semiconductor substrate 100 on which the first spacer 500 is formed. In this case, the third insulating layer 800 is formed using a material having a different etch rate from the fourth insulating layer to be formed thereon. For example, the nitride film SiN is formed to have a thickness of 10 kPa to 300 kPa. The third insulating layer 800 formed as described above is used as an etch stopper in an etching process to be introduced later, or an element separation (not shown) or a first spacer 500 under the third insulating layer 800 is performed. Serves to protect the

5 illustrates forming a fourth insulating film 630 on the third insulating film 800.

The fourth insulating layer 630 is formed on the third insulating layer 800 by using a material having an etching rate different from that of the third insulating layer 800. For example, when the third insulating film 800 is formed using a nitride film, an oxide film is used as the fourth insulating film 630. In this case, an etch selectivity between the third insulating film 800 and the fourth insulating film 630 becomes high, and the third insulating film 800 may act as an etching end point in a subsequent etching process. In addition, the third insulating layer 800 may serve to protect the lower portion thereof, thereby preventing invasion of the lower layer and device separation by the etching process.

6 illustrates forming a second spacer 550.

Specifically, by using an etching method such as an anisotropic etching method, a portion of the fourth insulating film 630 overlapping the first spacer 500 is left and the fourth insulating film 630 is removed. In this case, the portion of the third insulating layer 800 overlapping with the first spacer 500 is left by using the third insulating layer 800 as an end point of etching. In this way, a second spacer 550 is formed on the first spacer 500 so as to overlap the first spacer 500. Accordingly, a shape in which double spacers including a first spacer 500 and a second spacer 550 are formed at both sides of the first gate stack 250, 350, and 450 and the second gate stack 200, 300, and 400. Becomes

Thereafter, a second impurity region 750 is formed in the semiconductor substrate 100 adjacent to the second gate stacks 200, 300, and 400 using the second spacer 550 as a mask. For example, after forming the second spacer 550, the second ion shielding film pattern exposing the semiconductor substrate 100 in the PMOS region B and shielding the semiconductor substrate 100 in the NMOS region A. 650, for example, a photoresist pattern is formed. Subsequently, impurities are implanted into the semiconductor substrate 100 adjacent to the second gate stacks 200, 300, and 400 with a dose of about 1E15 / cm 2 or more using the second spacer 550 as a mask. A second impurity region 750 is formed, that is, a second drain region and a second source region. Preferably, boron or boron difluoride is ion implanted at a dose of 1E15 / cm 2 to 1E17 / cm 2. In this manner, a PMOS transistor is formed in the semiconductor substrate 100 in the PMOS region B. FIG.

As described above, the double spacers of the first spacer 500 and the second spacer 550 are masked to form the PMOS transistor, whereas the first spacer 500 is ion implanted to form the NMOS transistor. Inject with ions. Therefore, an effect of performing an ion implantation process for forming a PMOS transistor with a thicker mask can be obtained. Thus, an effective channel length of a larger PMOS transistor can be obtained. Therefore, the effective channel length of the PMOS transistor can be secured from diffusion caused by the heat budget of boron and boron difluoride.

7 illustrates removing the second spacer 550.

Specifically, after the second impurity region 750, that is, the second drain region and the second source region, is formed in the semiconductor substrate 100 of the PMOS region B, the second spacer 550 is formed on the lower portion thereof. The third insulating layer 800, for example, is removed by using an isotropic etching method with a high selectivity. For example, the second spacer 550 is removed using a wet etching method using selective buffered oxide etchant (SBOE). As such, when the second spacer 550 is removed, the width of the semiconductor substrate 100 exposed between the first spacers 500 formed on the NMOS region A may be further secured. Therefore, when the interlayer insulating film is formed on the first spacer 500 later, the gap between the first spacer 500, that is, between the first gate stacks 250, 350, and 450 is filled, compared to the conventional art. Lower aspect ratios can be achieved.

The reduction of the aspect ratio is calculated by taking a process of manufacturing a dynamic random access memory (DRAM) device having a pitch of 0.5 μm as an example. In other words, the width of the line space is 250 nm and 250 nm, respectively, and the thickness of the first spacer 500 is 500 Å, the thickness of the second spacer 550 is 300 Å, and the thickness of the third insulating film 800 is set. Consider the NMOS transistor of the cell array unit in the case where the height of the first gate stack including the 100 kHz, the first gate electrode 350 and the first insulating film pattern 450 is 4000 kHz. In this case, in case of using the conventional double spacer, the gap margin of 700 μs is obtained by subtracting the thickness of the first spacer 500, the second spacer 550, and the third insulating layer 800 from the height of 4000 μs of the first gate stack. Is secured. Therefore, an aspect ratio of 5.7 is obtained by 4000 Hz / 700 Hz. In contrast, in the present invention, since the second spacer 550 is subsequently removed, an aspect ratio of approximately 3.1 is achieved by 4000 Å / 1300 Å. Therefore, the aspect ratio of about 2.5 can be lowered than when using the conventional double spacer. In addition, the advantage of lowering the aspect ratio shows a larger effect as the pitch is smaller.

As such, the first spacer 500 and the second spacer 550 are formed to satisfy the effective channel length required for the PMOS transistor, and the second impurity region 750, that is, the second drain region and the second source region, is formed. Can be formed. Subsequently, the second spacer 550 may be removed to further secure a gap gap between the first gate stacks 250, 350, and 450 of the NMOS transistors formed in the cell array of the semiconductor device. The gap ratio secured in this way can lower the aspect ratio of the gap, thereby suppressing the occurrence of filling defects when forming the subsequent interlayer insulating film, and satisfactorily filling the gap with the interlayer insulating film.

8 is a cross-sectional view for explaining the second embodiment of the present invention.

In the second embodiment, the step of forming the second spacer 550 by etching the fourth insulating layer 630 is omitted. That is, the second embodiment is the same as the first embodiment until the step of forming the fourth insulating film 630. Incidentally, in the second embodiment, the same reference numerals as in the first embodiment denote the same members.

Specifically, as illustrated in FIG. 2, the first gate oxide pattern 250, the first gate electrode 350, and the first insulating layer pattern 450 are formed on the semiconductor substrate 100 to form the first gate stack 250. , 350, 450, and at the same time, the second gate oxide pattern 200, the second gate electrode 300, and the second insulating layer pattern 400 are formed to form the second gate stacks 200, 300, and 400. do. 3 to 5, the first spacer 500, the third insulating film 800, and the fourth insulating film 630 are formed. The above is the same as described in the first embodiment. However, after the fourth insulating film 630 is formed, another process is performed.

As described above, after the fourth insulating layer 630 is formed, the semiconductor substrate 100 of the PMOS region B is exposed on the fourth insulating layer 630 and the NMOS region A is exposed. A second ion shielding film pattern 650, for example, a photoresist pattern, is formed to shield the semiconductor substrate 100. Subsequently, the first spacer 500 and a portion of the fourth insulating layer 630 disposed thereon and overlapping the first spacer 500 are adjacent to the second gate stacks 200, 300, and 400 using a mask. The second impurity region 750 is formed in the semiconductor substrate 100. For example, impurities are implanted at a dose of about 1E15 / cm 2 or more to form the second impurity region 750, that is, the second drain region and the second source region. Preferably, boron or boron difluoride is ion implanted at a dose of 1E15 / cm 2 to 1E17 / cm 2. In this manner, a PMOS transistor is formed in the semiconductor substrate 100 in the PMOS region B. FIG.

Thereafter, the fourth insulating layer 630 is removed using an isotropic etching method having a high selectivity with respect to the third insulating layer 600, for example, the nitride layer. For example, by using a wet etching method using SBOE, the fourth insulating layer 630 is etched and removed until the third insulating layer 800 is exposed. As such, when the fourth insulating layer 800 is removed, the width of the semiconductor substrate 100 exposed between the first spacers 500 formed on the NMOS region A, that is, the first gate electrodes 250 and 350. , A gap margin between 450) can be more secured. Therefore, when forming an interlayer insulating film that fills the gap between the first spacer 500 on the first spacer 500, a gap having a lower aspect ratio than the conventional one can be realized, and the gap is better. Can be filled.

As such, unlike the first embodiment, the etching process of forming the second spacer 550 may be omitted by forming the fourth insulating layer 630 and forming the second impurity region 750 forming the PMOS transistor. The process can be simplified further. In addition, by omitting the etching process for forming the second spacer 550 as in the first embodiment, the third insulating layer 800 may be less invaded by the etching process. Therefore, the thickness of the third insulating layer 800 may be formed thinner than in the first embodiment.

9 is a cross-sectional view for explaining the third embodiment of the present invention.

In the third embodiment, the same reference numerals as in the first and second embodiments denote the same members. The third embodiment is the same as the second embodiment until the step of forming the second impurity region 750 for forming the PMOS transistor, that is, the second drain region and the second source region. However, unlike the second embodiment, a portion of the fourth insulating layer is etched without being completely removed and used as the buffer layer 670.

Specifically, as illustrated in FIG. 2, the first gate stacks 250, 350, and 450 are set on the semiconductor substrate 100, and the second gate stacks 200, 300, and 400 are set. 3 to 5, the first spacer 500, the third insulating film 800, and the fourth insulating film 630 are formed. Subsequently, as illustrated in FIG. 8, a second impurity region 750, that is, a second drain region and a second source region, for forming a PMOS transistor is formed. Thereafter, the fourth insulating layer 630 is etched to leave a portion thereof without being completely removed. In this way, a buffer film 670 having a thickness smaller than that of the fourth insulating film 630 is formed on the third insulating film 800. When the buffer layer 670 is formed thereafter, the interlayer insulating layer (not shown) serves to improve the interfacial property between the third insulating layer 800 and the interlayer insulating layer 670.

In the above, the present invention has been described in detail with reference to specific embodiments, but the present invention is not limited to the above-described embodiments, and modifications and improvements of the present invention are made by those skilled in the art within the scope of the technical idea of the present invention. It is obvious that this is possible.

Therefore, according to the present invention described above, the first impurity region, that is, the first drain region for forming the NMOS transistor by forming the first spacer on both sides of the first gate stack on the semiconductor substrate including the PMOS region and the NMOS region And a first source region. Subsequently, by forming a second spacer overlapping the first spacer, a second impurity region for forming a PMOS transistor may be formed using a double spacer composed of the first spacer and the second spacer. In addition, instead of forming a second spacer, a fourth insulating layer may be formed on the first spacer, and the second impurity region may be formed using a portion of the fourth insulating layer overlapping the first spacer. In this way, the effective channel length required for each of the NMOS transistor and the PMOS transistor can be satisfied.

In addition, after forming the second impurity region for forming the PMOS transistor as described above, the second spacer or the fourth insulating layer is formed using another third insulating layer formed between the first spacer and the second spacer or the fourth insulating layer. The first spacer and the fourth insulating layer may be removed using the etching endpoint. Alternatively, a portion of the fourth insulating layer may be removed to form a buffer layer. In this way, the gap gap between the first gate stacks of the NMOS transistors can be more secured, and the aspect ratio of the gap can be lowered. Accordingly, when the interlayer insulating layer is formed on the first gate stack, the gap may be better filled and the interlayer insulating layer may be formed.

Claims (8)

Forming a first gate stack on a semiconductor substrate of the NMOS region of the semiconductor substrate including an NMOS region and a PMOS region and forming a second gate stack on the semiconductor substrate of the PMOS region; Forming first spacers on both sides of the first gate stack and the second gate stack; Forming a third insulating layer on an entire surface of the semiconductor substrate on which the first spacer is formed; Forming a second spacer on the third insulating layer, the second spacer having an etch rate different from that of the third insulating layer and overlapping the first spacer; Forming a second impurity region on a semiconductor substrate adjacent to the second gate stack with the second spacer as a mask to form a PMOS transistor; And And removing the second spacer using the third insulating layer as an etching end point. The method of claim 1, wherein after forming the first spacer And forming a first impurity region in a semiconductor substrate adjacent to the first gate stack with the first spacer as a mask to form an NMOS transistor. The method of claim 1, wherein the second spacer is formed of an oxide film. The method of claim 1, wherein the third insulating film is formed of a nitride film. Forming a first gate stack on a semiconductor substrate of the NMOS region of the semiconductor substrate including an NMOS region and a PMOS region and a second gate stack on the semiconductor substrate of the PMOS region; Forming a first spacer covering both sides of the first gate stack and the second insulating film stack; Forming a third insulating layer on an entire surface of the semiconductor substrate on which the first spacer is formed; Forming a fourth insulating layer on the third insulating layer, the fourth insulating layer having an etching rate different from that of the third insulating layer; Forming a second impurity region in a semiconductor substrate adjacent to the second gate stack using a portion of the fourth insulating layer overlapping the first spacer to form a PMOS transistor; And And removing the fourth insulating film using the third insulating film as an etching end point. 6. The method of claim 5, wherein the third insulating film is formed of a nitride film. 6. The method of claim 5, wherein the fourth insulating film is an oxide film. Forming a first gate stack on a semiconductor substrate of the NMOS region of the semiconductor substrate including an NMOS region and a PMOS region and forming a second gate stack on the semiconductor substrate of the PMOS region; Forming a first spacer covering both sides of the first gate stack and the second gate stack; Forming a third insulating layer on an entire surface of the semiconductor substrate on which the first spacer is formed; Forming a fourth insulating layer on the third insulating layer, the fourth insulating layer having an etching rate different from that of the third insulating layer; Forming a PMOS transistor by forming an impurity region in a semiconductor substrate adjacent to the second gate stack using a portion of the fourth insulating layer overlapping the first spacer as a mask; And And removing the fourth insulating film to a part of the thickness of the fourth insulating film to form a buffer film having a thickness thinner than the thickness of the fourth insulating film.