KR19990009905A - Graphic Data Processing Unit - Google Patents

Abstract

The present invention relates to a graphic data processing method and apparatus for processing graphic data.

An apparatus for processing graphic data of the present invention includes main control means for controlling data transmission and operation of data, a memory for storing data processed by the main control means in a bitmap manner, and an access request of the main control means. A memory device for continuously accessing data stored in any rectangular storage area on the memory in response to and storing a head address of the image data stored in the memory, and a memory for storing width data of the image stored in the memory. An element, a memory element for storing the height data of the image stored in the memory, a memory element for storing the width data of the part to be accessed, a memory element for storing the height data of the part to be accessed, and A storage element for storing width direction data of the portion, and a portion to be accessed Auxiliary control means having a memory element for storing minute height data is provided.

Description

Graphic Data Processing Unit

The present invention relates to a graphic data processing method and apparatus for processing graphic data.

As the environment of all electronic devices enters the multimedia era, the amount of data is increasing, and the rapid transmission of this data has become a big issue. In particular, how fast a relatively large amount of graphics data transfer in a personal computer or multimedia device is the benchmark of the device. In addition, in a window system commonly used in personal computers or multimedia devices, in order to process graphic data for expressing visual symbols and figures, the position of each bit in the main memory and the pixel position of the graphic display device are matched. The bitmap (BIT MAP) method shown on the screen is adopted.

On the other hand, in terms of the processing speed of graphic data, when comparing a central processing unit (CPU) and a DMA controller (Direct Memory Access Controller), the CPU directly accesses and reads the memory. A fetch cycle for specifying the address to be assigned, outputting data in memory, and transferring the output data is required to process individual bitmap data, so that the transfer time of graphic data is long, and data processing is performed. Is performed by the CPU operation, the processing speed of the graphic data is lowered, resulting in a decrease in the performance of the multimedia device. On the other hand, in the DMA controller, when the head address of the data to be transmitted from the CPU and the number of data to be transmitted are transferred to the DMA controller, the DMA controller accesses the memory and processes the data continuously, thereby enabling fast graphic data transfer. Therefore, it can be seen that the graphic data processing speed of the DMA controller is faster than that of the CPU in processing the graphic data.

A method of transferring graphic data in a conventional DMA controller will be described with reference to FIGS. 1 and 2.

1 is a block diagram of a system using a DMA controller to transfer graphic data.

2 is a diagram schematically illustrating a transmission cycle of distributed graphic data in a DMA controller according to an embodiment of the prior art.

In the configuration of FIG. 1, a system using a DMA controller includes a CPU 2 for controlling data transfer and a calculation of data, a graphics controller 8 for performing graphics processing on a graphics display device, and a graphics controller. Graphic memory 10 for storing graphic data, main memory 6 for storing data on the system, data bus 12 for transferring data on the system, and main memory under control of the CPU 2 Or a DMA controller 4 for accessing the graphics memories 6, 10. When the CPU 2 wants to access a part of the storage area on the main memory 6 or the graphics memory 10, the CPU 2 displays the start position information of the storage area on the memory to be accessed and the number of storage areas to be accessed. Transfer to DMA controller 4 via 12). The DMA controller 4 accesses the start position of the storage area on the main memory 6 or the graphics memory 10 and continuously processes bitmap data by the number of data to be transmitted, thereby completing data transmission for one line. When transfer of one line is completed, the CPU 2 calculates the address to jump to and the head address of the next line, and transfers it to the DMA controller 4 via the data bus 12. The DMA controller 4 accesses the next line start position in the memory and continuously transmits bitmap data to complete the transfer of the corresponding line. On the other hand, in the CPU 2, a portion for calculating the storage area start position, the number of data to be transferred, the address to jump to, and the start position of the next line on the main memory 6 or the graphics memory 10 includes the CPU cycle of FIG. This is the case. In addition, the portion where the DMA controller 4 accesses the main memory 6 or the graphics memory 10 and continuously processes bitmap data line by line corresponds to the DMA cycle of FIG. Therefore, a CPU cycle and a DMA cycle are required to transfer a single line of data, and the CPU cycle and the DMA cycle are repeatedly performed as many as the number of graphic data lines to be transmitted. To complete.

As described above, in the case of transferring a part of graphic data, the conventional DMA controller requires CPU cycles and DMA cycles as many as the number of lines of the graphic data, and the data processing time becomes longer, thereby degrading the performance of the multimedia apparatus. There was a downside.

Accordingly, an object of the present invention is to provide a graphic data processing apparatus capable of continuously accessing graphic data from a memory to improve the processing speed of the graphic data.

1 is a block diagram of a system using a DMA controller to transfer graphic data.

2 is a diagram schematically illustrating a transmission cycle of distributed graphic data in a DMA controller according to an embodiment of the prior art.

3 is a flow chart illustrating a method for a DMA controller to access data in main memory in accordance with an embodiment of the present invention.

4 schematically illustrates the structure of bitmap data stored on a physical memory according to an embodiment of the present invention;

FIG. 5 is a diagram schematically illustrating a method for transferring graphic data from a first memory to a second memory by a DMA controller according to an embodiment of the present invention. FIG.

6 is a flow chart illustrating a method for transferring graphics data from a first memory to a second memory by a DMA controller according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

2: Central Processing Unit (CPU)

4: DMA controller

6: MAIN MEMORY

8: GRAPHIC CONTROLLER

10: GRAPHIC MEMORY

12: DATA BUS

14: Area where bitmap data is not written on physical memory

16: Area where bitmap data is recorded on physical memory

In order to achieve the above objects, the apparatus for processing graphic data of the present invention includes main control means for controlling data transmission and operation of data, a memory for storing data processed by the main control means in a bitmap manner, A storage element for continuously accessing data stored in any rectangular storage area on the memory in response to an access request of a control means and storing a head address of the image data stored in the memory, and width data of the image stored in the memory A memory for storing the height data, a memory for storing the height data of the image stored in the memory, a memory for storing the width data of the portion to be accessed, and a memory for storing the height data of the portion to be accessed. To store data on the device and its width And an auxiliary control means having a memory element for storing the height direction data of the portion to be accessed.

Other objects and features of the present invention other than the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

A preferred embodiment of the present invention will be described with reference to FIGS. 1 and 3 to 6.

FIG. 4 is a diagram schematically showing the structure of bitmap data stored on the physical memory according to an embodiment of the present invention, and shows the structure of the bitmap data stored on the first memory of FIG.

1, 3, and 4 will be described with reference to how the DMA controller accesses the graphic data on the first memory.

FIG. 1 is a block diagram of a system using a DMA controller to transfer graphic data. In the configuration of FIG. 1, the graphic data processing apparatus of the present invention includes a SAR (Source Address) for storing a storage area head position of an entire source image. Register (hereinafter referred to as SAR) register, SWW (Width of Source Whole image) register to store the width of the entire source image, and SHW (Heght of Source Whole) to store the height of the entire source image image; hereinafter referred to as SHW) register, SXR (Source X Coordinate; hereinafter referred to as SXR) register for storing the X coordinate of the partial source image to be transferred, and SYR (Source Y Coordinate) for storing the Y coordinate of the partial source image to be transferred. A SYR register, a SWP (Width of Source Partial image) register for storing the width of the partial source image, It further includes a weight of source partial image (SHP) register for storing the height of the partial source image, and a register for storing corresponding data in the destination.

FIG. 3 is a flowchart illustrating a method of accessing data in a first memory by a DMA controller according to an embodiment of the present invention. The embodiment of FIG. 3 is performed by the DMA controller of FIG.

When the DMA controller 4 wants to access the distributed bitmap data on the main memory, the CPU 2 uses the X coordinate (SXR) value of the partial source image, the Y coordinate (SYR) value of the partial source image, and the partial. The width (SWP) value of the source image, the height (SHP) value of the partial source image, the storage area leading position (SAR) value of the entire source image, the width (SWW) value of the entire source image, The data of each height SHW is transmitted to the DMA controller 4. (Step 34) The DMA controller 4 stores the storage area leading position (SAR) value and the partial source of the entire source image by the product of the width (SWW) value of the entire source image and the Y coordinate (SYR) of the partial source image. The X coordinate (SXR) value of the image is added to calculate the storage area head position (Axy) of the partial source image, and the X direction counter value and the Y direction counter value are initialized to one. (Step 36) In step 38, the DMA controller 4 accesses data corresponding to the storage area head position (Axy) value of the partial source image on the first or second memories 6 and 10. In step 40, the DMA controller 4 compares the X-direction counter value with the width (SWP) value of the partial source image and ends the access of the bitmap data for one line if the X-direction counter value is matched, and the X-direction counter value is In case of small, step 42 is performed. On the other hand, when the X-direction counter value is smaller than the width (SWP) value of the partial source image, the X-direction counter value and the storage area head position (Axy) value of the partial source image are increased by one. (Step 42) And steps 38 to 42 are repeated until the condition of step 40 is satisfied. In step 44, the DMA controller 4 compares the Y-direction counter value with the height (SHP) value of the partial source image and ends the access of the bitmap data on the first memory 6, if it matches. If the counter value is small, step 46 is performed. On the other hand, when the Y-direction counter value is smaller than the height (SHP) value of the partial source image, the DMA controller 4 determines the width (SWW) value of the entire source image and the partial value at the storage area (Axy) value of the partial source image. The difference of the width (SWP) value of the source image is added to obtain an address value to jump to. The memory head address value of the bitmap data of the next line is calculated by adding the value obtained by adding 1 to the Y-direction counter value to the address value to be jumped. Also, increase Y direction counter value by 1 and reset X direction counter value to 1. (Step 46) And steps 38 to 46 are repeated until the condition of step 44 is satisfied. In the above, steps 34 and 46 correspond to an area 14 in which bitmap data is not written in the first memory 6 of FIG. 5 and the remaining steps are described in FIG. It corresponds to the area 16 in which data is recorded on the memory 6.

In the same manner as described above, the DMA controller 4 uses the X coordinate (SXR) value of the partial source image, the Y coordinate (SYR) value of the partial source image, and the width (SWP) value of the partial source image. Data of the partial source image height (SHP), the storage source head position (SAR) value of the entire source image, the width (SWW) value of the entire source image, and the height (SHW) value of the entire source image By receiving the data, several lines of graphic data on the first memory 6 can be accessed in one DMA cycle.

5 and 6 will be described how the DMA controller transfers bitmap data from the first memory to the second memory.

FIG. 5 is a diagram schematically illustrating a method for transferring graphic data from a first memory to a second memory by a DMA controller according to an embodiment of the present invention. The embodiment of FIG. 5 is performed by the DMA controller of FIG. .

In the configuration of FIG. 5, the DMA controller uses the X coordinate (SXR1) value of the partial source image, the Y coordinate (SYR1) value of the partial source image, and the width (SWP1) of the partial source image to transfer bitmap data of the source memory. ), The height (SHP1) value of the partial source image, the storage area head position (SAR1) value of the entire source image, the width (SWW1) value of the entire source image, the height (SHW1) value of the full source image, Each register, the X coordinate (SXR2) value of the partial object image for processing bitmap data of the destination memory, the Y coordinate (SYR2) value of the partial object image, the width (SWP2) value of the partial object image, Registers of the height of the partial-purpose image (SHP2), the storage area head position (SAR2) of the full-purpose image, the width of the full-purpose image (SWW2), and the height (SHW2) of the full-purpose image. Equipped.

6 is a flowchart illustrating a method in which a DMA controller transfers graphic data from a first memory to a second memory according to an embodiment of the present invention, wherein the DMA controller 4 is connected to the second memory from the first memory 6. When the bitmap data is to be transferred to the memory 10, in the CPU 2, the head position SXR1 value of the entire source image on the first memory 6, the X coordinate SXR1 value of the partial source image, The Y coordinate (SYR1) value of the partial source image, the width (SWP1) value of the partial source image, the height (SHP1) value of the partial source image, the storage area head position (SAR1) value of the full source image, and the total source The width SWW1 value of the image, the data value of the height SHW1 value of the entire source image, the head position SXR2 value of the full-purpose image on the second memory 10, and the X-coordinate SXR2 of the partial-object image. ), The Y-coordinate (SYR2) value of the partial-object image, the width (SWP2) value of the partial-object image, and the partial-object image. The data value of each of the height (SHP2) value, the storage area head position (SAR2) value of the full-purpose image, the width (SWW2) value of the full-purpose image, and the height (SHW2) value of the full-purpose image are stored in the DMA controller ( 4) to transmit. (Step 48) In step 50, the DMA controller 4 determines the first position SAR1 of the entire source image storage area by a product of the width SWW1 of the entire source image and the Y coordinate SYR1 of the partial source image. Value and the X coordinate (SXR1) value of the partial source image, the storage area head position (Axy1) value of the partial source image on the first memory 6, the width (SWW2) of the full-purpose image, and the Y-coordinate of the partial-object image. The value of the product of (SYR2) is added to the head position (SAR2) of the whole object image and the X coordinate (SXR2) value of the partial object image to obtain the storage area head position (Axy2) value of the partial object image on the second memory 10. Calculate and initialize the X direction counter value and Y direction counter value to 1. The DMA controller 4 reads data corresponding to the storage area head position Axy1 of the partial source image from the first memory 6, and then stores the head position Axy2 of the partial-object image on the second memory 10 side. Write the data to the address corresponding to). (Steps 52 to 54) In step 56, the DMA controller 4 compares the X-direction counter value and the width (SWP) value of the partial source image and compares the bitmap data for one line with each other. The method reads from the first memory 6, writes to the second memory 10, and performs step 58 when the X-direction counter value is small. On the other hand, when the X direction counter value is small, the storage area head position (Axy1) value of the partial source image and the storage area head position (Axy2) value of the partial object image are each increased by 1, and the X direction counter value is increased by 1, respectively. Let's do it. (Step 58) Then, steps 52 to 58 are repeatedly performed until the condition of step 56 is satisfied. In step 60, the DMA controller 4 compares the Y-direction counter value with the height (SHP) value of the partial source image and reads bitmap data from the first memory 6 when the value matches and the second memory. After writing to (10), if the data transfer is completed and the Y-direction counter value is small, step 62 is performed. On the other hand, when the Y-direction counter value is small, the DMA controller 4 differs between the width (SWW1) value of the entire source image and the width (SWP1) value of the partial source image from the storage area head position (Axy1) value of the partial source image. In addition, the difference between the address to jump on the first memory 6, the start position (SWW2) value of the full-purpose image and the height (SWP2) value of the partial-object image is added to the storage area head position (Axy2) value of the partial-object image. In addition, after obtaining an address value to jump on the second memory 10, a value of 1 in the Y direction is added to each address value to be jumped to calculate the memory head address value of the bitmap data of the next line. Also, increase Y direction counter value by 1 and reset X direction counter value to 1. (Step 62) Then, steps 52 to 62 are repeatedly performed until the condition of step 60 is satisfied.

In the same manner as described above, the DMA controller 4 uses the CPU 2 to determine the X coordinate SXR1 value of the partial source image on the first memory 6, the Y coordinate SYR1 value of the partial source image, and the partial source image. Width (SWP1) value, the height of the partial source image (SHP1), the storage area head position (SAR1) value of the entire source image, the width (SWW1) value of the entire source image, and the height of the entire source image ( SHW1) value, the first position SXR2 value of the whole object image on the second memory 10, the X coordinate SXR2 value of the partial object image, and the Y coordinate SYR2 value of the partial object image. , The width of the partial-object image (SWP2), the height of the partial-object image (SHP2), the storage area leading position (SAR2) of the whole-object image, the width of the whole-object image (SWW2), and the total-object Receives the data value of each height SHW2 value of the image and transfers the bitmap data from the first memory 6 to the second message in one DMA cycle. Li can transport up (10). In the same manner as above, the DMA controller 4 may transfer graphic data from the first memory 6 to the output device.

As described above, the graphic data processing apparatus of the present invention has an advantage of speeding up the processing speed of graphic data.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (1)

In the graphic data processing apparatus, Main control means for controlling data transmission and for calculating data; A memory for storing data processed by the main control means in a bitmap manner; A memory element for storing the head address of the memory stored bitmap data for continuously accessing data stored in any rectangular storage area on the memory in response to an access request of the main control means, and the memory stored in the memory; A storage element for storing the width data of the bitmap data, a storage element for storing the height data of the bitmap data stored in the memory, a storage element for storing the width data of the long-term storage area to be accessed; An auxiliary control means having a memory element for storing the height data of the long-term storage area to be accessed, a memory element for storing the address of the storage area of the bitmap data to be accessed, and a memory element for storing the number of jumps Graphic data processing apparatus comprising a.