KR19990009107A - Composite semiconductor device having test pad merging means - Google Patents

Abstract

MML (Merged Memory with Logic) is disclosed in which the number of test pads is small and the test time is reduced. The MML may include a memory block, a logic block, and a test pad merging means having improved general purpose synchronous DRAM. In particular, the test pad merging means efficiently merges the test pads to reduce the test pad of the memory block and reduce the test time, and at least one of a test command input unit, a test address input unit, and a test data input / output unit. Equipped. The test command input unit receives first, second, and third input signals externally applied during a test, and includes a low address strobe signal and a column address of a bank selected by a bank selection signal among a plurality of banks of the memory block. A strobe signal and a write enable signal are respectively transmitted to the memory block. The test address input unit is commonly connected to a low address pass and a column address pass of the memory block to control the low address and the column address of the memory block externally during a test. The test data input / output unit is commonly connected to the input data path and the output data path of the memory block and inputs and outputs data through one path commonly connected during a test.

Description

Composite semiconductor device having test pad merging means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which logic and synchronous DRAM (hereinafter referred to as SDRAM) are merged into one chip. In particular, the test pads are efficiently merged. It relates to an MML having a test pad merging means.

In general, systems used for information processing and communication, etc. are configured to include logic semiconductor devices that perform control, operation, and interface functions, and memory semiconductor devices that store data. Conventionally, logic semiconductor devices and memory semiconductor devices have been used separately for a system, but in recent years, logic semiconductor devices and memory semiconductor devices have been used in accordance with the development of semiconductor design technology and manufacturing technology and also in accordance with the demand for cost reduction of the system. Research continues to integrate on one chip. Of course, in the past, ASIC (Application Specific Integrated Circuit) has been a common technology for integrating logic semiconductor devices and small-capacity SRAMs on a single chip. In recent years, a lot of researches have been made on the integration technology.

However, in a conventional SDRAM having a plurality of banks, for example, two banks, common command signals, that is, one low address strobe signal ( ), One column address strobe signal ( ), And one write enable signal ( 2 banks are controlled together, and the low and column addresses are input to the same address input pins. Thus, when the conventional SDRAM is merged into one chip together with logic as it is, MML is designed, Performance degrades the overall performance of the MML.

Accordingly, as shown in the block diagram of the MML shown in FIG. 1, the conventional general-purpose SDRAM includes an improved memory block 113 and a logical block 111. More specifically, in the memory block 113 of the MML, in order to improve the performance of the conventional general-purpose SDRAM, the input / output data paths and the row / column address paths, which are bound to each other by one pad in the general-purpose SDRAM, are used as separate paths. Are separated. That is, one input / output data path in the conventional general-purpose SDRAM is divided into input data DIN [0: k] paths and output data DOUT [0: k] paths, and one row / The column address path is divided into a low address (RADDR [0: i]) path and a column address ([CADDR [0: j]) path. In the memory block 113 of the MML, one low address strobe signal (commonly used for a plurality of banks, for example, two banks (A bank and B bank)) is used. ) Path, one column address strobe signal ( ) Path, and one write enable signal ( ) Paths are separated for each bank. That is, one low address strobe signal ( The path is a low address strobe signal for the A bank. a) the low address strobe signal for the Path and B banks ( b) separated by paths; In addition, one column address strobe signal ( The path is the column address strobe signal for the A bank. a) the column address strobe signal for the Path and B banks ( b) separated by paths; In addition, one write enable signal ( ) Path is the write enable signal for the A bank. a) the write enable signal for the pass and B banks ( b) separated by paths;

However, in order to directly test the memory block 113 of the MML, test pads that may be directly connected to an external tester should be connected to the paths of all the signals. However, since the paths of all the signals are separated from each other as described above, when the test pads are connected to all of them, the number of pads becomes excessively large, thus increasing the chip size, especially in parallel in the tester. This reduces the number of chips you can test. This has the disadvantage of reducing the number of chips that can be tested in unit time, resulting in a long overall test time.

It is therefore an object of the present invention to provide an MML in which the number of test pads is small and the test time is reduced.

1 is a block diagram of a typical MML.

2 is a block diagram of an MML according to an embodiment of the present invention.

The MML according to the present invention for achieving the above object is characterized in that the general-purpose SDRAM is provided with an improved memory block and logic block, and test pad merging means for efficiently merging the test pads.

The memory block includes a plurality of banks, each bank independently controlled by a respective low address strobe signal, a respective column address strobe signal, and a respective write enable signal. In addition, in the memory block, the low address and the column address of the banks are independently applied through different paths, and a path through which input data is input and a path through which output data is output are different from each other.

The logic block generates the respective low address strobe signal, the respective column address strobe signal, the respective write enable signal, the low address and the column address, and the input data and output data to the memory block. And give each other.

The test pad merging means is for efficiently merging test pads to reduce the test pad of the memory block and reduce the test time, and at least one of a test command input unit, a test address input unit, and a test data input / output unit. It is provided. Here, the test command input unit receives first, second, and third input signals externally applied during a test, and includes a low address strobe signal and a column address strobe of a bank selected by a bank selection signal among the plurality of banks. A signal and a write enable signal to the memory block. The test address input unit is commonly connected to the low address path and the column address path to control the low address and the column address externally during a test. The test data input / output unit is commonly connected to the input data path and the output data path to input / output data through one path commonly connected during a test.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an MML according to an embodiment of the present invention.

Referring to FIG. 2, the MML is a test pad for efficiently merging test pads to reduce the test time of the memory block 213 and logic block 211 and the memory block 213 in which the general-purpose SDRAM is improved. Merging means 215a, 215b, 215c are provided.

The memory block 213 is an improved general-purpose SDRAM, and includes two banks, for example, a bank A and a bank B, and one low-address strobe signal path commonly used for the banks A and B in the general-purpose SDRAM. One column address strobe signal path and one write enable signal path are separated for each bank. Accordingly, the respective banks have respective low address strobe signals (command signals). a, b), each column address strobe signal ( a, b), and each write enable signal ( a, independently controlled by b). That is, the A bank is the low address strobe signal ( a), the column address strobe signal ( a) and the write enable signal ( controlled by a), and the B bank receives the low address strobe signal ( b), the column address strobe signal ( b), and the write enable signal ( controlled by b).

In addition, the row / column address paths, which are bound to each other by one pad in the general-purpose SDRAM, are separated into separate low address and column address paths in the memory block 213. Accordingly, the low address RADDR [0: i] and the column address CADDR [0: j] of the memory block 213 are generated in the logical block 211 and the memory block (2) through the separate path. 213). In addition, the input / output data paths that are bound to each other by one pad in the general-purpose SDRAM are also separated into separate paths in the memory block 213. Accordingly, the input data DIN [0: k] for the memory block 213 is generated in the logic block 211 and input to the memory block 213 through the input data path, and the memory block ( The output data DOUT [0: k] of the 213 is read from the memory block 213 and transferred to the logical block 211 through a separate output data path.

The logic block 211 may be configured in various logic circuits according to an application, and typically has a control, arithmetic, and interface function, and the low address strobe signals ( a, b), the column address strobe signals ( a, b), and the write enable signals ( a, b) and the input data DIN [0: k] and the output data DOUT [0: k] are exchanged with the memory block 213.

The test pad merging means 215a, 215b, 215c includes a test command input unit 215a, a test address input unit 215b, and a test data input / output unit 215c. If necessary, only one of the test command input unit 215a, the test address input unit 215b, and the test data input / output unit 215c may be provided, or both may be provided.

In more detail, the test command input unit 215a receives the first, second, and third input signals TIN1, TIN2, and TIN3 that are applied from the outside during the test, and is configured by the bank selection signal BS. The low address strobe signal for the selected bank ( a or b), column address strobe signal ( a or b), and write enable signal ( a or and b) to each of the memory blocks 213. That is, the test command input unit 215a may include first, fourth, and fourth through which the first, second, third input signals TIN1, TIN2, TIN3, and the bank selection signal BS are applied to the outside during a test. The low address strobe signal of the bank selected by the test pads 5a1, 5a2, 5a3, 5a4 and the bank select signal BS applied to the fourth test pad 5a4. a or b) a first demultiplexer 5a5 which receives the first input signal TIN1 applied to the first test pad 5a1 and transmits the first input signal TIN1 to the memory block 213 and the bank selection signal BS. Column address strobe signal of the selected bank ( a or b) a second demultiplexer 5a6 which receives the second input signal TIN2 applied to the second test pad 5a2 and transmits it to the memory block 213 and the bank selection signal BS. The write enable signal for the selected bank ( a or and b) a third demultiplexer 5a7 which receives the third input signal TIN3 applied to the third test pad 5a3 and transmits the third input signal TIN3 to the memory block 213.

The test address input unit 215b includes a fifth test pad 5b1 that is commonly connected to the low address path and the column address path and to which an address TADDR is externally applied during a test, and that the address TADDR is tested. The low address RADDR [0: i] and the column address CADDR [0: j] are controlled by the "

The test data input / output unit 215c buffers the output data of the output data path only when the data is read in response to the control signal READ, and buffers the input data when the data is written. And a sixth test pad 5c3 commonly connected to an output terminal of the output buffer 5c1 and an input terminal of the input buffer 5c2. Data is input and output through the sixth test pad 5c3. The control signal READ is a signal generated from the memory block 213.

Therefore, in the MML including the test pad merging means, the two low address strobe signal paths, the two column address strobe signal paths, and the two write enable signal paths are respectively defined by the first, second, and second enable address signal paths of the test command input unit 215a. The number of test pads is reduced by merging into the first, second, and third test pads 5a1, 5a2, 5a3 by the second and third demultiplexers 5a1, 5a2, 5a3, respectively. In addition, the low address path and the column address path are merged into one fifth test pad 5b1 of the test address input unit 215b, thereby reducing the number of test pads for address input by half. In addition, the input data path and output data path are merged into the sixth test pad 5c3 of the test data input / output unit 215c, thereby reducing the number of test pads for data input / output by half.

As described above, the present invention has been limited to one embodiment, but not limited thereto. It is obvious that various modifications to the present invention can be made by those skilled in the art within the scope of the spirit of the present invention. .

In conclusion, the MML according to the present invention has the advantage of reducing the number of test pads and also reducing the test time by providing test pad merging means for efficiently merging test pads.

Claims (16)

A plurality of banks, wherein each bank is independently controlled by a respective low address strobe signal, a respective column address strobe signal, and a respective write enable signal, and the low address and the column address of the banks are different; A memory block which is independently applied through a path and has a path from which input data is input and a path from which output data is output; Logic for generating each of the low address strobe signals, the respective column address strobe signals, the respective write enable signals, and the low addresses and column addresses, and exchanging the input data and output data with the memory block. Block; And A test pad merging means for efficiently merging test pads to reduce a test time of the memory block; The test pad merging means, It receives the first, second, and third input signals externally applied during the test, and selects a low address strobe signal, a column address strobe signal, and a write enable signal of a bank selected by a bank selection signal among the plurality of banks. And a test command input unit for transmitting the test command input unit to the memory block. The semiconductor device of claim 1, wherein the memory block is a DRAM. The test command input unit of claim 1, wherein the test command input unit comprises: first to fourth test pads to which the first, second, third input signals, and the bank selection signal are externally applied during a test; A first demultiplexer receiving the first input signal applied to the pad and transferring the first input signal to the memory block as a low address strobe signal of a bank selected by the bank selection signal applied to the fourth test pad, and the second test pad A second demultiplexer which receives the second input signal applied to the second block and transfers it to the memory block as a column address strobe signal of a bank selected by the bank selection signal applied to the fourth test pad, and the third test pad; Receives the third input signal applied to the write-in of the bank selected by the bank selection signal applied to the fourth test pad A block signal semiconductor device comprising the third de-multiplexer for transmitting to said memory block. A plurality of banks, wherein each bank is independently controlled by a respective low address strobe signal, a respective column address strobe signal, and a respective write enable signal, and the low address and the column address of the banks are different; A memory block which is independently applied through a path and has a path from which input data is input and a path from which output data is output; Logic for generating each of the low address strobe signals, the respective column address strobe signals, the respective write enable signals, and the low addresses and column addresses, and exchanging the input data and output data with the memory block. Block; And A test pad merging means for efficiently merging test pads to reduce a test time of the memory block; The test pad merging means, And a test address input unit connected to the low address path and the column address path to control the low address and the column address externally during a test. The semiconductor device of claim 4, wherein the memory block is a DRAM. The semiconductor device of claim 4, wherein the test address input unit comprises a fifth test pad connected to the low address path and the column address path and to which an address is externally applied during a test. A plurality of banks, wherein each bank is independently controlled by a respective low address strobe signal, a respective column address strobe signal, and a respective write enable signal, and the low address and the column address of the banks are different; A memory block which is independently applied through a path and has a path from which input data is input and a path from which output data is output; Logic for generating each of the low address strobe signals, the respective column address strobe signals, the respective write enable signals, and the low addresses and column addresses, and exchanging the input data and output data with the memory block. Block; And A test pad merging means for efficiently merging test pads to reduce a test time of the memory block; The test pad merging means, And a test data input / output unit commonly connected to the input data path and the output data path to input and output data through one path commonly connected during a test. 8. The semiconductor device of claim 7, wherein the memory block is a DRAM. 8. The test data input / output unit of claim 7, wherein the test data input / output unit buffers the output data of the output data path only when data is read in response to a control signal and buffers the input data when the data is written and outputs the buffered data to the input data path. A bidirectional buffer comprising an input buffer, a sixth test pad commonly connected to an output end of the output buffer, and an input end of the input buffer, and wherein the data is input and output through the sixth test pad during a test; Device. The semiconductor device of claim 9, wherein the control signal is a signal generated from the memory block. A plurality of banks, wherein each bank is independently controlled by a respective low address strobe signal, a respective column address strobe signal, and a respective write enable signal, and the low address and the column address of the banks are different; A memory block which is independently applied through a path and has a path from which input data is input and a path from which output data is output; Logic for generating each of the low address strobe signals, the respective column address strobe signals, the respective write enable signals, and the low addresses and column addresses, and exchanging the input data and output data with the memory block. Block; And A test pad merging means for efficiently merging test pads to reduce a test time of the memory block; The test pad merging means, It receives the first, second, and third input signals externally applied during the test, and selects a low address strobe signal, a column address strobe signal, and a write enable signal of a bank selected by a bank selection signal among the plurality of banks. A test command input unit for transmitting to the memory block, respectively; A test address input unit commonly connected to the low address path and the column address path to externally control the low address and the column address during a test; And a test data input / output unit commonly connected to the input data path and the output data path to input and output data through one path that is commonly connected during a test. The semiconductor device of claim 11, wherein the memory block is a DRAM. The apparatus of claim 11, wherein the test command input unit comprises: first to fourth test pads to which the first, second, third input signal, and the bank selection signal are respectively applied during a test; A first demultiplexer receiving the first input signal applied to the pad and transferring the first input signal to the memory block as a low address strobe signal of a bank selected by the bank selection signal applied to the fourth test pad, and the second test pad A second demultiplexer which receives the second input signal applied to the second block and transfers it to the memory block as a column address strobe signal of a bank selected by the bank selection signal applied to the fourth test pad, and the third test pad; Receives the third input signal applied to the write-in of the bank selected by the bank selection signal applied to the fourth test pad And a third demultiplexer which transmits to the memory block as an enable signal. The semiconductor device of claim 11, wherein the test address input unit includes a fifth test pad connected to the low address path and the column address path and to which an address is externally applied during a test. The method of claim 11, wherein the test data input / output unit outputs to the input data path by buffering an output buffer for outputting the output data of the output data path only when data is read in response to a control signal and input data when writing data. A bidirectional buffer comprising an input buffer, a sixth test pad commonly connected to an output end of the output buffer, and an input end of the input buffer, and wherein the data is input and output through the sixth test pad during a test; Device. The semiconductor device of claim 15, wherein the control signal is a signal generated from the memory block.