JPH11260100A - Test method for memory element in mml device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for facilitating DRAM test of an MML device and shortening the test time using an ordinary DRAM test equipment and test system. SOLUTION: The method for testing a DRAM 30 in an MML device comprises a first stage for inputting a test signal through a test pin, a step for applying a plurality of control signals, address signals and data externally to a multiplexer 10, and a step for inputting internal control signals, internal addresses and internal data from the multiplexer 10 to the input buffer of the DRAM 30 and a processor 20. When the test signal is enable, the DRAM 30 is tested by each signal passed through the input buffer. When the test signal is disable, the DRAM 30 and the processor 20 are operated entirely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MML in which a memory element and a logic circuit are implemented on a single chip, and more particularly to an MML.
The present invention relates to a test method for facilitating a DRAM test in an ML and shortening a test time.

[0002]

2. Description of the Related Art At present, the processing speed of a central processing unit (CPU) and other processors for special purposes is developed day by day.
On the other hand, the access time of DRAM has been improved by about 10% per year, while the access time difference between the processor and the DRAM has been increasing.

Recently, in order to greatly increase the data bandwidth and reduce the RC delay due to the bus capacitance between pins and the load capacitance of pins, an MML (Merged Memory and MML) in which a memory element and a logic circuit are mounted on one chip.
Logic (hereinafter, referred to as MML) device is provided.

[0004]

As described above, when a memory element and a logic circuit are mounted on one chip, it is not easy to test only the memory element. Further, the test cost is significantly increased as compared with the case of testing an existing general memory device.

Generally, a memory element in an MML, for example, a DR
There are various ways to test AM. Normal data transmission method between logic circuit and DRAM (internally defined standard)
After determining the data bandwidth and the like, there is a problem in that a test method for the DRAM must be selected in consideration of each of these cases.

An object of the present invention is to provide a test method capable of facilitating a DRAM test in an MML device and shortening the test time in order to solve these problems. And a test apparatus for testing the DRAM.

[0007]

According to the first aspect of the present invention,
A logic circuit with a processor and a method for testing a memory device in an MML device including the memory device, the method comprising: providing the memory device and multiplexer means for controlling operation of the processor; Selectively operating the memory device and the processor according to a mode signal to be performed. If the mode signal is enabled, a test mode for operating only the memory device is performed, and the control signal is disabled. If enabled, the DRAM
And a processor mode in which the processor operates together.

According to the first aspect of the present invention, a logic circuit including a processor and an MM including a memory element
A method for testing a memory device in an L device, the method comprising: providing the memory device; multiplexer means for controlling operation of the processor; and a mode signal output from the multiplexer, wherein the memory device and the processor are provided. A test mode for operating only the memory element if the mode signal is enabled, and the DRAM and the processor if the control signal is disabled. A cooperating processor mode is performed.

According to a fifth aspect of the present invention, there is provided a method for testing a memory device in an MML device having a memory device and a logic circuit, wherein a plurality of external control signals, address signals, and data are received; Generating a test signal by combining a plurality of control signals; applying the plurality of external control signals, address signals, data and the test signal to multiplexer means; responding to the test signal; Inputting an internal control signal, an internal address, and internal data output from the multiplexer means to an input buffer and a logic circuit of a memory element, and when the test signal is in an enabled state, by using each signal passed through the input buffer. When the memory device is tested and the test signal is disabled,
The memory device and the logic circuit are all operated.

According to the fifth aspect of the present invention, in the method for testing a memory device in an MML device having a memory device and a logic circuit, receiving a plurality of external control signals, address signals, and data. Generating a test signal by combining the plurality of control signals; and the plurality of external control signals, an address signal,
Applying data and the test signal to a multiplexer means, and inputting an internal control signal, an internal address, and internal data output from the multiplexer means to an input buffer and a logic circuit of a memory element in response to the test signal. When the test signal is in the enable state, the memory element is tested by each signal passing through the input buffer, and when the test signal is in the disable state, all of the memory element and the logic circuit operate.

Therefore, the DRAM in the MML device can be tested by the same test method as that for testing a general DRAM. That is, according to the test method of the present invention, the test can be performed according to the existing method using the existing DRAM test equipment, which is very economical and convenient.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an MML device for applying the test method of the present invention.

As shown in FIG. 1, the MML device includes a multiplexer 10, a processor 20, and a DRAM 30. The function of the multiplexer 10 will be described in detail with reference to a functional block diagram shown in FIG.

Control signals, addresses, and data necessary for the operation of the DRAM 30 are applied to the MML device via pads. Control signals applied to the pad include / RAS, / CAS, / WE, and / OE shown in FIG.
And so on. The functions of these pads are the same as the functions of the pins mounted when a package of an existing DRAM is manufactured. That is, it is a pad to which an electrostatic discharge (Electro Static Discharge) circuit is added.

Control signals, addresses, and data externally applied to the MML device are applied to the multiplexer 10. The multiplexer 10 outputs an internal control signal, an internal address, and internal data applied to the DRAM 30. The output signal of the multiplexer 10 is
0 and selectively applied to the processor 20.

The processor mode and the DRAM test mode which are the test methods of the present embodiment will be described below.

In the case of the processor mode, the processor 2
The control of the output signal from 0 causes the DRAM 30 to operate. At this time, the output signal from the processor 20 is applied to the DRAM 30 via the multiplexer 10.

In the DRAM test mode, external control signals, addresses, and data are directly applied to the DRAM 30. In this case, external control signals, addresses, and data are transmitted through the multiplexer 10 to the DRA.
Applied to M30.

In order to select one of the processor mode and the DRAM test mode, TES
A control signal is applied via the T pin. For example, DRA
A high voltage (1) is applied to the TEST pin in the M test mode, and a low voltage (0) in the processor mode.
Is applied to the TEST pin.

FIG. 2 shows the multiplexer 10 shown in FIG.
FIG. 3 is a block diagram showing the functions of the above. As shown in FIG. 2, the multiplexer 10 includes a control signal synthesizing unit 11,
Address signal synthesizing section 12 and read data synthesizing section 13
And a write data synthesizing unit 14.

The control signal synthesizing unit 11 receives an external / RA
S, / CAS, / WE, / OE, etc.
DR for AS, internal / CAS, internal / WE, internal / OE, etc.
It has a function of outputting to the control signal buffer 31 in the AM 30.

The address signal synthesizing section 12 receives an external address (A0, A1,...
It has a function of outputting an internal address to the address buffer 32 in the M30.

The read data synthesizing unit 13 is provided in the DRAM 3
It has a function of outputting read data output from 0 to the processor 20 or the data output buffer 33 of the MML device.

The write data synthesizing section 14 has a function of outputting write data from the processor 20 or the data input buffer 34 of the MML device to the DRAM 30.

FIGS. 3A and 3B show the multiplexer 1
FIG. 9 is a diagram for schematically explaining an operation of a zero. This figure 3
As shown in (a), an external signal (TTL) applied through a pad is applied to the multiplexer 10. The external signal applied to the multiplexer 10 is controlled by the processor 20 and applied to an input buffer of the DRAM 30. Further, as shown in FIG. 3B, data output from the output buffer of the DRAM 30 by a read operation or the like is applied to the multiplexer 10. The data applied to the multiplexer 10 is transmitted to a processor or an output buffer.

The circuit configuration of the multiplexer 10 can be realized by using a transmission gate or an inverter, and a corresponding configuration example is the same as that shown in FIGS.

In FIG. 4, when the test signal is 1, the data is transmitted to the data-test terminal to perform the DRAM test mode. DRAM test mode, DRAM
Only 30 is enabled, and processor 20 is disabled. If the test signal is 0, the data is transmitted to the data-pro terminal, and the processor operates normally. In this case, both the DRAM 30 and the processor 20 maintain the enabled state.

5 and 6, only one of the input signals in1 and in2 is transmitted to the output terminal out according to the level of the test signal. One of the input signals in1 and in2 indicates the DRAM test mode, and the other indicates the processor mode.

The test signal shown in FIG. 4 is a signal directly applied through a test pin, and the input signals shown in FIGS. 5 and 6 are signals generated by combining control signals from the outside. That is,
By applying a control signal obtained by combining external signals to the multiplexer 10, a test mode for the DRAM can be set.

The operation in the DRAM test mode is summarized as follows. Step 1. Enable the test signal. Step 2. An external control signal, address signal, and data are applied to the multiplexer 10. Step 3. The multiplexer inputs the internal control signal, the internal address, and the internal data to the input buffer of the DRAM 30. Step 4. The signals and the like that have passed through the input buffer are transferred to the DRAM 3 in the same manner as when a normal DRAM is operated.
0 is operated to perform a read operation or a write operation.

The above steps are performed, and the general DRA
The DRAM 30 in the MML device can be tested by the same test method as when testing M. That is, according to the test method of the present invention, the test can be performed according to the existing method using the existing DRAM test equipment, which is very economical and convenient.

The preferred embodiments and the like of the present invention have been disclosed for the purpose of illustration, and those skilled in the art can make various modifications, changes, additions, etc. within the spirit and scope of the present invention. Yes, such modifications, changes, etc. should be considered as belonging to the following claims.

[0033]

According to the method of testing a memory element in an MML device of the present invention, a DRAM in an MML device can be tested by the same test method as that for testing a general DRAM. That is, according to the test method of the present invention, the test can be performed according to the existing method using the existing DRAM test equipment, which is very economical and convenient.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an MML device including a memory device and a logic circuit according to the present invention.

FIG. 2 is a block diagram showing a functional configuration of a multiplexer 10 of FIG.

3 shows a data input state (FIG. 3A) and a data output state (FIG. 3B) of the multiplexer 10 of FIG.
FIG.

FIG. 4 is a diagram showing a specific circuit configuration example of the multiplexer 10 of FIG.

FIG. 5 is a diagram showing a specific circuit configuration example of the multiplexer 10 of FIG. 1;

FIG. 6 is a diagram showing a specific circuit configuration example of the multiplexer 10 of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Multiplexer 20 Processor 30 DRAM

Claims (6)

[Claims] 1. A method of testing a memory device in an MML device including a logic circuit having a processor and a memory device, the method comprising: providing the memory device and multiplexer means for controlling operation of the processor. A mode signal output from the multiplexer,
Selectively operating the memory device and the processor, a test mode for operating only the memory device is performed when the mode signal is enabled, and the test mode is performed when the control signal is disabled. A method for testing a memory device in an MML device, wherein a processor mode in which a DRAM and a processor operate together is performed. 2. The MM according to claim 1, wherein the multiplexer receives an externally applied test signal via a test pin and generates the mode signal.
Test method for a memory element in an L device. 3. The multiplexer means receives a plurality of externally applied control signals and generates the mode signal, wherein the plurality of control signals are / RAS, / CAS,
2. The method as claimed in claim 1, further comprising the signals / WE and / OE. 4. An MML having a memory element and a logic circuit
A method of testing a memory element in a device, a first step of inputting a test signal via a test pin, a step of applying a plurality of external control signals, address signals, and data to multiplexer means; An internal control signal output from the means,
Inputting an internal address and internal data to an input buffer and a logic circuit of the memory element, and when the test signal is enabled, the memory element is tested by each signal passing through the input buffer;
A method of testing a memory device in an MML device, wherein when the test signal is disabled, all of the memory device and the logic circuit operate. 5. An MML having a memory element and a logic circuit.
A method for testing a memory device in an apparatus, comprising: receiving a plurality of external control signals, address signals, and data; generating a test signal by combining the plurality of control signals; Applying a plurality of control signals, address signals, data, and the test signal to a multiplexer means, and responding to the test signal, outputting an internal control signal, an internal address, and internal data output from the multiplexer means to a memory element. Inputting to an input buffer and a logic circuit, wherein when the test signal is enabled, a memory element is tested by each signal passing through the input buffer;
A method of testing a memory device in an MML device, wherein when the test signal is disabled, all of the memory device and the logic circuit operate. 6. The method according to claim 1, wherein the plurality of control signals are / RAS, / C
6. The method as claimed in claim 5, further comprising an AS, / WE, and / OE signal.