KR19990061022A - Integrated chip of memory and logic and its test method - Google Patents

Abstract

The present invention relates to MML (MML) that implements memory and logic in one chip. In particular, signals from outside and internally made signals can be used to facilitate DRAM test in MML and reduce test time. A DRAM test apparatus having a multiplexer 10 for controlling and selecting the signals, and selecting and outputting the mixed signals in a test mode or a processor mode with a small time delay of the mixed signals; A processor 20 that executes processing of control signals, addresses, and data when a processor mode is selected according to the output of the multiplexer 10; And a DRAM 30 storing data processed from the processor 20 or data input from the outside according to the output of the multiplexer 10, and an integrated chip of memory and logic and a test method thereof.

Description

Integrated chip of memory and logic and its test method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to MML (MML), which implements memory and logic in one chip. In particular, an integrated chip of memory and logic and a test method thereof for facilitating DRAM test in MML and reducing test time. It is about.

The processing speed of today's CPUs and other special-purpose processors has grown from day to day, with CPUs increasing about 60% a year since 1986. In this case, the access time is improved by about 10% a year, and the gap between the processor and the DRAM is increasing.

Recently, memory (DRAM) and logic have been implemented to significantly increase the data band width and to reduce the RC delay caused by the chip's bus line and pin's load cap. MML (Merged Memory and Logic, MML) method to implement on the chip has been tried.

However, when DRAM and logic are implemented in one chip, it is not easy to test DRAM and test time is greatly increased, and it is easy to imagine that there will be a huge increase in cost compared to conventional DRAM.

MML has recently been attempted, and there is no specific DRAM test method for MML.

According to the logic part that performs a specific function, the method of exchanging data between the logic and the DRAM (internal specification) and the data bandwidth are determined, and the DRAM test has to be limited in each case.

Accordingly, the present invention was devised to solve the above-mentioned problems, and provides an integrated chip and a test method thereof for facilitating DRAM test in MML and reducing test time. The purpose is.

1 is a block diagram of an integrated chip of memory and logic according to the present invention;

2 is a detailed configuration diagram of the multiplexer of FIG. 1;

3 is an exemplary diagram for describing input and output of a multiplexer;

4 is an exemplary embodiment of a control signal generation circuit for controlling a DRAM;

5 is an exemplary configuration diagram of a multiplexer.

Explanation of symbols for main parts of the drawings

10: multiplexer 20: processor

30: DRAM

The present invention for achieving the object as described above, and outputs the selected mode in the test mode or processor mode, while controlling (muxing) the externally incoming signals and internally generated signals, while reducing the time delay of the mixed signal A DRAM test apparatus having a multiplexer (10); A processor 20 that executes processing of control signals, addresses, and data when a processor mode is selected according to the output of the multiplexer 10; And a DRAM 30 for storing data processed from the processor 20 or data input from the outside according to the output of the multiplexer 10.

The present invention relates to a method for facilitating a DRAM test in MML and reducing a test time. The DRAM test in MML is made to use a conventional DRAM test method and test equipment as it is. Can be.

To make this possible, circuits for this must be added from the DRAM design stage, which adds several multiplexer circuits and a mode-division circuit that separates the processor mode when the processor is running and the test mode for DRAM test only. Only possible.

The operating principle of the DRAM test method in the chip in which the memory and the logic are implemented according to the present invention will be described in detail as follows.

FIG. 1 is a schematic block diagram of the present invention. As shown in FIG. 1, / RAS, / CAS, / WE, / OE and control signals required for operating the DRAM 30 are externally applied. Make a pad for this so you can.

This is the same as pulling the pin to make a package on a conventional DRAM.

That is, it is a pad to which an electrostatic discharge (ESD) circuit is added.

Inside the MML chip, control signals / RAS, / CAS, / WE, / OE and addresses for controlling the DRAM 30 are internally generated, and processed data is stored in the DRAM 30 according to the function of the processor 20. The data can be stored or received from the outside (for example, a CD-ROM).

Therefore, in the processor mode, the processor 20 receives the processed signal and the processed data from the processor 20 according to the address case, and in the DRAM test mode, the control signal, the address, and the data applied from the outside are used. Add the multiplexer 10 for this to receive and use.

One control signal is required to distinguish the processor mode from the DRAM test mode. An external pin is also created for this signal and forced to Vdd in the test mode and grounded to the ground in the processor mode. How to do this is possible.

In this way, the signals from the outside and internally generated and sent to the DRAM 30 are controlled and muxed, and the selected signals are stored in the respective control signal buffers 31, the address buffers 32 and the data of the DRAM 30. Effective placement of internal bus lines is important so that delays can be delivered to the output buffer 33 and the data input buffer 34 with a low delay.

The control signals and addresses for controlling the DRAM 30 are signals that are used globally to operate each block in the DRAM 30, so that the control signals generating circuits for controlling each block are possible. Ideally, they have a small delay and are distributed in the form of symmetrical bus lines in each block.

To do this, the positions of the control signal (/ RAS, / CAS, / WE, / OE) lines, address signal (A0 ... An) lines, and data (DQ0 ... DQn) lines cross the center of the chip. The form is the most ideal.

One embodiment thereof is as shown in FIG. 4.

In addition, metal lines with low resistance are used to reduce the RC delay of these overall lines.

In the case of MML, even the existing 2 metals to 3 metals, 4 metals, and 5 metals can be configured according to the process, and thus it may be configured in a small area.

The multiplexer 10 circuit can be implemented using a transmission gate or a tri-state inverter, one embodiment of which is shown in FIG.

The operation process in the test mode is as follows.

1. First, enable the test signal.

2. In the case of control signals, address signals, and writes from the outside, data is applied to the DRAM through a pin connected to the outside.

3. External signals are sent to each input buffer via a multiplexer.

At this time, the signals entering the DRAM area are sent to each input buffer via a signal bus line properly arranged to minimize the RC delay as in the case of FIG.

4. Each signal that passes through the buffer is read or written by operating the DRAM in the same way as a normal DRAM.

Through the above process, the DRAM is tested in the same manner as when the general DRAM is tested.

As described in detail above, in the present invention, when the test mode is designed separately as in the present invention, the existing DRAM test equipment can be used to test according to the existing method, which is added in terms of cost and time. It is convenient to test without a head.

In addition, the circuit required to add the test mode is possible with only a few simplex multiplexers. Even in the design aspect, the case where the signal line composed of properly arranged metal lines is 50 lines as compared to the conventional off-chip configuration is assumed. With a pitch of 2.4um, only a width of 120um is possible.

Therefore, in the case of off-chip, since each pad and buffer occupy the inside of the DRAM, the total chip area is reduced or hardly reduced as compared to the one-chip configuration.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, additions, and the like within the spirit and scope of the present invention, and such modifications and changes should be regarded as belonging to the following claims. something to do.

Claims (7)

A DRAM test apparatus having a multiplexer which controls and selects external signals and internally generated signals, and selects and outputs a test mode or a processor mode while reducing a time delay of the selected signal; A processor that executes processing of control signals, addresses, and data when a processor mode is selected according to the output of the multiplexer; And And a DRAM configured to store data processed from a processor or data input from the outside according to the output of the multiplexer. The method of claim 1, The multiplexer, As signals from outside and internally made are passed through the multiplexer and buffer inside the DRAM and distributed to the required circuit blocks, the signal lines are arranged across the center of the chip to reduce RC delay as much as possible. Memory and logic integrated chip. The method of claim 1, The multiplexer, A memory and logic integrated chip comprising a pad having an electrostatic discharge circuit necessary for externally applying a control signal, an address signal, a write-time data, etc. to the DRAM to test only the DRAM in the MML. The method of claim 1, The multiplexer, Characterized in that the signal coming from the outside and the signals made by the processor in the internal control mode according to the test mode, so that the external signal or internal signal is supplied to the DRAM according to the test mode or processor mode, each mode, Chip of memory and logic. In an integrated chip with a combination of memory and logic, A method for testing integrated chips in memory and logic, characterized by putting a test mode to test only DRAM. The method of claim 5, The test mode, A first step of enabling a test signal; A second step of applying data to the DRAM through a pin connected to the outside in the case of an external control signal, an address signal, or a write; A third step of sending externally received signals to each input buffer via a multiplexer; And Each signal passing through the buffer is a four-step process of memory and logic, characterized in that the four steps to read or write the DRAM in the same way as operating a normal DRAM. The method of claim 6, The test signal, A test method for an integrated chip of memory and logic, comprising adding a signal for a test to enter a test mode, or using a test mode entry signal as a signal that distinguishes a test mode from a processor mode among existing signals.