KR19990005451A - Highly integrated memory device and its manufacturing method - Google Patents

Abstract

1. Areas in which the claimed invention is concerned

Semiconductor memory element and method of manufacturing the same.

2. Technical Challenges to be Solved by the Invention

In the case of using platinum as the lower electrode of the capacitor and TiN / Ti as the barrier layer, in order to solve the problem that the oxidation reaction of the barrier layer occurs actively even at a low temperature, the electrical connection between the lower electrode of the capacitor and the MOSFET below the capacitor is destroyed.

3. The point of the solution of the invention

Stabilizing the electrical connection between the capacitor lower electrode and the MOSFET by forming a conductor sidewall on the side of the storage node pattern.

4. Important Uses of the Invention

Used in the manufacture of semiconductor memory devices.

Description

Highly integrated memory device and its manufacturing method

The present invention is a highly integrated memory device and relates to a method of manufacturing the same, in particular BST [Ba (Sr, Ti) O 3] of the second to use a dielectric material highly integrated DRAM or ferroelectric memory device (ferroelectric RAM) manufacturing a capacitor lower electrode and the MOSFET To a device structure suitable for securing the reliability of the electrical connection of a source and a method of manufacturing the same.

In a highly integrated DRAM, when a high dielectric material such as BST is used as a dielectric material, use of Pt is considered as a lower electrode, and Pt is one of the most probable electrode materials in a ferroelectric nonvolatile memory device.

1 is a cross-sectional view of a typical highly integrated memory device using Pt as the lower electrode of a capacitor. As shown in the figure, a capacitor storage node of a highly integrated storage element is composed of a polysilicon plug 6, a diffusion prevention film 7, and a Pt lower electrode 8. Since Pt, which is mainly used as a lower electrode, does not act as a barrier for preventing the diffusion of oxygen, oxygen is diffused through the Pt lower electrode 8 in the process of depositing the high dielectric material or the ferroelectric substance 9, Is oxidized.

Meanwhile, TiN / Ti is mainly used for the diffusion preventive film 7, and polysilicon 6, which is a material for plugs and various kinds of barrier materials including Ti and TiN, is very active in oxidation reaction. Therefore, Oxidation may occur even at low temperatures to destroy the electrical connection of the Pt lower electrode 8 and the source junction (S / D) formed under the capacitor. This problem becomes worse as the dielectric constant or the ferroelectric deposition temperature is higher.

In particular, in the case of SBT (SrBi ₂ Ta ₂ O ₉ ), which is one of the most promising materials for ferroelectric memory devices, the temperature required for deposition and crystallization is about 800 ° C., in order to realize a highly integrated ferroelectric memory device of on-bit line structure, it is most important to stabilize the electrical connection between the Pt electrode and the MOSFET.

An object of the present invention is to provide a device structure and a manufacturing method thereof that can increase the reliability of electrical connection between a capacitor electrode and a MOSFET in a highly integrated memory device.

In order to achieve the above object, the ferroelectric memory device of the present invention includes a conductor layer which is connected to a junction layer of a MOSFET which penetrates an insulating layer on a semiconductor substrate and has a lower structure, a diffusion preventing layer formed on the conductor layer, And a conductor spacer formed on the sidewall of the patterned laminated films and electrically connecting the lower electrode and the conductor layer.

According to an aspect of the present invention, there is provided a method of fabricating a ferroelectric memory device, including: forming an insulating layer on a semiconductor substrate, the insulating layer including a contact hole exposing a predetermined portion of the semiconductor substrate; Forming a plug by filling a first conductor in the contact hole; stacking a second conductor layer, a first diffusion preventive film, a capacitor lower electrode layer, a dielectric thin film, and a second diffusion preventive film on the insulating layer including the plug in order step; Patterning the stacked films in a predetermined pattern, and forming a third conductor spacer on the sidewalls of the patterned layer; And forming a third diffusion barrier layer on the front surface.

1 is a cross-sectional view of a highly integrated memory device of a conventional COB structure,

2 is a cross-sectional view showing a memory element structure according to the present invention,

FIGS. 3A to 3C are flow charts showing a method of manufacturing a storage element according to an embodiment of the present invention;

4A to 4C are flowcharts showing a method of manufacturing a memory element according to another embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

1: semiconductor substrate 2: field oxide film

3: Gate 5: Insulating layer

210: Conductor 220: First diffusion preventing layer

230: capacitor lower electrode layer 250: dielectric thin film

240: conductor spacer 260: capacitor upper electrode layer

270: second diffusion preventing layer

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The problem of breaking the electrical connection between the capacitor electrode and the MOSFET due to the oxidation of the barrier layer or polysilicon layer in the highly integrated memory device occurs mainly in the step of exposure to the oxygen atmosphere at high temperature, i.e., the deposition and crystallization process of the dielectric thin film. The present invention fundamentally solves the above problem by electrically connecting the capacitor electrode to the MOSFET after the deposition of the high dielectric constant or ferroelectric thin film and the crystallization process.

Fig. 2 is a cross-sectional view of a memory element according to the present invention.

The highly integrated memory device of the present invention has a MOSFET formed with a gate 203 and a source and a drain (S / D) on a semiconductor substrate 201, and a capacitor is formed on the semiconductor substrate 201 with an insulating layer 205 interposed therebetween The capacitor includes a conductor 210 which penetrates the insulating layer 205 and is connected to a source and a drain of the MOSFET S / D, a first diffusion prevention film 220 sequentially formed on the conductor 210, a lower electrode layer 230, A second conductor spacer 240 electrically connecting the conductor 210 and the lower electrode layer 230 and a dielectric thin film 250 and an upper electrode layer 260 sequentially formed on the lower electrode layer 230 . A second diffusion barrier layer 270 is formed on the second conductor spacers 240 and the upper electrode layer 260.

In FIG. 2, reference numeral 202 denotes a field oxide film, and 204 denotes a bit line.

3A to 3C show a method of fabricating a highly integrated memory device according to an embodiment of the present invention in the order of steps.

3A, a field oxide film 302 is formed on a semiconductor substrate 301 to separate an active region and a field region. Then, a gate 303, a source and a drain are formed on a semiconductor substrate 301 on an active region. Drain (S / D) is formed, and then an insulating layer 305 is formed on the entire surface of the substrate to planarize. Subsequently, the insulating layer 305 is selectively etched to form a contact hole exposing the source or drain (S / D) of the MOSFET. Then, a first conductor such as polysilicon is buried in the contact hole, Thereby forming a sieve plug 306. A second conductive layer 310 such as polysilicon and a first diffusion barrier layer 311 such as TiO ₂ and a capacitor Pt lower electrode layer 312 are formed on the insulating layer 305 and the first conductive plug 306, And a high dielectric or ferroelectric thin film 313 such as BST, PZT, Y1 or the like is deposited thereon and crystallized, and then TiO ₂ and a second diffusion prevention film 314 are formed thereon. Then, the stacked films are etched by selective etching using a storage node mask.

Here, the first diffusion barrier layer 311 selects a material capable of acting as an oxygen diffusion barrier or, when the surface of the second conductive layer is oxidized, selects the second conductor layer material so that the oxide layer acts as an oxygen barrier. The surface oxide layer or the first diffusion barrier layer of the second conductor that may occur during the process does not need to be a conductor, and the diffusion of oxygen in the process of vapor deposition of the dielectric thin film and the heat treatment process, 1 conductor plug 306 is not lost.

Next, in FIG. 3B, a third conductor layer is formed on the entire surface, and the third conductor spacer 315 is formed on the pattern side by etching without a mask. At this time, the degree of etching is over-etched so that the uppermost portion of the third conductor spacer is adjusted to be close to the top of the Pt lower electrode 312. Even if the first diffusion barrier layer 311 is made of an insulator or the upper surface of the second conductor layer 310 is oxidized by the diffusion of oxygen due to the deposition and crystallization process of the dielectric thin film to become a nonconductor, (312) and the MOSFET source are electrically and stably connected through the third conductor spacer (315), the lower portion of the second conductor layer, and the first conductor plug (306).

Next, referring to FIG. 3C, a third diffusion barrier layer 316 is formed to serve as a diffusion barrier for oxygen so that the conductors are no longer oxidized and electrical connection is cut off. Since the lower portion of the third conductor and the second conductor and the first conductor are protected by the thick third diffusion barrier layer 316, the electrode of the capacitor and the MOSFET are electrically stable And it will play a role of connecting to it.

Thereafter, the upper electrode forming process and the subsequent process of the capacitor are performed.

4A to 4C are process cross-sectional views showing another embodiment of the present invention, in which a method of forming the third conductor spacer 315 and the third diffusion preventing layer 316 in a state of forming the Pt upper electrode 317 Respectively. In this alternative embodiment, it can be seen that the patterning of the third diffusion barrier layer 316 is selectively etched by a mask other than the front etch, other than the method of forming the Pt upper electrode 317 first, and other specific explanations 2A and 2C, and will not be described here.

In the conventional memory element shown in Fig. 1, the diffusion preventing film must maintain the bonding property between the lower electrode and the polysilicon plug, prevent diffusion of oxygen to the polysilicon plug at a high temperature, and oxidize itself to make the electrical contact poor The selection range of the material was very small, and it was impossible to obtain satisfactory characteristics. However, as described above, since the first diffusion prevention film may be non-conductive in the present invention, the choice of the material is very wide. This means that the physical properties of the lower electrode, for example, the Pt electrode, deposited on the first diffusion prevention film can be optimized. In fact, when Pt is deposited on the Ti barrier layer as in the conventional method, the crystallinity is significantly lower than that of Pt deposited on SiO ₂ under the same conditions. The physical properties of the dielectric thin film, particularly the high dielectric / ferroelectric thin film, are largely influenced by the lower electrode material and the film quality thereof. Therefore, if the selection range of the diffusion preventing material is widened, the characteristics of the capacitor itself can be remarkably improved.

On the other hand, the thickness of the third conductor can be precisely controlled, and the etching process of the third conductor proceeds without a mask, so that the gap between the two storage nodes can be narrowed to a minimum level. Therefore, the integration degree of the memory element does not decrease due to the application of the present invention. The first diffusion barrier layer and the second diffusion barrier layer may be omitted depending on the case. The first diffusion barrier layer may be a conductor or an insulator. The first conductor, the second conductor, the third conductor, The same material. An intermediate layer may be inserted between the respective layers, for example, for the purpose of improving adhesion, etc. between the first conductor and the second conductor, between the first diffusion preventing layer and the lower electrode, or before the deposition of the third conductor .

In one embodiment of the present invention and other embodiments, the conductors are formed of a material selected from the group consisting of polysilicon, Al, Ti, Cu, W, Ta, Pt, Au, Pd, Rh, Ru, Ir, Re, La, Sr, An alloy including these, a conductive oxide, a conductive nitride film, a silicide, or the like.

The first diffusion barrier layer may be formed of an oxide or a nitride containing various elements including Si, Ti, Ta, Sr, Bi, and Zr to prevent diffusion of oxygen. The CVD or PVD method or the spin- It is preferable to use a spin on glass.

The electrode of the capacitor may be formed of a metal or an alloy including Pt, Au, Ag, Pd, Rh, Ru, Ir, Re or the like or a conductive oxide including elements such as Ru, Ir, Re, La, Sc, Co, , Conductive silicide, or the like.

The dielectric film is a ferroelectric material having a perovskite (perovskite) structure including Ba (Sr, Ti) of material not less than a dielectric constant of 50, including the O _3, or with or without Pb (Zr, Ti) not doped O ₃ Or SrBi ₂ Ta ₂ O ₉ , BaBi ₂ Nb ₂ O ₉ , PbBi ₂ Ta ₂ O ₉ , BaBi ₂ Ta ₂ O ₉ , SrBi ₂ TaNbO ₉ , SrBi ₂ Nb ₂ O ₉ , SrBi ₄ Ti ₄ O ₁₅ , PbBi ₂ Nb ₂ O _9, or a solid solution of two or more thereof.

Further, the ferroelectric thin film is composed of Al_w1 ^{+ a1}A2_w2 ^{+ a2}....... Aj_wj ^{+ aj}S1_x1 ^{+ s1}S2_x2 ^{+ s2}...... Sk_xk ^{+ sk}B1_y1 ^{+ b1}B2_y2 ^{+ b2}...... Bl_yl ^{+ bl}Q_z ^-2Layered superlattice material having a structure of a superlattice structure. Where Aj is the A site element of the perovskite structure, Sk is the superlattice generator element, Bl is the B site element of the perovskite structure, and Q is the anion. The superscripts represent valences and the subscripts represent the average number of atoms in a unit cell.

The third diffusion barrier layer may be formed of an oxide or a nitride containing various elements including Si, Ti, Ta, Sr, Bi, and Zr to prevent diffusion of oxygen. The third diffusion barrier layer may be formed by CVD or PVD, It is preferable to use a spin on glass.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.

According to the present invention, the reliability of the electrical connection between the capacitor electrode and the MOSFET in the highly integrated memory element can be improved, and the characteristics of the capacitor itself can be improved.

Claims (18)

A conductor layer pattern contacted with a junction layer of a MOSFET, which penetrates the insulating layer on the semiconductor substrate and has a lower structure; A diffusion prevention layer pattern formed on the conductor layer; A capacitor lower electrode layer pattern formed on the diffusion preventing layer; And a conductor spacer which is formed to extend on each side wall of the conductor layer pattern, the diffusion preventing layer pattern, and the capacitor lower electrode layer pattern, thereby electrically connecting the conductor layer pattern and the lower electrode layer pattern. The storage element according to claim 1, further comprising a dielectric thin film sequentially stacked on the lower electrode layer and a capacitor upper electrode. 3. A storage element according to claim 1 or 2, further comprising a second diffusion barrier layer formed on the conductor spacer. 3. The device according to claim 1 or 2, wherein the conductor layer comprises a first conductor plug contacted with the junction layer of the MOSFET, and a second conductor plug laminated on the insulating layer comprising the first conductor plug, And a second conductive layer patterned to have the same size. 3. The storage element according to claim 1 or 2, wherein the first and second diffusion prevention films are oxide films or nitride films of any one of Si, Ti, Ta, Sr, Bi and Zr. 5. The memory element of claim 4, wherein the first conductor plug and the second conductor layer are the same material. 5. The device of claim 4, wherein the first conductor plug and the second conductor layer are different materials, and the third and fourth conductors are disposed between the first and second conductors to increase contact between the first and second conductors. Further comprising a conductive layer. Forming an insulating layer on the semiconductor substrate, the insulating layer including a contact hole exposing a predetermined portion of the semiconductor substrate; Burying a first conductor in the contact hole to form a plug; Depositing a second conductive layer, a first diffusion barrier layer, a capacitor lower electrode layer, a dielectric thin film, and a second diffusion barrier layer in this order over the insulating layer including the plug; Patterning the stacked films in a predetermined pattern, and forming a third conductor spacer on the sidewalls of the patterned layer; And forming a third diffusion barrier layer on the front surface. 9. The method according to claim 8, further comprising forming a capacitor upper electrode layer between the dielectric thin film and the second diffusion barrier layer. The method of claim 8 or 9, wherein the first, second, and second diffusion barrier layers are oxide or nitride layers of any one of Si, Ti, Ta, Sr, Bi, and Zr. 11. The method of claim 10, wherein the first, second, and third diffusion barrier layers are formed by CVD, PVD, or a spin-on-glass method. 10. The method of claim 8 or 9, wherein the first conductor plug and the second conductor layer are the same material. 10. The method of claim 8 or 9, wherein the first conductor plug and the second conductor layer are different materials, and the first and second conductors And a fourth conductive layer between the first conductive layer and the second conductive layer. 10. The method of claim 8 or 9, wherein the third conductor spacer is formed by forming the third conductor layer on the entire surface of the substrate and then front-etching the substrate without a mask. 11. The method of claim 8 or 9, wherein the first, second, and third conductors are selected from the group consisting of polysilicon, Al, Ti, Cu, W, Ta, Pt, Au, Pd, Rh, Ru, La, Sr, Sc, Co or the like, an alloy containing them, a conductive oxide, a conductive nitride film, or a silicide. The capacitor lower electrode layer according to claim 8 or 9, wherein the capacitor lower electrode layer comprises a metal or an alloy including Pt, Au, Ag, Pd, Rh, Ru, A conductive nitride, and a conductive silicide including an element such as a silicon oxide or a silicon nitride. 10. The method according to claim 8 or 9, wherein the dielectric thin film is formed of a high dielectric constant or ferroelectric thin film. 9. The method of claim 8, further comprising: after selectively etching the third diffusion barrier layer and the second diffusion barrier layer to expose the surface of the dielectric thin film, and then forming a capacitor upper electrode layer thereon Further comprising the step of: