KR19990004948A - Method of forming contact pattern in semiconductor device without photolithography process - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Regarding the field of semiconductor manufacturing.

2. The technical problem to be solved by the invention

An object of the present invention is to provide a method of manufacturing a semiconductor device for forming a contact pattern of a charge storage electrode, a bit line, etc. while excluding a photo etching process.

3. Summary of Solution to Invention

The present invention uses the anisotropic and isotropic epitaxial growth method using silicon, polysilicon, tungsten, silicide, transition metal, etc. to form a conductive film pattern without a photolithography process.

4. Important uses of the invention

Conductive film pattern, especially used to form charge storage electrodes.

Description

Method of forming contact pattern in semiconductor device without photolithography process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor drafting, and more particularly, to a method of patterning a conductive film pattern such as a charge storage electrode, a bit line, or the like in a semiconductor device manufacturing process without using a mask.

As the integration of semiconductor devices increases, devices having the same function in a small cell area need to be implemented, which in turn depends on the resolution capability of lithography processes. The lithography process is used to form patterns of charge storage, electrodes, bit line electrodes, etc. In the order of this, first, a photoresist is applied on the lower layer to be patterned, and then a photoresist is applied using a photo mask. Selectively exposed. Subsequently, the substrate is immersed in the developing solution to form a photoresist pattern as an etching mask.

However, pattern formation using such lithography process has faced limitations in terms of resolution, superposition accuracy, depth of focus, etc. when manufacturing a ULSI (Ultra Large Scale Integration) device.

In addition, the problems caused during the post-treatment process, such as the removal of the resist may adversely affect the characteristics of the device, there is a problem that leads to a cost increase of the product due to the complex process step.

Disclosure of Invention The present invention devised to solve the above problems is to provide a semiconductor device manufacturing method for forming a conductive film pattern of a charge storage electrode, a bit line electrode and the like without a photolithography process.

1A to 1D are diagrams illustrating a process of forming a contact pattern of a semiconductor device according to an embodiment of the present invention.

2A is a conventional general DRAM cell layout diagram.

2B is a DRAM cell layout diagram applied in one embodiment of the present invention.

3 is a cross-sectional view taken along a line A-A 'of FIG. 2B.

* Explanation of symbols for the main parts of the drawings

10: silicon substrate

11: interlayer insulation film

12: selective epitaxial layer

In order to achieve the above object, the semiconductor device manufacturing method of the present invention comprises the steps of forming a contact hole by selectively etching the interlayer insulating film of the semiconductor substrate having a predetermined lower layer; Filling a conductive film in the contact hole; And isotropically growing the conductive film to form a conductive film pattern having a predetermined line width.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, FIGS. 1A to 1D are diagrams illustrating a conductive film pattern forming process according to an embodiment of the present invention. First, as shown in FIG. 1A, a predetermined interlayer insulating film (see FIG. 1A) is formed on a semiconductor substrate 10 that has completed a predetermined lower layer process. 11) and the interlayer insulating film 11 is selectively etched to form contact holes.

Next, as shown in FIG. 1B, the selective epitaxial layer 12 is grown to the extent that the contact holes are buried. In this case, the selective epitaxial layer 12 may be used as long as it is a material capable of selective growth, such as silicon, polysilicon, tungsten, or silicide.

Subsequently, the selective epitaxial layer 12 is isotropically grown to secure the line width of the desired pattern as shown in FIG. 1C.

Subsequently, anisotropic growth can be used again to form the pattern if necessary, as shown in FIG. 1D. This process is intended to increase the surface area in the charge storage electrode pattern.

According to another embodiment of the present invention, after forming the contact hole, the conductive film is deposited and etched back to bury the conductive film in the contact hole, and then the isotropic and anisotropic growth process shown in FIGS. 1C and 1D is performed.

As shown in the above embodiment, the present invention may form an island pattern of a charge storage electrode, a bit line bullet, or the like while excluding a photo etching process. In addition, since the overlap with the contact hole is self-aligned (self-align), it is possible to solve problems such as misalignment.

In addition, the present invention is particularly useful for forming charge storage electrodes of DRAMs.

The charge storage electrode is regularly present as an isolation pattern only in the cell region, and according to the embodiments of the present invention and the DRAM cell layout of the conventional folded bit-ine structure, respectively, in FIGS. 2A and 2B. The layout of the DRAM cell applied is shown.

Reference numeral 21 denotes a word line (gate electrode) 22, an active region, 23, a charge storage electrode, 24 a bit line contact, and 25 a charge storage electrode contact.

3 is a cross-sectional view taken along the line A-A 'in FIG. 2, and it can be seen that the structure is the same as that of a general DRAM.

Reference numeral 31 denotes an active region, 32 a word line (gate electrode), 33 and 37 an interlayer insulating film, 34 a charge storage electrode, 35 a dielectric film, 36 a plate electrode, and 38 a bit line electrode.

As described above, the present invention can form a pattern of a semiconductor device excluding the photo etching process, and when applied to a highly integrated semiconductor device manufacturing process, it can overcome the limitations of the conventional photo etching process, in particular, misalignment, and simplify the process. Through this, the manufacturing cost of the semiconductor device can be expected to decrease.

Claims (5)

Forming a contact hole by selectively etching the interlayer insulating film of the semiconductor substrate on which the predetermined lower layer is formed; Filling a conductive film in the contact hole; And Isotropically growing the conductive film to form a conductive film pattern having a predetermined line width. The method of claim 1, Embedding a conductive film in the contact hole; And embedding the conductive film by growth of a selective epitaxial layer. The method of claim 1, Embedding a conductive film in the contact hole; Depositing the conductive film on the entire structure; And etching back the conductive film. The method of claim 2 or 3, After forming the conductive film pattern And anisotropically growing the conductive film pattern. The method of claim 2 or 3, The conductive film pattern is A semiconductor device manufacturing method comprising any one of silicon, polysilicon, tungsten and silicide.