KR19990004588A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR19990004588A KR19990004588A KR1019970028715A KR19970028715A KR19990004588A KR 19990004588 A KR19990004588 A KR 19990004588A KR 1019970028715 A KR1019970028715 A KR 1019970028715A KR 19970028715 A KR19970028715 A KR 19970028715A KR 19990004588 A KR19990004588 A KR 19990004588A
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- tinx
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- metal wiring
- heat treatment
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000002184 metal Substances 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 229910010421 TiNx Inorganic materials 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 229910008484 TiSi Inorganic materials 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 4
- 238000005546 reactive sputtering Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 5
- 238000005755 formation reaction Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 41
- 239000000758 substrate Substances 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 확산 방지 금속층 형성을 위해 TiNx/TiNy 다중층으로 형성하여 후속 열처리 공정에서 Ti 가 많은 TiNx 층만이 TiSi2형성 반응에 기여하여 매우 얇은 TiSi2를 형성할 수 있어 양호한 콘택 특성을 얻을 수 있고, 또한 TiNy 층이 고온 열처리 후에도 매우 안정하게 유지될 수 있어 종래의 Ti/TiN 공정 내지는 TiNx 공정보다 개선된 결과를 얻어 반도체 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, to form a diffusion barrier metal layer formed of TiNx / TiNy multilayer, in the subsequent heat treatment process, only TiNx layer having a large amount of Ti contributes to the TiSi 2 formation reaction so that very thin TiSi 2 It is possible to form a good contact characteristics, and the TiNy layer can be maintained very stable even after a high temperature heat treatment to obtain an improved result than the conventional Ti / TiN process or TiNx process yield and reliability It is a technology that can improve.
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히 확산 방지 금속층을 반응성 스퍼터링 방법으로 형성한 후, 고온 열처리하여 실리콘 기판과의 사이에 얇은 금속층을 형성함에 의해 소자의 전기적 특성을 양호하게 하고, 확산 방지능력을 확보할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, by forming a diffusion preventing metal layer by a reactive sputtering method, and then performing a high temperature heat treatment to form a thin metal layer between the silicon substrate to improve electrical characteristics of the device. The present invention relates to a metal wiring forming method of a semiconductor device capable of ensuring diffusion preventing capability.
종래의 일반적인 금속 배선 형성 공정은 아래의 공정단계로 이루어진다.The conventional general metal wiring forming process consists of the following process steps.
즉, 하부 절연막 상부에 하부 금속층을 도포한 후 패턴 공정으로 하부 금속 배선을 형성한다. 그 후 얇은 절연막을 증착시킨 다음 상기 절연막을 평탄화한다. 그 후 금속 배선 들간의 연결을 위해 콘택 마스크를 이용한 식각공정으로 콘택홀을 형성하고, Al 을 금속 배선물질로 하여 화학 기상 증착(Chemical Vapor Deposition; 이하 CVD 라 칭함)방법으로 증착한다. 이 후 에치백(etchback) 공정으로 상기 증착된 금속배선 물질을 식각하여 상기 콘택홀내에 금속 플러그를 형성한다.That is, after applying the lower metal layer on the lower insulating film, the lower metal wiring is formed by a pattern process. After that, a thin insulating film is deposited and then the insulating film is planarized. Thereafter, a contact hole is formed by an etching process using a contact mask to connect the metal lines, and Al is deposited using a chemical vapor deposition (CVD) method using a metal wiring material. Thereafter, the deposited metallization material is etched by an etchback process to form a metal plug in the contact hole.
다음으로 전체구조 상부에 식각 차단층을 형성한 후 절연물질로서 SiO2를 CVD 방법으로 증착한다.Next, an etch stop layer is formed on the entire structure, and SiO 2 is deposited as an insulating material by a CVD method.
그 후 상기 증착된 SiO2막의 상부에 상부 금속배선을 다시 형성하기 위해 금속 배선 물질인을 증착한 후 평탄화시키고, 상기 평탄화된 배선물질 상부에 절연물질로 다시 절연층을 형성한다.Thereafter, a metal wiring material phosphor is deposited and planarized to re-form an upper metal wiring on the deposited SiO 2 film, and then an insulating layer is formed again with an insulating material on the planarized wiring material.
이상 상기와 같은 종래의 기술에 따른 금속 배선 형성 방법에 있어서, 확산방지 금속층을 적층할 시 Si-기판/Ti/TiN 이나 Si-기판/TiN 혹은 Si-기판/TiNx 등의 확산방지 금속층을 적층하는 기술을 널리 사용하고 있다.In the metal wiring forming method according to the related art as described above, when the diffusion barrier metal layer is laminated, a diffusion barrier metal layer such as Si-substrate / Ti / TiN or Si-substrate / TiN or Si-substrate / TiNx is laminated. Technology is widely used.
그러나 상기의 종래의 방법들은 Ti 와 Si-기판 과의 반응에 의한 접합손실, TiN 층만의 증착에 의한 높은 콘택저항 그리고 TiNx 단일층 증착에 의한 TiSi2형성두께 조절의 난이성등이 고집적 소자에의 적용을 어렵게 하는 문제점이 있다.However, the above conventional methods are applied to highly integrated devices such as bonding loss due to reaction between Ti and Si-substrate, high contact resistance by deposition of TiN layer only, and difficulty in controlling TiSi 2 formation thickness by TiNx single layer deposition. There is a problem that makes it difficult.
따라서 본 발명은 상기의 문제점을 해결하기 위한 것으로, 본 발명의 목적은 확산 방지 금속층을 반응성 스퍼터링 방법으로 형성한 후, 고온 열처리하여 실리콘 기판과의 사이에 얇은 금속층을 형성함에 의해 소자의 전기적 특성을 양호하게 하고, 확산 방지능력을 확보할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to form electrical diffusion characteristics of a device by forming a thin metal layer between a silicon substrate and a high temperature heat treatment after forming a diffusion preventing metal layer by a reactive sputtering method. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device, which can be made satisfactory and can secure a diffusion preventing ability.
도 1 내지 도 4 는 본 발명의 방법에 따른 금속 배선 형성 공정단계를 도시한 단면도.1 to 4 are cross-sectional views showing the metallization process steps according to the method of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
1 : 하부층(실리콘 기판) 2 : 절연막1: lower layer (silicon substrate) 2: insulating film
3,4,5,6 : 금속박막 7 : Al(혹은 W)3,4,5,6: Metal thin film 7: Al (or W)
8 : 반사 방지층8: antireflection layer
상기 목적을 달성하기 위한 본 발명의 방법에 의하면,According to the method of the present invention for achieving the above object,
하부 절연막 상부에 하부 금속층을 형성한 후 패턴 공정으로 하부 금속배선을 형성하는 단계와,Forming a lower metal layer on the lower insulating layer and then forming a lower metal wiring by a pattern process;
상기 하부 금속층 상부에 소정 두께의 절연막을 증착시킨 후, 상기 절연막을 평탄화시키는 단계와,Depositing an insulating film having a predetermined thickness on the lower metal layer, and then planarizing the insulating film;
콘택 마스크를 이용한 식각공정으로 상기 절연막에 콘택홀을 형성하는 단계와,Forming a contact hole in the insulating layer by an etching process using a contact mask;
전체구조 상부에 TiNx 층을 형성하는 단계와,Forming a TiNx layer on the entire structure,
동일 장치내에서 상기 TiNx 층 상부에 TiNy 층을 형성하는 단계와,Forming a TiNy layer on top of the TiNx layer in the same device,
열처리 공정을 통하여 TiNx의 일부가 TiSi2 로 변환되게 하는 단계와,Converting a part of TiNx into TiSi2 through a heat treatment process;
전체구조 상부에 금속 배선층과 반사 방지층을 차례로 형성하는 단계로 구성되는 것을 특징으로 한다.Forming a metal wiring layer and an anti-reflection layer in order on the entire structure, characterized in that consisting of.
이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1 내지 도 4 는 본 발명의 방법에 따른 금속 배선 형성 공정단계를 도시한 단면도이다.1 to 4 are cross-sectional views illustrating a process for forming metal wirings according to the method of the present invention.
먼저, 하부층(1) 또는 실리콘 기판(1)의 상부에 절연막(2)을 형성한 후 금속 배선들 간의 연결을 위해 상기 절연막(2)을 콘택 마스크를 이용한 식각공정으로 비아 콘택홀(7)을 형성한다.First, the insulating layer 2 is formed on the lower layer 1 or the silicon substrate 1, and then the via contact hole 7 is formed by etching the insulating layer 2 using a contact mask to connect the metal wires. Form.
이때 상기 콘택홀(7)은 비트라인 형성을 위한 콘택홀(7)일 수도 있다.In this case, the contact hole 7 may be a contact hole 7 for forming a bit line.
그 후 전처리 공정을 통해 콘택홀(7)의 하부에 형성된 자연 산화막을 제거한다. 그리고 고진공으로 유지된 반응성 스퍼터링 장치를 이용하여 Ti 가 많이 함유된 (Ti-rich) TiNx 층(3)을 형성한다.Thereafter, the native oxide film formed on the lower portion of the contact hole 7 is removed through a pretreatment process. In addition, a Ti-rich (Ti-rich) TiNx layer 3 is formed using a reactive sputtering apparatus maintained at high vacuum.
이때 상기 TiNx 층(3)의 두께는 증착장치의 성능과 소자의 콘택 단차비에 따라 다르나 일반적으로 예정된 전체 확산 방지 금속층 두께의 10~60% 를 증착하여 추후 형성되어질 두께를 조절한다. (도 1 참조).In this case, the thickness of the TiNx layer 3 depends on the performance of the deposition apparatus and the contact step ratio of the device, but in general, 10 to 60% of the predetermined thickness of the total diffusion barrier metal layer is deposited to control the thickness to be formed later. (See Figure 1).
다음, TiNx 층(3) 형성후 전체 구조 상부에 TiNy 층(4)을 형성한다. 이때 증착조건은 상기 TiNx 층(3) 형성시와 동일한 스퍼터링 챔버에서 진공파괴 없이 증착하는 조건으로 한다.Next, after the TiNx layer 3 is formed, a TiNy layer 4 is formed on the entire structure. At this time, the deposition condition is a condition for depositing without vacuum destruction in the same sputtering chamber as when forming the TiNx layer (3).
상기 TiNy 층(4)은 후속 열처리 공정에서도 TiSi2형성에 기여하지 않고 단지 확산 방지 금속 역할만을 한다. (도 2 참조)The TiNy layer 4 does not contribute to TiSi 2 formation even in the subsequent heat treatment process, but merely serves as a diffusion preventing metal. (See Figure 2)
이후 RTP 나 노(Furnace) 등을 이용한 열처리 공정을 실시한다. 이때 실리콘 기판(1)과 반응하여 Si-기판(1)/TiSi2(6)/TiNz(5) 를 형성한다.Thereafter, a heat treatment process using RTP nano-furnace is performed. At this time, it reacts with the silicon substrate 1 to form an Si-substrate 1 / TiSi 2 (6) / TiNz (5).
상기 TiSi2(5) 는 열처리 온도와 시간에 따라 C49 나 C54 상의 TiSi2를 형성할 수도 있고, C49 나 C54 상이 혼재된 상태일 수도 있다.(도 3 참조)The TiSi 2 (5) may form TiSi 2 on the C49 or C54 phase depending on the heat treatment temperature and time, or may be in a mixed state of the C49 or C54 phase (see FIG. 3).
열처리 후, 화학 기상 증착(Chemical Vapor Deposition ; CVD) 혹은 물리 기상 증착(Physical Vapor Deposition ; PVD )법을 이용하여 Al 합금 혹은 W 등의 금속 배선층을(7)을 형성한다. 그 후 금속 배선 마스크 작업을 위해 상기 금속 배선층(7)의 상부에 반사 방지층(8)을 형성한다. (도 4 참조)After the heat treatment, a metal wiring layer 7 such as Al alloy or W is formed by using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Thereafter, an antireflection layer 8 is formed on the metal wiring layer 7 for metal wiring mask work. (See Figure 4)
한편, 상기에서 TiNx 증착 후 TiNy 증착시 증착된 TiNy 가 N-rich 혹은 Ti : N 의 비율이 1 : 1 인 상으로 할 수 있고, 또한 상기 고온 열처리 공정은 650~850℃ 사이의 온도와 N2혹은 N2+ Ar 분위기 하에서 진행한다.Meanwhile, TiNy deposited during TiNy deposition after TiNx deposition may be in an N-rich or Ti: N ratio of 1: 1, and the high temperature heat treatment process is performed at a temperature between 650 ° C. and 850 ° C. and N 2. Or in an N 2 + Ar atmosphere.
따라서 상기한 바와 같이, 확산 방지층 형성에 있어 종래의 Ti/TiN 층 대신 TiNx/TiNy 층을 형성하여 원하는 두께의 TiSi2형성을 가능하게 한다.Therefore, as described above, in forming the diffusion barrier layer, instead of the conventional Ti / TiN layer, a TiNx / TiNy layer is formed to enable formation of TiSi 2 having a desired thickness.
한편, 본 발명은 얇은 접합을 갖는 소자의 금속 콘택에서 뿐만 아니라, 후속 열공정이 600℃ 이상인 경우에 있어서도 적용함으로써, 후속 열공정에 관계없이 열안정성을 확보할 수 있다. 특히 기가(giga) 디램 소자급에서의 W-비트라인 공정의 확산 방지 금속으로의 사용이 유망시되고, 또한 고유전체 공정에서 필요로 하는 전극 확산 방지막으로의 사용도 가능하다.On the other hand, the present invention can be applied not only in the metal contact of a device having a thin junction but also in a case where the subsequent thermal process is 600 ° C. or higher, thereby ensuring thermal stability regardless of the subsequent thermal process. In particular, the use of the W-bit line process as a diffusion preventing metal in a giga DRAM device class is promising, and also as an electrode diffusion preventing film required in a high dielectric process.
이상 상술한 바와 같은 본 발명의 방법에 의하면, 확산 방지 금속층 형성을 위해 TiNx/TiNy 다중층으로 형성하기 때문에 후속 열처리 공정에서 Ti 가 많은 TiNx 층만이 TiSi2형성 반응에 기여하여 매우 얇은 TiSi2를 형성할 수 있어 양호한 콘택 특성을 얻을 수 있다.According to the method of the present invention as described above, since the TiNx / TiNy multilayer is formed in order to form the diffusion preventing metal layer, only the TiNx layer having a high Ti in the subsequent heat treatment process contributes to the TiSi 2 formation reaction to form a very thin TiSi 2 . It is possible to obtain good contact characteristics.
또한 TiNy 층이 고온 열처리 후에도 매우 안정하게 유지될 수 있어 종래의 Ti/TiN 공정 내지는 TiNx 공정보다 개선된 결과를 얻을 수 있다.In addition, the TiNy layer can be maintained very stably even after high temperature heat treatment, and thus the TiNy layer can obtain improved results over the conventional Ti / TiN process or the TiNx process.
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