KR19990004406A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990004406A KR19990004406A KR1019970028497A KR19970028497A KR19990004406A KR 19990004406 A KR19990004406 A KR 19990004406A KR 1019970028497 A KR1019970028497 A KR 1019970028497A KR 19970028497 A KR19970028497 A KR 19970028497A KR 19990004406 A KR19990004406 A KR 19990004406A
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- insulating film
- semiconductor device
- etch back
- back process
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- 239000004065 semiconductor Substances 0.000 title abstract description 18
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000010408 film Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 230000003064 anti-oxidating effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 239000010949 copper Substances 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 소자의 제조 방법에 관한 것임.The present invention relates to a method for manufacturing a semiconductor device.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
반도체 소자의 금속 배선 형성시 또는 층간 절연막 증착시 크기가 다른 패턴을 동시에 매립하는 경우 패턴된 영역이 넓은 부분에 단차가 발생하여 후속 에치 백 공정시 패턴이 완전히 매립되지 않는 문제점을 해결하기 위함.This is to solve the problem that the pattern is not completely embedded in the subsequent etch back process when the patterned area is widened at the same time when the metal wires are formed in the semiconductor device or when the interlayer insulating film is deposited.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
금속 박막 또는 층간 절연막 증착 후 스텝 커버리지가 우수한 절연막을 형성한 다음 에치 백 공정을 실시하므로써 패턴된 영역이 넓은 부분의 단차로 인한 비평탄화 문제를 해결할 수 있음.After the deposition of the metal thin film or the interlayer insulating film, an insulating film having excellent step coverage is formed, followed by an etch back process, thereby solving the problem of unplanarization due to the step difference in the patterned area.
4.발명의 중요한 용도4. Important uses of the invention
구리박막을 배선 구조로 이용한 반도체 소자 제조 분야.Semiconductor device manufacturing using copper thin film as wiring structure.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 평탄화 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a planarization method for a semiconductor device.
반도체 소자의 금속 배선 형성시 크기가 다른 패턴에 금속 박막을 동시에 매립기 위해서 종래에는 금속 박막을 증착한 후 에치 백 공정을 실시하였다. 이와 같은 경우 패턴이 큰 영역에서는 충분한 양의 구리를 매립하기 어려우며 이에 따라 소자의 전기적 특성이 저하되었다. 또한 금속 배선 간에 절연막을 형성하는 경우에도 절연막만을 증착하고 에치 백 공정을 실시함에 따라 소자의 평탄화 특성이 낮아져 소자의 신뢰성이 저하되는 문제점이 있다.In order to simultaneously embed a metal thin film in a pattern having a different size at the time of forming a metal wiring of a semiconductor device, a metal thin film is deposited, followed by an etch back process. In such a case, it is difficult to bury a sufficient amount of copper in a large pattern area, thereby deteriorating the electrical characteristics of the device. In addition, even when the insulating film is formed between the metal wires, only the insulating film is deposited and the etch back process is performed, thereby lowering the planarization characteristics of the device, thereby reducing the reliability of the device.
따라서, 금속 박막 또는 층간 절연막 증착 후 스텝 커버리지가 우수한 절연막을 형성한 다음 에치 백 공정을 실시하므로써 패턴된 영역이 넓은 부분의 단차로 인한 비평탄화 문제를 해결할 수 있는 반도체 소자의 제조 방법을 제공하는 데 그 목적이 있다.Therefore, by forming an insulating film having excellent step coverage after deposition of a metal thin film or an interlayer insulating film, and then performing an etch back process, a method of manufacturing a semiconductor device capable of solving the problem of non-planarization caused by a step of a wide patterned region is provided. The purpose is.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 평탄화 방법은 하지막이 형성된 기판 상부에 금속 박막 및 내산화 방지막을 순차적으로 형성한 후 선택된 영역을 패터닝하는 단계와, 전체 구조 상부에 제 1 절연막을 형성하는 단계와, 전체 구조 상부에 제 2 절연막을 형성하는 단계와, 상기 제 2 절연막을 형성한 후 플라즈마 에치 백 공정을 실시하는 단계와, 전체 구조 상부에 제 3 절연막을 형성하는 단계로 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of planarizing a semiconductor device, by sequentially forming a metal thin film and an anti-oxidation film on a substrate on which an underlayer is formed, patterning a selected region, and forming a first insulating film on the entire structure. Forming a second insulating film over the entire structure, performing a plasma etch back process after forming the second insulating film, and forming a third insulating film over the whole structure. It is characterized by.
도 1(a) 및 1(b)는 종래의 반도체 소자 제조 방법 중 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of devices sequentially shown in order to explain a metal wiring formation method in a conventional semiconductor device manufacturing method.
도 2(a) 내지 2(c)는 종래의 반도체 소자의 제조 방법 중 소자의 평탄화 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown in order to explain the planarization method of devices in the conventional method for manufacturing semiconductor devices.
도 3(a) 내지 3(c)는 본 발명에 따른 반도체 소자의 제조 방법 중 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.3 (a) to 3 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings in the method of manufacturing a semiconductor device according to the present invention.
도 4(a) 내지 4(d)는 본 발명에 따른 반도체 소자의 제조 방법 중 소자의 평탄화 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.4 (a) to 4 (d) are cross-sectional views of devices sequentially shown in order to explain a method of planarization of devices in the method of manufacturing a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11, 21, 31, 41 : 기판 12 : 절연막11, 21, 31, 41: substrate 12: insulating film
13, 33 : 베리어 메탈 14, 22, 34, 42 : 금속 박막13, 33: barrier metal 14, 22, 34, 42: metal thin film
23, 43 : 내산화 방지막 24, 32, 44 : 제 1 절연막23, 43: oxidation resistant film 24, 32, 44: first insulating film
25, 35, 45 : 제 2 절연막 46 : 제 3 절연막25, 35, 45: Second insulating film 46: Third insulating film
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 및 1(b)는 종래의 반도체 소자 제조 방법 중 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of devices sequentially shown in order to explain a metal wiring forming method in a conventional semiconductor device manufacturing method.
도 1(a)에 도시된 바와 같이, 기판(11) 상부에 절연막(12)을 형성한 후 금속배선을 형성할 부분을 패터닝한다. 이후 전체 구조 상부에 베리어 메탈(13)을 형성한 다음 금속 박막(14)을 증착한다. 금속 박막(14) 증착시 패턴의 크기가 넓은 부분에 심한 단차가 발생하게 된다.As shown in FIG. 1A, after forming the insulating film 12 on the substrate 11, the portion to form the metal wiring is patterned. After that, the barrier metal 13 is formed on the entire structure, and then the metal thin film 14 is deposited. When the metal thin film 14 is deposited, a severe step occurs in a large portion of the pattern size.
도 1(b)는 금속 박막(14) 형성된 전체 구조에 에치 백 공정을 실시한 후의 소자의 단면도이다. 이때 패턴된 영역이 좁은 부분은 금속 박막이 완전히 매립될 수 있지만, 패턴된 영역이 넓은 부분은 에치 백 공정에 의해 금속 박막이 완전이 매립되지 않고 절연막(12) 측벽에만 스페이서 형태로 매립되게 된다. 이와 같은 소자의 비평탄화 특성으로 인해는 소자의 전기적 특성 및 신뢰성이 저하되는 문제점이 있다.FIG.1 (b) is sectional drawing of the element after performing the etch back process to the whole structure in which the metal thin film 14 was formed. In this case, the portion where the patterned region is narrow may be completely filled with the metal thin film, but the portion where the patterned region is wide may be filled with spacers only on the sidewall of the insulating layer 12 without the metal thin film being completely embedded by the etch back process. Due to the non-planarization characteristics of the device there is a problem that the electrical characteristics and reliability of the device is degraded.
도 2(a) 내지 2(c)는 종래의 반도체 소자의 제조 방법 중 소자의 평탄화 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown in order to explain a planarization method of devices in a conventional method of manufacturing a semiconductor device.
도 2(a)에 도시된 바와 같이, 기판(21) 상부에 금속 박막(22) 및 내산화 방지막(23)을 순차적으로 형성한 후 선택된 영역을 패터닝한다. 이후, 전체 구조 상부에 제 1 절연막(24)을 형성한다. 이때 패턴의 크기가 큰 부분에는 심한 단차가 발생하게 된다.As shown in FIG. 2A, the metal thin film 22 and the oxidation resistant film 23 are sequentially formed on the substrate 21, and then the selected region is patterned. Thereafter, the first insulating film 24 is formed on the entire structure. At this time, a large step occurs in a large portion of the pattern size.
도 2(b)는 제 1 절연막(24)을 형성한 후 에치 백 공정을 실시한 후의 소자의 단면도이다. 도면에서 알 수 있는 바와 같이, 에치 백 공정시 패턴의 크기가 넓은 부분의 단차로 인해 제 1 절연 산화막(24)이 완전히 매립되지 않는다.2B is a cross-sectional view of the device after the etch back process is performed after the first insulating film 24 is formed. As can be seen from the figure, the first insulating oxide film 24 is not completely buried due to the step difference of the wide part of the pattern during the etch back process.
도 2(c)에 도시된 바와 같이, 에치 백 공정 후 전체 구조 상부에 제 2 절연막(25)을 증착하였다. 그러나 제 1 절연막(24)만을 형성한 후 바로 에치 백 공정을 실시하여 패턴의 크기가 큰 부분에는 제 1 절연막(24)이 완전히 매립되어 있지 않기 때문에 제 2 절연막(25) 형성 후 소자의 표면이 평탄하지 않은 문제점이 발생한다.As shown in FIG. 2C, after the etch back process, a second insulating layer 25 was deposited on the entire structure. However, since only the first insulating film 24 is formed, the etch back process is performed immediately, so that the surface of the element after the second insulating film 25 is formed because the first insulating film 24 is not completely embedded in the large portion of the pattern. An uneven problem occurs.
도 3(a) 내지 3(c)는 본 발명에 따른 반도체 소자의 제조 방법 중 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도로서, 콘택 홀 내부에 금속 박막을 증착하는 경우 소자의 평탄화 방법을 나타낸다.3 (a) to 3 (c) are cross-sectional views sequentially illustrating the metal wiring forming method in the method of manufacturing a semiconductor device according to the present invention. In the case of depositing a metal thin film inside a contact hole, The planarization method of the is shown.
도 3(a)에 도시된 바와 같이, 하지막이 형성된 반도체 기판(31) 상부에 제 1 절연막(32)을 형성한 후 금속배선을 형성할 부분을 패터닝한다. 이후 전체 구조 상부에 베리어 메탈(33)을 형성한 다음 금속 박막(34)을 증착한다.As shown in FIG. 3 (a), after forming the first insulating layer 32 on the semiconductor substrate 31 on which the underlayer is formed, a portion on which a metal wiring is to be formed is patterned. After that, the barrier metal 33 is formed on the entire structure, and then the metal thin film 34 is deposited.
도 3(b)에 도시된 바와 같이, 금속 박막(34)이 형성된 전체 구조 상부에 제 2 절연막(35)을 형성한다. 이때 제 2 절연막(35)은 스텝 커버리지가 우수한 물질을 사용한다.As shown in FIG. 3B, the second insulating layer 35 is formed on the entire structure where the metal thin film 34 is formed. In this case, the second insulating layer 35 is made of a material having excellent step coverage.
도 3(c)에 도시된 바와 같이, 제 2 절연막(35)이 형성되어 있는 전체 구조에 플라즈마 에치 백 공정을 실시한다. 이때 금속 박막과 제 2 절연막(35)의 식각 속도가 1 : 1이 되도록 제어하므로써 크기가 다른 패턴을 동시에 매립할 수 있고 이에 따라 소자의 평탄화 특성을 개선할 수 있다.As shown in FIG. 3C, a plasma etch back process is performed on the entire structure in which the second insulating film 35 is formed. In this case, by controlling the etching rate of the metal thin film and the second insulating layer 35 to be 1: 1, the patterns having different sizes can be buried at the same time, thereby improving the planarization characteristics of the device.
도 4(a) 내지 4(d)는 본 발명에 따른 반도체 소자의 제조 방법 중 소자의 평탄화 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.4 (a) to 4 (d) are cross-sectional views of devices sequentially shown in order to explain a method of planarization of devices in the method of manufacturing a semiconductor device according to the present invention.
도 4(a)에 도시된 바와 같이, 기판(41) 상부에 금속 박막(42) 및 내산화 방지막(43)을 순차적으로 형성한 후 선택된 영역을 패터닝한다. 이후, 전체 구조 상부에 제 1 절연막(44)을 형성한다. 이때 패턴의 크기가 큰 부분에는 심한 단차가 발생하게 된다.As shown in FIG. 4A, the metal thin film 42 and the oxidation resistant film 43 are sequentially formed on the substrate 41, and then the selected region is patterned. Thereafter, the first insulating film 44 is formed on the entire structure. At this time, a large step occurs in a large portion of the pattern size.
도 4(b)에 도시된 바와 같이, 패턴의 크기가 큰 부분의 단차를 줄이기 위해 전체 구조 상부에 제 2 절연막(45)을 형성한다. 이때 제 2 절연막(45)은 스텝 커버리지가 우수한 물질을 사용한다. 또한 제 2 절연막(45)을 사용하는 대신 패턴의 크기가 큰 영역에 감광막을 얇게 도포하는 방법을 사용할 수도 있다.As shown in FIG. 4B, the second insulating layer 45 is formed on the entire structure to reduce the step difference of the portion having the large size of the pattern. In this case, the second insulating layer 45 uses a material having excellent step coverage. In addition, instead of using the second insulating film 45, a method of thinly applying the photosensitive film to a large area of the pattern may be used.
도 4(c)에 도시된 바와 같이, 제 2 절연막(45)에 의해 단차가 발생한 부분을 매립한 후 플라즈마 에치 백 공정을 실시한다. 이때 제 1 절연막(44)와 제 2 절연막(45)의 식각 속도가 1 : 1이 되도록 제어하는 것이 중요하다.As shown in FIG. 4C, after the stepped portion is buried by the second insulating layer 45, a plasma etch back process is performed. In this case, it is important to control the etching rate of the first insulating film 44 and the second insulating film 45 to be 1: 1.
도 4(c)에 도시된 바와 같이, 에치 백 공정을 실시한 후 전체 구조 상부에 제 3 절연막(46)을 형성한다. 도면으로부터 알 수 있듯이, 제 2 절연막(45)에 의해 넓은 패턴 부분의 단차가 방지되어 소자의 평탄화 특성을 개선시킬 수 있다.As shown in FIG. 4C, after the etch back process, a third insulating layer 46 is formed on the entire structure. As can be seen from the figure, the step of the wide pattern portion is prevented by the second insulating film 45 to improve the planarization characteristics of the device.
상술한 바와 같이 본 발명에 따르면 에치 백 공정을 실시하기 전 절연막을 증착하여 패턴된 영역이 넓은 부분이 에치 백 공정에 의해 제거되는 것을 방지할 수 있어, 소자의 평탄화 특성을 개선시킬 수 있고 이에 따라 소자의 전기적 특성 및 신뢰성이 향상되는 탁월한 효과가 있다.As described above, according to the present invention, an insulating film may be deposited before the etch back process to prevent a large portion of the patterned area from being removed by the etch back process, thereby improving the planarization characteristics of the device. There is an excellent effect of improving the electrical characteristics and reliability of the device.
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