KR19990004249A - Bus switching unit of computer - Google Patents

Abstract

The present invention relates to a bus switching device of one computer that can effectively switch two four-way global buses in extending 4-way to 8-way Intel standard for SMP machine design using Pentium Pro.

According to the present invention, a plurality of CPUs 10, an I / O controller 11, an I / O device 12 connected to the A bus, and a plurality of CPUs 20 and I / O controller 21 connected to the B bus are provided. By connecting the I / O device 22 to the memory control unit 30 so that any one of the A bus and the B bus can be selected and operated, the Intel standard 4-way can be extended to 8-way. will be.

Description

Bus switching unit of computer

TECHNICAL FIELD The present invention relates to a computer, and in particular, to switch between two 4-way global buses in an SMP machine design using the Pentium Pro, to effectively switch two 4-way global buses. Relates to a device.

In general, if eight processors are split into two buses of four each, the two buses must be used as one bus, because each bus cannot be independent of each other.

In other words, when a request is driven on the A bus, the request must be reflected on the B bus to ensure the CPU cache coherence of the A and B buses.

This requires switching between the two buses, and each bus requires the CPU to drive the revolve only if the bus to which it belongs is active.

Therefore, the CPU of the inactive bus detects only the reflected request and updates the status of the local cache.

The present invention has been developed in response to this, and when using two Pentium Pro buses with up to four processors on one bus, two buses can be used as one bus to maintain the cache coherence of each CPU. It is an object of the present invention to provide a bus switching device of a computer for switching a bus for use.

In order to achieve the above object, the present invention provides a plurality of CPUs mounted on an A bus, an I / O control unit connected to the A bus, an I / O device connected to the I / O control unit, and a plurality of B mounted on a B bus. An I / O control unit connected to the CPU and the B bus, an I / O device connected to the I / O control unit, and bus switching logic connected to the A bus and the B bus to switch to select any one of them. And a memory for storing data connected to the memory controller and the memory controller.

1 is a schematic diagram of a bus switching device of the computer of the present invention.

2 illustrates a state flow of bus switching logic in accordance with the present invention.

3 is a timing chart of a BPRI and a request of the present invention.

Explanation of symbols for the main parts of the drawings

10, 20: CPU 11, 21: I / O control unit

30: memory controller 31: bus switching logic

32: memory

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of the present invention, a plurality of CPU 10 mounted on the A bus, I / O control unit 11 connected to the A bus, I / O connected to the I / O control unit 11 A device 12, a plurality of CPUs 20 mounted on a B bus, an I / O control unit 21 connected to the B bus, and an I / O device 22 connected to the I / O control unit 21. ), A memory controller 30 having a bus switching logic 31 connected to the A and B buses and switching to select any one of them, and a memory connected to the memory controller 30 and storing data. It consists of 32.

However, the processor of the CPU 10 (20) contains a BREQ (BUS REQUE ST) which is an arbitration signal, and the I / O control unit 11 (12) and the memory control unit 30 are BPRI (BUS PRIORITY) which is an arbitration signal. ) Is included.

According to the present invention configured as described above, the A bus and the B bus can be equipped with up to four CPUs as Pentium Pro buses, and each CPU has four bus request signals.

When the system is initialized, the four CPUs on the bus set their own request signals, which then participate in bus arbitration.

And the arbitration of the CPUs uses the ROUND-ROBIN ROTATING PRIORITY technique.

There is one signal for each Pentium Pro Bus request in an I / O device or memory. This signal has a higher priority than the bus request signal of the CPU 10 (20). The bus switching logic 31 controls the active and inactive states of the bus by using the BPRI signals in the I / O controller 11 and the memory controller 30.

Since the BPRI takes precedence over the BREQ in the processor of the CPU 10 (20), if the BPRI is driven on the bus, all the CPU 10 (20) cannot make a request.

2 shows a state flow diagram of the bus switching logic, in which A2B shows the state of switching from the A bus to the B bus, where the CPU 10 and the I / O controller 11 of the A bus are bus requests. You can do

That is, the B bus is inactive and only snoops on the reflected requests. On the contrary, when switching from B2A, that is, B bus to A bus, the A bus becomes inactive and only the CPU 20 and the I / O control unit 21 of the B bus can request. To make the bus inactive, the bus switching logic drives the BPRI signal on that bus.

Here, switch 2A and switch 2B are intermediate processes of switching from A2B to B2A and B2A to A2B. The switching of the bus is not performed immediately, but refers to an intermediate state that is switched when it is determined that the switch is in a temporary state and can be completely passed.

Hereinafter, the state transition process in FIG. 2 will be described.

First, a transition from A2B to switch 2B occurs when the internal switch timer expires, or when the I / O control unit 21 of the B bus requests without the I / O control unit 11 of the A bus sending a request. Or when the A bus is idle (when all the CPUs 10 and I / O controller 11 on the A bus are idle).

The transition from the switch 2B to the B2A is made when the CPU 10 or the I / O control unit 11 of the A bus does not make a request when driving the BPRI to the A bus.

On the other hand, the transition from B2A to switch 2A is when the internal switch timer expires, or when the I / O control unit 21 of the B bus is idle and the I / O control unit 11 of the A bus requests, or the B bus. Is made when children are children.

The transition from switch 2A to A2B is made when the CPU 20 or the I / O control unit 21 of the B bus does not make a request when driving the BPRI to the B bus.

That is, the BPRI is driven to the A bus when the states are at switches 2B, B2A and switch 2A.

If the status is on switches 2A, A2B and switch 2B, BPRI is driven on B bus.

3 shows the case of the transition from switch 2B to B2A and the transition from switch 2A to A2B during the state transition process.

When the state changes to switch 2B, the BPRI signal is driven to the A bus, which shows the request coming out when BPRI is driven.

The Pentium Proverse must consider all requests in ①②③ of FIG. 3 as legitimate requests and ensure normal operation, and no requests can be generated thereafter.

As described above, the present invention overcomes the limitations of the Pentium Pro Bus and can be a new 8-way industry standard. In particular, the system can be greatly improved by installing up to eight processors. There is an effect that can be useful when making.

Claims (2)

A plurality of CPUs 10 mounted on the A bus, an I / O control unit 11 connected to the A bus, an I / O device 12 connected to the I / O control unit 11, and a B bus. A plurality of CPUs 20 mounted, an I / O control unit 21 connected to the B bus, an I / O device 22 connected to the I / O control unit 21, and the A and B buses And a memory control section 30 having a bus switching logic 31 connected to and arbitrating to select one of them, and a memory 32 connected to the memory control section 30. Device. The computer bus of claim 1, wherein a BREQ signal is included in the CPU 10 and 20, and a BPRI signal is included in the I / O control unit 11 and 21 and the memory control unit 30, respectively. Switching device.