KR19990004133A - Multi Closed Circuit TV Unit - Google Patents

Abstract

The present invention relates to a multi closed circuit TV device, and more particularly, to a multi closed circuit TV display device by field switching.

In the multi-closed circuit TV apparatus according to the present invention, the video signals of a plurality of channels are sequentially switched by two channels every one frame period, and the inflow and inflow channels are separated from the luminance and color signals. By storing them in video RAM and reading them sequentially and displaying each channel on a multi screen, even when there are many channels, the video can be displayed on the screen naturally and close to real time.

Description

Multi Closed Circuit TV Unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi closed circuit television device, and more particularly to a multi closed circuit television display device by field switching.

1 is a block diagram illustrating a conventional multi-closed circuit TV display device.

Referring to the operation of the apparatus illustrated in FIG. 1, two channels CH1 and CH2 are applied to the MUX unit 100 in units of one frame from among video channel signals captured by a plurality of video cameras, which are not shown. The vertical synchronization signal generated by the generation unit 106 is divided into four divisions in the division unit 108 and output to the mux unit 100.

Therefore, the mux unit 100 selects and outputs an image signal of one channel signal, a clock, horizontal and vertical synchronization signals for each frame section according to the high and low levels of the inflow mux control signal. The field detector 102 outputs the clock and the horizontal and vertical synchronization signals corresponding to the interval of one stable field among the two fields of one channel to the address generator 104 and the memory controller 110.

The address generator 110 generates an address of the video RAM 112 corresponding to the position of the screen on which the field of the incoming channel is displayed, and the memory controller 110 outputs a memory control signal for the video RAM 112. . The video RAM 112 writes an image signal of each channel according to a memory control signal and reads one scan line so that the image of each channel is output to the multi screen. Since the multi-closed circuit TV display apparatus detects and displays a field of one channel in units of time of one frame on a multi screen, when the number of channel screens is large, it takes a long time for screen information to be changed for each channel. If the movement is fast, it is displayed unnaturally and the image is not displayed in real time.

The technical problem to be achieved by the present invention is to switch the captured channel image signals in units of one field section, so that the movement of the image displayed on the multi-screen is more natural and the multi-closed circuit TV by the field switching to display the image close to real time on the screen To provide a device.

1 is a block diagram of a multi-closed loop TV device by conventional frame switching.

2 is a block diagram of a multi-closed circuit TV device by field switching according to the present invention.

3 (a) to 3 (c) are timing diagrams of the mux control signal of the first mux part and the vertical synchronization signal of each channel shown in FIG.

Explanation of symbols for the main parts of the drawings

200 ... microcomputer control unit, 202 ... video switching unit

204 ... Y / C separation part, 206 ... sync signal and color decoding part

208 ... 1st mob part, 210 ... light address generation part

212 ... 2nd Mouthbu, 214 ... 3rd Mouthbu

216 synchronous signal generator, 218 divider

220 ... Read address generator, 222 ... Address

224 memory controller, 226 video RAM.

According to an aspect of the present invention, a multi-closed circuit TV apparatus using field switching according to the present invention includes switching switching means for separating a luminance and a color signal from each channel by sequentially inputting multiple channel video signals and switching to two channels. ; Synchronization signal separation and color decoding means for separating the synchronization signal of each channel and decoding a phase locked loop (PLL) clock and a color signal for the synchronization signal; Write address generation means for generating an address to write the synchronization signal and the PLL clock of each of the separated channels to write the video signals of the respective channels; Synchronization signal generation means for generating a stable synchronization signal and a mux control signal having a predetermined period; A mux unit for muxing the write address of each channel, the PLL clock, horizontal and vertical synchronization signals of each channel, and the color signal of each of the decoded channels according to the mux control signal output from the synchronization signal generating means; A read address generation unit for generating an address of a video signal to be read in by introducing the synchronization signal of the synchronization signal generation means; A video RAM for storing or reading video signals of each channel; A memory controller for accessing the video RAM by introducing the read address and the write address of each channel, and outputting a control signal of the video RAM; And a microcomputer controller for controlling the image switching unit.

In addition, the period of the mux control signal flowing into the mux portion is preferably twice the period of the vertical synchronization signal.

In addition, the write address means preferably includes two write address generators for generating an address of the video RAM to which video signals of the respective channels are to be written.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a multi-closed circuit TV device by field switching according to the present invention.

The apparatus shown in FIG. 2 includes a microcomputer control unit 200, a video switching unit 202, a Y / C separation unit 204, a synchronization signal separation and color decoding unit 206, a first mux unit 208, and a channel address. Generation unit 210, second mux unit 212, third mux unit 214, synchronization signal generator 216, frequency divider 218, lead address generator 220, address mux unit 222 , A memory controller 224, a video RAM unit 226, a video encoder 228, and a mux unit 230.

Referring to the operation according to the configuration of FIG. 2, the microcomputer control unit 200 controls the image switching unit 202 to sequentially rotate the image signals captured by the 16 channel video cameras and selects the two channels by one frame. . The two selected channels CH1 and CH2 are respectively separated into luminance and color signals in the Y / C separation unit 204 and then applied to the synchronization signal separation and color decoding unit 206. The synchronization signal separation and color decoder 206 separates a phase locked loop (PLL) clock locked from the horizontal synchronization signal of each channel signal introduced from the horizontal and vertical synchronization signals, and separates the PLL clocks of CH1 and CH2. The horizontal and vertical synchronous signals are output to the light address generator 210. It also decodes the incoming CH1 and CH2 color signals into R-Y and B-Y signals.

The light address generation unit 210 has a horizontal light corresponding to the horizontal effective signal based on the vertical light address and the horizontal synchronous signal corresponding to the vertical effective screen displayed on the basis of the vertical synchronous signals of the channels CH1 and CH2. CH1 and CH2 write address generation units 2101 and 2102 for generating write addresses.

The second mux unit 212 also uses the output signal of the division unit 218 for dividing the stable vertical synchronizing signal generated by the synchronization signal generation unit 216 as a mux control signal, so that the horizontal and The vertical light address is muxed and output to the address mux unit 222.

Also, the first mux unit 208 muxes the video signal of CH1 and CH2, which is output from the dividing unit 218 and has a square wave signal having a period twice the vertical synchronization signal, according to the mux control signal. The video RAM 226 stores the video signal of the corresponding channel according to the write address of CH1 and CH2 selected by the address mux 222.

On the other hand, the read address generator 220 receives the stable sync signal generated by the sync signal generator 216 to generate a read address and outputs the read address to the address mux unit 222. The memory controller 224 introduces the PLL clocks of the muxes CH1 and CH2 from the third mux unit 214 and the horizontal and vertical synchronization signals, and introduces a synchronization signal output from the synchronization signal generation unit 216 to generate a general video RAM ( RAS (Row Address Strobe), CAS (Column Address Strobe), WEB (Write Enable Bar), DT (Data Transfer), SC (Serial Clock) are generated and output to the video RAM 226. do. Here, the third mux unit 214 inputs the PLL clocks of CH1 and CH2 output from the synchronization signal separation and color decoding unit 206 and the horizontal and vertical synchronization signals to output the vertical synchronization signal output from the division unit 218. A square wave signal having a double cycle is used as a mux control signal. The video signal of each channel stored in the video RAM 226 is read by the read address and the memory control signal, and then encoded by the luminance (Y) and color (C) signals by the video encoder 228, and the mixing unit 230. Are mixed and output as composite video signal.

FIG. 3A illustrates a mux control signal which is divided by the division unit 218 shown in FIG. 2 and has a period twice as long as the vertical synchronization signal. FIG. 3B illustrates a vertical control signal included in the video signal of CH1. 3, (c) shows the vertical synchronization signal of CH2.

Here, the first mux unit 208 muxes the signals CH1 and CH2 according to the mux control signal of FIG. 3 (a), and each section of the high or low level of the mux control signal is a section of one field and each section. Correspondingly, CH1 of FIG. 3 (b) and CH2 of FIG. 3 (c) are sequentially selected in units of one field section, and the CH3, CH4 ... CHn signals of other channels not shown in FIG. Are selected sequentially. The video signal of the channel selected by one field section is stored in the video RAM 226 in units of fields corresponding to the position of the effective screen, and then sequentially read and displayed on a multi screen after signal processing.

As described above, the multi-closed circuit TV device by field switching according to the present invention muxes and stores video signals of each channel photographed by a CCTV camera in units of field sections and sequentially reads the video signals of each channel on a multi screen. As a result, even when there are many channels, the image is natural and the image close to real time can be displayed on the screen.

Claims (3)

Switching separation means for inputting a plurality of channel video signals and sequentially switching two channels per frame period to separate luminance and color signals for each channel introduced and introduced; Synchronization signal separation and color decoding means for separating the synchronization signal of each channel and decoding a phase locked loop (PLL) clock and a color signal for the synchronization signal; A write address generation unit configured to generate an address for writing the synchronization signal and the PLL clock of each of the separated channels to write an image signal of each channel; Synchronization signal generation means for generating a stable synchronization signal and a mux control signal having a predetermined period; A mux unit for muxing the write address of each channel, the PLL clock, horizontal and vertical synchronization signals of each channel, and the color signal of each of the decoded channels according to the mux control signal output from the synchronization signal generating means; A read address generation unit for generating an address of a channel video signal to be read in by introducing a synchronization signal of the synchronization signal generation means; A video RAM for storing or reading video signals of each channel; A memory controller for accessing the video RAM by introducing the read address and the write address of each channel, and outputting a control signal of the video RAM; And a microcomputer control unit for controlling the image switching unit. The multi-closed circuit TV apparatus according to claim 1, wherein the period of the mux control signal flowing into the mux unit is twice the period of the vertical synchronization signal. The multi-closed circuit TV apparatus according to claim 1, wherein the write address means includes two write address generators for generating an address of the video RAM to which video signals of the respective channels are to be written.