KR910007390B1 - Multi-screen window signal generation circuit - Google Patents

Abstract

The circuit for generating the multiwindow signal to a monitor with picutre-in-picture function includes a horizontal counter (10) for generating the 1st-4th horizontal counting signals sequentially, a vertical counter (20) for generating the 1st-4th vertical counting signals sequentially, a horizontal position signal generator (30) for generating the horizontal counting signals corresponding to the horizontal position of the equivalent bank region, a vertical position signal generator (40) for generating the vertical counting signals corresponding to the vertical position of the equivalent bank region, and the window signal generator (50) for generating the horizontal and vertical window signals and logically combining them to generator the window signals selecting multiple bank regions.

Description

Multi-Screen Window Signal Generation Circuit

1 is a specific circuit diagram of the present invention.

2 is an operating waveform diagram for each part of FIG.

3 is a small screen position diagram on a monitor.

4 is an embodiment of small screen generation by a multi-window signal.

* Explanation of symbols for main parts of the drawings

10: horizontal counter 20: vertical counter

30: horizontal position signal generator 40: vertical position signal generator

50: window signal generator

The present invention relates to a picture-in-picture control circuit of an image processing system, and more particularly to a circuit capable of displaying a plurality of picture-in-picture screens on one monitor.

In general, a picture-in-picture control circuit sets a specific area of the main picture area on the monitor to a small picture area in an image processing system such as a television and a VTR. Performs a function to display a screen different from the screen on a small screen. In this case, the conventional PIP controller may display one small picture on the monitor as a still picture and move one small picture being displayed to a specific position. However, the conventional PIP function as described above can provide various services because only one small screen is displayed on the monitor and thus a plurality of small screens cannot be implemented on one monitor or a plurality of small screens can be realized. There is a flaw that can't be.

Accordingly, an object of the present invention is to provide a multi-window signal generation circuit for implementing a plurality of small screens on one monitor when the PIP function is implemented in an image processing system.

It is still another object of the present invention to provide a multi-window signal generation circuit capable of implementing the same screen on a plurality of small screen positions on a monitor.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a concrete circuit diagram of the present invention, which is cleared by the horizontal synchronization signal MH, and counts a color subcarrier signal (fsc) in units of periods of the horizontal synchronization signal MH, and decodes the count value to indicate a horizontal position of a small screen. Cleared by the horizontal counter 10 for generating the first to fourth horizontal count signals L11 to L14 and a vertical synchronization signal Mv, and counting the horizontal synchronization signal MH in the period unit of the vertical synchronization signal Mv; A vertical counter 20 for generating the first-fourth vertical count signals L21-L24 for decoding the count value and indicating the vertical position of the small screen; and the oragate OG1 and the NAND gates NG1, NG2, and NG5. And a first horizontal position signal generator configured to decode the first and second horizontal count signals L11 and L12 and the first horizontal control signal WDL of the horizontal counter 10 to determine whether a window signal is generated at the left small screen position. 31 and Oage (OG2) and NAND gates (NG3-NG5), the third and fourth horizontal count signals L13 and L14 and the second horizontal control signal WDR of the horizontal counter 10 are decoded. A second horizontal position signal generator 32 for determining whether or not a window signal is generated, an OA gate OG3 and a NAND gate NG6, NG7, and NG10 is used to determine the first-second vertical of the vertical counter 10. A first vertical position signal generator 41 which decodes the count signals L21 and L22 and the first vertical control signal WDT to determine whether or not a window signal is generated at the upper small screen position; and an OG4 and a NAND gate NG8-. NG10, which is configured to decode the third and fourth vertical count signals L23 and L24 and the second vertical control signal WDB of the vertical counter 20 to determine whether or not a window signal is generated at a lower small screen position. The signal generator 42, the flip-flops FF1-FF2, and the AND gate AG1. A second vertical beetle signal generator 42 which decodes the third and fourth vertical count signals L23 and L24 and the second vertical control signal WDB of the counter 20 to determine whether or not a window signal is generated at a lower position; A window signal generator comprising a flip-flop (FF1-FF2) and an AND gate (AG1) for receiving a horizontal position signal and a vertical position signal and generating horizontal and vertical window signals of a corresponding small screen position to be displayed on a monitor. 50).

In the above configuration, the horizontal counter 10 and the vertical counter 20 are constituted by an 8-bit counter and a decoding circuit for selecting a specific count value representing the horizontal and vertical positions of each bank area among these counter values.

In the above configuration, the first and second horizontal position signal generators 31 and 32 correspond to the horizontal position signal generator 30, and the first and second vertical position signal generators 41 and 42 are vertical positions. It corresponds to the signal generator 40.

FIG. 2 is an operation waveform diagram of each part of FIG. 1, and FIG. 2a shows a process of generating a horizontal window signal using the color carrier fsc within the horizontal synchronization signal MH period, and FIG. 2b shows a vertical synchronization signal MV period. The process of generating the vertical window signal using the horizontal synchronizing signal MH is shown.

FIG. 3 shows the small screen position on the monitor according to the present invention, and FIG. 4 shows the small screen selection state of each bank area (bank 0-bank 3) set by the multi-window signal.

Based on the above-mentioned configuration, the present invention will be described in detail with reference to the first, second, third and fourth degrees.

To configure a plurality of small screens on one monitor, a plurality of banks must be set and a window signal capable of displaying a plurality of small screens according to the number of banks must be generated. In the present invention, as shown in FIG. 3, four small screens of banks 0 to 3 can be displayed on one monitor, and the horizontal and vertical counters of each bank area are made using the horizontal and vertical counters 10 and 20. FIG. A position signal is generated to determine the horizontal and vertical position of each bank.

In order to determine the horizontal and vertical positions of the respective banks using the horizontal and vertical counters 10 and 20, the horizontal counter 10 is set to 3.58 equal to (A2) during the horizontal synchronization signal MH period such as (A1). The color carrier (fsc) of MHZ is counted, and the count value is decoded to output the first to fourth horizontal count signals L11 to L14 such as (A3) at a specific pixel position, and the vertical counter 20 is (B1). Counts the horizontal sync signal MH of 15.75KHZ, such as (B2), during the vertical sync signal MV period, as shown in (), and decodes this count value to produce the first to fourth vertical count signals L21 such as (B3) Output L24.

In addition, the selection signal of the bank 0-bank 3 is a signal generated by a user's remote controller or key input, and is output from the microcomputer and applied to the oragates OG1-OG4. At this time, each zone of the bank 0-bank of the small screen displayed on the monitor is allocated as shown in FIG. Therefore, when looking at the horizontal position, the regions of the banks 2 and 3 are left windows, and the regions of the banks 0 and 1 are right windows. In addition, when looking at the vertical position, the regions of the bank 1 and the bank 2 is a top window, the regions of the bank 0 and the bank 3 is a bottom window. Therefore, as shown in FIG. 3, the bank 0 area becomes the bottom right, the bank 1 area becomes the upper right, the bank 2 area becomes the upper left, and the bottom left of the bank 3. A window signal generation table for selecting the horizontal and vertical positions of the bank 0 to bank 3 as described above is shown in Table 1 below.

TABLE 1

The OAGs OG1-GO4, which generate the bank selection signals as shown in Table 1, may generate vertical and horizontal control signals of the window signals as shown in Table 2 according to the received bank selection signals.

TABLE 2

In Table 2, the bank selection signal is generated from the microcomputer by the user's selection as described above. Therefore, when the control signals WDL, WDR, WDT, and WDBs generated from the oragates OG1 to OG4 are combined with the output count signals of the horizontal counter 10 and the vertical counter 20 as shown in Table 2, A small screen can be displayed in the bank area on the desired monitor.

First, the horizontal window signal generation process will be described.

The horizontal counter 10 performs the operation by receiving the color carrier signal fsc clock as shown in (A2), and is initialized by the horizontal synchronization signal MH as shown in (A1). Accordingly, the horizontal counter 10 counts the number of pixels of the horizontal line in units of one horizontal synchronization period. In general, the sampling signal of the pixel data is 2fsc or 4fsc. In addition, the horizontal counter 10 should generate a first horizontal count signal L11 to a fourth horizontal count signal L14 for indicating that the bank area is at a specific pixel position. Accordingly, the horizontal counter 10 decodes the pixel count value to generate a first horizontal count signal L11-a fourth horizontal count signal L14 such as (A3) at a specific pixel position of each horizontal line.

As described above, when the horizontal counter 10 generates the first horizontal count signal L11 to the fourth horizontal count signal L14 for each horizontal line, the NAND gates NG1-NG5 are horizontally controlled output from the oragates OG1 and OG2. The horizontal position of the bank is selected according to the states of the signals WDL and WDR. That is, when the bank 2 or the bank 3 is selected, the oragate OG1 outputs the first horizontal control signal WDL as "1". Then, the NAND gates NG1 and NG2 which receive the first horizontal control signal WDL output the first horizontal count signal L11 and the second horizontal count signal L12 in a low state. In addition, when bank 0 or bank 1 is selected, the oragate OG2 outputs the second horizontal control signal WDR as "1". In this case, the NAND gates NG1 and NG2 which receive the second horizontal control signal WDR have the third horizontal count signal L13 and the fourth horizontal count of the horizontal counter 10 while the second horizontal control signal WDR is "high". The signal L14 is output in the "low" state.

Accordingly, the NAND gate NG5 which receives the outputs of the NAND gates NG1-NG4 and performs a negative logic multiplication, when the bank 2 or the bank 3 is selected according to the selection of the bank 0-bank 3, the first horizontal count signal L11 and The second horizontal count signal L12 is output in the "high" state, and when the bank 0 or the bank 1 is selected, the third horizontal count signal L13 and the fourth horizontal count signal L14 are output in the "high" state.

The flip-flop FF1 is then toggled on the first horizontal count signal L11 or the third horizontal count signal L13 to output a signal of the "high" state, and toggled on the second horizontal count signal L12 or the fourth horizontal count signal L14. Low signal will be output. Therefore, when the first horizontal control signal WDL is in the "high" state and the second horizontal control signal WDR is in the "low" state, the flip-flop FF1 generates a left horizontal window signal LHWD such as (A4), and the first When the horizontal control signal WDL is in the "low" state and the second horizontal control signal WDR is in the "high" state, the flip-flop FF1 generates a right horizontal window signal RHWD such as (A5), and the first horizontal window signal. When both the WDL and the second horizontal window signal WDR are in the "high" state, horizontal window signals LHWD and RHWD are generated as shown in (A6).

Therefore, the horizontal window signals LHWD and RHWD as described above are generated as shown in <Table 3> according to each condition.

TABLE 3

L11-L14 in the <Table 3>: first-fourth horizontal count signal of the horizontal counter 10

WDL: Horizontal window control signal (Left window) of banks 2 and 3

WDR: Horizontal window control signal of bank 0, 1

HWD: Horizontal window signal

That is, the horizontal window signal HWD generated through the horizontal counter 10 as shown in (A4)-(A6) of FIG. 2A is the first and second horizontal window control signals WDL, generated by the user's selection. It can be seen that control is possible through the WDR).

Second, the generation process of the vertical window signal will be described.

The vertical counter 20 is initialized by the vertical synchronizing signal MV as shown in (B1) of FIG. 2B, and performs a count operation by receiving a horizontal synchronizing signal such as (B2) as a clock in one vertical synchronizing period. Accordingly, the vertical counter 20 counts the number of horizontal lines of the screen in units of one vertical synchronization period. The vertical counter 20 should also generate a first vertical count signal L21-a fourth vertical count signal L24 to indicate that it is a bank area at a particular horizontal line position. Accordingly, the vertical counter 20 decodes the line count value to generate a first vertical count signal-fourth vertical count signal L24, such as (B3), at a specific horizontal line position in one vertical sync interval.

When the vertical counter 20 as described above generates the first vertical count signal L21 to the fourth vertical count signal L24 in one vertical synchronizing period, the NAND gates NG6-NG10 are in the output states of the oragates OG3 and OG4. This selects the vertical position of the bank. That is, when Bank 1 or Bank 2 is selected, OA gate OG3 outputs the first vertical control signal WDT as "1". Then, the NAND gates NG6-NG7 output the first vertical count signal L21 and the second vertical count signal L22 of the vertical counter 20 in a low state. In addition, when bank 0 or bank 3 is selected, the oragate OG4 outputs the second vertical control signal WDB as "1". The NAND gates NG8-NG9 output the third vertical count signal L23 and the fourth vertical count signal L24 of the vertical counter 20 in a "low" state.

Therefore, the NAND gate NG10 that receives the output of the NAND gates NG6-NG9 and performs a negative logic multiplication, when the bank 1 or the bank 2 is selected according to the selection of the bank 0-bank 3, the first vertical count signal L21 and the first 2 The vertical count signal L22 is output in the "high" state, and when the bank 0 or the bank 3 is selected, the third vertical count signal L23 and the fourth vertical count signal L24 are output in the "high" state.

The flip-flop FF2 is then toggled on the first vertical count signal L21 or the third vertical count signal L23 to output a "high" state signal, and toggled on the second vertical count signal L22 or the fourth vertical count signal L24. Low signal will be output. Therefore, when the first vertical control signal WDT is in the "high" state and the second vertical control signal WDB is in the "low" state, the flip-flop FF2 generates an upper vertical window signal TVWD such as (B4), and the first When the vertical control signal WDT is in the "low" state and the second vertical control signal WDB is in the "high" state, the flip-flop FF2 generates a lower vertical window signal VBWD such as (B5), and the first vertical window signal. If both the WDT and the second vertical window signal WDB are in the " high " state, vertical window signals TVWD and BVWD such as (A6) are generated.

Therefore, the horizontal window signals TVWD and BVWD as described above are generated as shown in <Table 4> according to each condition.

TABLE 4

In Table 4, L21-L24: the first-fourth vertical count signal of the vertical counter 20.

WDT: Vertical window control signal of bank 1 and 2 (Top window)

WDB: Vertical window control signal of bank 0, 3

VWD: Vertical window signal

That is, the vertical window signal VWD generated as shown in FIG. 2B (B4-B6) through the vertical counter 20 receives the first and second vertical window control signals WDT and WDB generated by the user's selection. You can see that it can be controlled.

As described above, the flip-flop FF1 generates the horizontal window signal HWD as shown in (A4)-(A6) of FIG. 2A according to the state of the horizontal control signals WDL and WDR, and the flip-flop FF2 generates the vertical control signal WDT, When the vertical window signal VWD is generated as shown in (B4)-(B6) of FIG. 2B according to the state of WDB, the AND gate AG1 is " high " in the corresponding bank region selected by ANDing the two window signals HWD and VWD. Will output the window signal WD. At this time, the output of the AND gate AG1 is applied as a switching signal of a video switch circuit, and the video switch circuit switches an image signal applied to a monitor. That is, when the AND gate AG1 outputs a "low" signal, the video switch circuit forms a video signal path so that the video signal of the main screen can be output to the monitor, and the AND gate AG1 " Outputting the high " state, the video switch circuit is switched to output the PIP screen output from the memory to the monitor. In this case, the AND gate AG1 outputs a high signal as described above only in the bank regions selected according to the user's bank selection signal, and thus, the AND gate AG1 is generated as a PIP screen only in the selected bank regions.

Therefore, when the PIP screen is to be displayed in the area of Bank 0 to Bank 3 on the monitor, the window control signals WDT and WDB are generated according to the state of the first to second horizontal window control signals WDL and WDR generated by the user's selection. The bank area is determined as shown in <Table 5> according to the state of).

TABLE 5

In the bank display examples shown in Table 5, when the horizontal and vertical window control signals WDL, WDR, WDT, and WDB are changed, the small screen can be moved as shown in FIG. It can also be seen that it can be implemented.

As described above, the small screen can be set by using the horizontal and vertical counters to display the small screen on the monitor, and a multi-window signal can be generated according to the selection input of bank 0-3. It can be displayed on the screen, it is possible to compose a rotation for a single screen or a plurality of small screens, and when using a TV Scan program, a plurality of methods can be simultaneously viewed in a Strobo form. There is this.

Claims (4)

In a picture-in-picture control circuit of an image processing system, the picture-in-picture control circuit is initialized by a horizontal synchronizing signal, counts the number of pixels in units of one horizontal line period using a color subcarrier signal as a clock, and decodes the pixel number count value. The horizontal counter 10 sequentially generates the first to fourth horizontal count signals at the pixel positions, and is initialized by the vertical synchronous signal, and counts the number of horizontal lines in units of one horizontal period using the horizontal synchronous signal as a clock. And a vertical counter 20 for sequentially generating the first to fourth vertical count signals at specific horizontal lines positions by decoding the horizontal line count value, and outputting the horizontal counter 10 and a bank selection signal. Selects and outputs horizontal count signals corresponding to a horizontal position of a corresponding bank area among the first to fourth horizontal count signals according to the bank selection state A horizontal position signal generator 30, an output of the vertical counter 20, and a bank selection signal, and the bank of the first to fourth vertical count signals of the first and fourth vertical count signals Receives the vertical position signal generator 40 for selectively outputting the vertical count signals corresponding to the position, the output of the horizontal position signal generator 30 and the vertical position signal generator 40, the horizontal count signal A window generating a horizontal window signal by a state, a vertical window signal by a state of the vertical count signal, and generating a window signal for selecting a plurality of bank regions by logically combining the horizontal window signal and the vertical window signal. Multi-screen window signal generation circuit, characterized in that the signal generator. The horizontal position signal generator 30 receives the bank 2 and bank 3 selection signals and the first and second horizontal count signals. The horizontal position signal generator 30 receives the bank 2 or bank 3 selection signals. In order to generate a horizontal position signal, a first horizontal position signal generator 31 forming a passage of the first and second horizontal count signals, a bank 0 and a bank 1 selection signal, and a third and fourth horizontal count signals are used. And a second horizontal position signal generator 32 which forms a passage of the third and fourth horizontal count signals to generate a horizontal position signal of the right small screen upon receiving the bank 0 and bank 3 selection signals. Multi-screen window signal generation circuit, characterized in that. The vertical position signal generator 40 of claim 2, wherein the vertical position signal generator 40 receives the bank 1 and bank 2 selection signals and the first and second vertical count signals. A first vertical position signal generator 41 forming a passage of the first and second vertical count signals, a bank 0 and a bank 3 selection signal, and a third and fourth vertical count signals And a second vertical position signal generator 42 which forms a passage of the third and fourth vertical count signals to generate a vertical position signal of a lower small screen upon receiving the bank 0 or bank 3 selection signal. Multi-screen window signal generation circuit, characterized in that. 4. The window signal generator of claim 3, wherein the window signal generator 50 sequentially receives the outputs of the first and second horizontal position signal generators 31 and 32, wherein the first horizontal count signal-fourth horizontal count. Toggles each signal to generate a left horizontal window signal in the interval between the first horizontal count signal and the second horizontal count signal, and generates a right horizontal window signal in the interval between the third horizontal count signal and the fourth horizontal count signal. The generated flip-flop FF1 and the outputs of the first and second vertical position signal generators 31 and 32 are sequentially received and toggled by the first vertical count signal and the fourth vertical count signal, respectively. An upper vertical window signal is generated in the interval between the first vertical count signal and the second vertical count signal, and a lower vertical window signal is generated in the third vertical count signal and the fourth vertical count signal. A flip-flop FF2 for generating a signal and an output of the flip-flops FF1 and FF2 to a gate AG1 for generating a window signal in a common section of a horizontal window signal and a vertical window signal corresponding to a selected bank area. Multi-screen window signal generation circuit, characterized in that configured.

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