KR19990003917A - Method of forming interlayer insulating film of semiconductor device - Google Patents
Method of forming interlayer insulating film of semiconductor device Download PDFInfo
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- KR19990003917A KR19990003917A KR1019970027880A KR19970027880A KR19990003917A KR 19990003917 A KR19990003917 A KR 19990003917A KR 1019970027880 A KR1019970027880 A KR 1019970027880A KR 19970027880 A KR19970027880 A KR 19970027880A KR 19990003917 A KR19990003917 A KR 19990003917A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법Semiconductor device manufacturing method
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 금속층간 절연막으로 사용되는 SOG막 자체의 균열 또는 금속 배선 및 패드 콘택의 열화를 방지하는 반도체 장치의 층간 절연막 형성방법을 제공하고자 함.An object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device which prevents cracking of the SOG film itself or deterioration of metal wiring and pad contacts used as the interlayer insulating film.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 유기계 SOG막 형성후 에치백을 실시하여 평탄화를 이루고, 다시 무기계 SOG막을 형성함으로써 후속 비아홀(또는 콘택홀) 식각시 유기계 SOG막이 노출되지 않도록 함.According to the present invention, an organic SOG film is formed and then etched back to form a planarization, and an inorganic SOG film is formed again so that the organic SOG film is not exposed during subsequent via hole (or contact hole) etching.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치의 다층 금속 배선 공정 및 보호막 공정에 이용됨.Used for multilayer metal wiring process and protective film process of semiconductor device.
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 다층 금속 배선 구조를 사용하는 초고집적 반도체 메모리 장치의 층간 절연막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for forming an interlayer insulating film of an ultra-high density semiconductor memory device using a multilayer metal wiring structure.
일반적으로, 반도체 장치 제조 공정에 사용되는 SOG(Spin On Glass)막은 용액이 갖는 점성도로 평탄화를 이루어 주며, 회전 도포 후 경화(bake) 및 소성(curing)을 거치면서 고분자화되어 절연막의 역할을 한다. SOG막의 종류에는 크게 유기계와 무기계가 있으며, 고분자의 화학 분자 구조와 용매의 종류에 따라 각기 다른 특성을 나타낸다.In general, the SOG (Spin On Glass) film used in the semiconductor device manufacturing process is planarized to the viscosity of the solution, and polymerized through baking and curing after rotational application to serve as an insulating film. . There are two types of SOG films, organic and inorganic, and exhibit different characteristics depending on the chemical molecular structure of the polymer and the type of solvent.
SOG막의 소성 후 기본 구조는 아래의 화학식 1과 같다.After firing the SOG film, the basic structure is represented by Chemical Formula 1 below.
A, B, C, D의 결합 가능 위치(site)에 어떤 라디칼(radical)이 결합하느냐에 따라 유기계 또는 무기계 SOG로 크게 나뉘며, 보통 -CH3, -C2H5, -OCH3,-OC2H5,-C6H4CH3등 탄소계 화합물이 결합하면 유기계이고 -H, -OH 또는 고분자 체인(chain)을 형성하는 -O-등이 결합하면 무기계라고 한다.Depending on which radicals bind to the bondable sites of A, B, C, and D, they are broadly divided into organic or inorganic SOG, and are usually -CH 3 , -C 2 H 5 , -OCH 3 , -OC 2 When carbon-based compounds such as H 5 , -C 6 H 4 CH 3 are bonded, they are organic, and -H, -OH, or -O- which forms a polymer chain, is inorganic.
유기계 SOG막은 메틸(-CH3) 그룹을 많이 함유할수록 경화 및 소성시 리-플로우(re-flow)되는 특성을 가져 평탄화 특성은 좋으나, 후속 공정인 비아(via)콘택 홀 형성시 노출되는 SOG막의 메틸(-CH3) 그룹이 감광막 제거시 사용하는 O2플라즈마에 의해 식각되어 비아홀 측벽의 휨(bowing)현상을 유발시킴으로써 금속의 단차 피복성(step coverage)을 나쁘게 하고, 심지어 단락까지 유발시킨다.The organic SOG film contains more methyl (-CH 3 ) groups, which has reflow properties when cured and fired, so that the planarization property is good. However, the SOG film exposed during the formation of via contact holes, which is a subsequent process, is formed. The methyl (-CH 3 ) group is etched by the O 2 plasma used to remove the photoresist to cause bowing of the sidewalls of the via holes, resulting in poor step coverage and even short circuiting of the metal.
한편, 무기계 SOG막은 메틸(-CH3) 그룹을 함유하지 않아 산소 플라즈마에는 강하나, 두께 한계성이 낮아 두께가 증가할수록 쉽게 균열(crack)이 발생하는 특성을 가지게 되어, 현재 SOG막을 적용하는 대부분의 소자에서 금속 패턴 사이의 골에 채워지는 두께를 고려할 때 그 적용에 한계가 있다.On the other hand, the inorganic SOG film does not contain methyl (-CH 3 ) group, so it is resistant to oxygen plasma, but the thickness limit is low, so that the crack is easily generated as the thickness increases, and most devices currently applying the SOG film. The application is limited when considering the thickness of the filling between the valleys between the metal patterns.
또한, 유기계 SOG막은 소성 후에도 완전히 증발하지 않은 휘발성 물질이 남게 되어 막 자체의 구조가 치밀하지 못하고, 친수성의 막질 때문에 수분 흡수 및 방출이 빈번히 일어나게 된다. 이로 인해 SOG막 상부에 형성되는 금속 배선 또는 보호막의 터짐을 유발하고 콘택홀 하부에 노출된 금속 배선이 산화되어 금속 배선의 자체 저항이 증가하고, 배선 불량을 유발하여 소자의 신뢰성이 저하된다. 또한 방출된 수분은 산화막과 실리콘 기판 사이에 존재하는 실리콘의 미결합 부분에 전기적으로 결합하여 핫 캐리어(hot carrier) 효과 및 필드 역전(field inversion) 효과를 일으키며 소자의 동작 특성을 저하시키는 원인이 된다.In addition, the organic SOG film remains a volatile substance that does not evaporate completely even after firing, and thus the structure of the film itself is not dense, and the water absorption and release occurs frequently because of the hydrophilic film quality. As a result, the metal wires or protective films formed on the SOG film may be burst, and the metal wires exposed under the contact holes may be oxidized to increase the resistance of the metal wires, resulting in poor wiring and deteriorating reliability of the device. In addition, the released moisture is electrically bonded to the unbonded portion of silicon existing between the oxide film and the silicon substrate, causing a hot carrier effect and a field inversion effect, and deteriorating the operation characteristics of the device. .
본 발명은 금속층간 절연막으로 사용되는 SOG막 자체의 균열 또는 금속 배선 및 패드 콘택의 열화를 방지하는 반도체 장치의 층간 절연막 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device which prevents cracking of the SOG film itself or deterioration of metal wiring and pad contacts used as the interlayer insulating film.
도 1a 내지 도 1e는 본 발명의 일실시예에 따른 반도체 장치의 금속층간 절연막 형성 공정도.1A to 1E are process diagrams for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 20 : 셀 지역10 silicon substrate 20 cell region
30 : 주변회로 지역 40 : 광역 굴곡부30: peripheral circuit area 40: wide bend
1 : 하부층 2 : 하부 금속 배선1: lower layer 2: lower metal wiring
3,6 : 산화막 4 : 유기계 SOG막3,6: oxide film 4: organic SOG film
5 : 무기계 SOG막 7 : 비아홀5: inorganic SOG film 7: via hole
상기 목적을 달성하기 위하여 본 발명의 층간 절연막 형성방법은 소정의 하부층이 형성된 반도체 기판 상부에 금속 배선을 형성하는 단계, 전체구조 상부에 제1 절연막을 형성하는 단계, 전체구조 상부에 유기계 실리콘-온 글래스막을 형성하는 단계, 상기 제1 절연막이 노출되도록 상기 유기계 실리콘-온 글래스막을 에치백하는 단계, 전체구조 상부에 무기계 실리콘-온 글래스막을 형성하는 단계 및 전체구조 상부에 제2 절연막을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the method for forming an interlayer insulating film of the present invention includes forming a metal wiring on an upper portion of a semiconductor substrate on which a predetermined lower layer is formed, forming a first insulating film on the entire structure, and forming an organic silicon-on on the whole structure. Forming a glass film, etching back the organic silicon-on glass film to expose the first insulating film, forming an inorganic silicon-on glass film over the entire structure, and forming a second insulating film over the entire structure It is made, including.
이하, 첨부된 도면 도 1a 내지 도 1e를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1A to 1E.
우선, 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 소정의 하부층(1)을 형성하는 공정을 마친 후, 그 상부에 하부 금속 배선(2)을 형성하고, 전체구조 상부에 산화막(3)을 증착한다. 이때, 셀 지역(20)이 주변회로 지역(30) 보다 높아서 단차를 가지는 광역 단차(global topology)가 형성되어 있다. 일반적으로, 도시된 바돠 같이 셀 지역(20)의 하부 금속 배선(2)은 그 선폭 및 간격이 좁고 균일한 반면, 주변회로 지역(30)의 하부 금속 배선(2)은 선폭과 간격이 넓고 균일하지 않다.First, as shown in FIG. 1A, after the process of forming the predetermined lower layer 1 on the silicon substrate 10 is completed, the lower metal wiring 2 is formed on the upper portion thereof, and the oxide film 3 is formed on the entire structure. E). At this time, since the cell region 20 is higher than the peripheral circuit region 30, a global topology having a step is formed. In general, the lower metal wires 2 in the cell region 20 are narrow and uniform in line width and spacing, as shown, while the lower metal wires 2 in the peripheral circuit region 30 are wide in line width, spaced and uniform. Not.
도면 부호 40은 광역 굴곡부를 나타낸 것이다.Reference numeral 40 denotes a wide bend.
다음으로, 도 1b에 도시된 바와 같이 광역 단차를 가진 전체구조 상부에 위에 탄소 성분을 함유한 유기계 SOG막(4)을 용액 회전 방식으로 도포하고, 450℃이하에서 소성 공정(curing)을 실시한다. 이때, 유기계 SOG막(4)은 SOP(Spin On Polymer)막으로 대신하여 사용할 수도 있다.Next, as shown in FIG. 1B, an organic SOG film 4 containing a carbon component is applied on the upper part of the whole structure having a wide step in a solution rotation method, and a baking process is performed at 450 ° C. or lower. . In this case, the organic SOG film 4 may be used instead of a spin on polymer (SOP) film.
이어서, 도 1c에 도시된 바와 같이 유기계 SOG막(4)을 O2플라즈마를 사용하여 주변회로 지역(30)에 있는 하부 금속 배선(2) 상단의 산화막(3)이 드러날 정도까지 식각한다. 이때, O2플라즈마에 의한 식각은 기존의 식각 장비 및 포토레지스트 제거 장비 또는 플라즈마 증착 장비 등에서 이루어질 수 있고, O2플라즈마 식각시 산화막(3) 또는 하부층(1) 등의 식각 손실이 전혀 없이 단지 유기계 SOG막(4)만을 선택적으로 식각할 수 있다. 즉, 유기계 SOG막(4) 내의 탄소(C) 성분이 O2플라즈마와 반응하여 CO 혹은 CO2형태로 산화되면서 유기계 SOG막(4)의 선택적 식각이 이루어진다. 또한, 주변회로 지역의 산화막(3)을 식각 정지층으로 하는 이유는 이후 형성되는 비아홀의 측벽 부위에 유기계 SOG막(4)이 노출되는 것을 억제할 수 있을 뿐만 아니라, 후속 무기계 SOG막 형성시 평탄화에 유리하도록 하기 위함이다.Subsequently, as shown in FIG. 1C, the organic SOG film 4 is etched using O 2 plasma to the extent that the oxide film 3 on top of the lower metal wiring 2 in the peripheral circuit region 30 is exposed. At this time, the etching by the O 2 plasma may be made in conventional etching equipment, photoresist removal equipment, or plasma deposition equipment, and the like, in the O 2 plasma etching, there is no etch loss of the oxide layer 3 or the lower layer 1, etc. Only the SOG film 4 can be selectively etched. That is, the carbon (C) component in the organic SOG film 4 reacts with the O 2 plasma to be oxidized in the form of CO or CO 2 to selectively etch the organic SOG film 4. Further, the reason why the oxide film 3 in the peripheral circuit region is used as an etch stop layer is not only to suppress the exposure of the organic SOG film 4 to the sidewall portion of the via hole to be formed later, but also to planarize the subsequent inorganic SOG film formation. This is to advantage.
계속하여, 도 1d에 도시된 바와 같이 전체구조 상부에 무기계 SOG막(5)을 형성한다.Subsequently, an inorganic SOG film 5 is formed on the entire structure as shown in FIG. 1D.
끝으로, 도 1e에 도시된 바와 같이 전체구조 상부에 산화막(6)을 증착하고, 산화막(6), 무기계 SOG막(5) 및 산화막(3)을 차례로 선택적 식각하여 금속 배선(3)을 노출시키는 비아홀(7)을 형성한다. 여기서, 비아홀(7) 측벽 부위에서 유기계 SOG막(4)이 노출되지 않으므로, 후속 상부 금속 배선 형성시 단선 또는 공극(void) 등의 악영향을 미치는 비아홀 측벽 휨 현상을 방지할 수 있게 된다. 또한, 이후 콘택 저항의 상승을 유발하는 SOG막으로부터 비아홀 내로의 수분 방출 현상등은 발생되지 않는다.Finally, as shown in FIG. 1E, an oxide film 6 is deposited on the entire structure, and the oxide film 6, the inorganic SOG film 5, and the oxide film 3 are selectively etched in order to expose the metal wiring 3. The via hole 7 is formed. Here, since the organic SOG film 4 is not exposed in the sidewall portion of the via hole 7, it is possible to prevent the via hole sidewall bending phenomenon that adversely affects disconnection or voids in the subsequent formation of the upper metal wiring. In addition, there is no occurrence of water release phenomenon into the via hole from the SOG film which causes an increase in contact resistance.
상기한 본 발명의 일실시예에서 산화막(3,6)은 절연막을 대표하여 나타낸 것으로, 다른 종류의 절연막을 사용할 수도 있다.In the above-described embodiment of the present invention, the oxide films 3 and 6 represent the insulating films, and other types of insulating films may be used.
본 발명의 다른 실시예는 본 발명의 층간 절연막 형성 공정을 보호막 형성 공정시 적용하는 것이다. 즉, 패드 식각시 측벽에서 유기계 SOG막이 노출되지 않도록 함으로써 유기계 SOG에 의한 수분 침투 경로를 차단 시킬 수 있다.Another embodiment of the present invention is to apply the interlayer insulating film forming process of the present invention during the protective film forming process. That is, by preventing the organic SOG film from being exposed on the sidewalls during the pad etching, the water penetration path by the organic SOG may be blocked.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
이상에서와 같이 본 발명을 실시하면 셀 지역과 주변회로 지역의 단차가 큰 반도체 장치의 다층 금속 배선 공정 또는 보호막 공정에 있어서 상부 금속 배선의 단선, 합선 등에 의한 페일을 방지할 수 있으며, 또한 비아홀 콘택에서의 수분 침투에 의한 금속 배선의 신뢰성 저하를 방지하는 효과가 있다. 또한, 본 발명은 SOG막 에치백시 선택 식각비를 맞출 필요가 없기 때문에 공정 단순화 측면에서도 유리하다.As described above, according to the present invention, in the multilayer metal wiring process or the protective film process of the semiconductor device having a large step difference between the cell region and the peripheral circuit region, failure due to disconnection or short circuit of the upper metal wiring can be prevented, and via hole contact can be prevented. There is an effect of preventing a decrease in the reliability of the metal wiring due to moisture infiltration in water. In addition, the present invention is advantageous in terms of process simplification since there is no need to match the selective etching ratio during etch back of the SOG film.
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| KR20010066380A (en) * | 1999-12-31 | 2001-07-11 | 박종섭 | Method for forming semiconductor device with multi-layered metal line |
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| KR20010066380A (en) * | 1999-12-31 | 2001-07-11 | 박종섭 | Method for forming semiconductor device with multi-layered metal line |
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