KR19990002550A - Bit-by-bit write control circuit of synchronous memory device - Google Patents

Abstract

The present invention relates to a bit-by-bit write control circuit implemented to use mask data input to an input buffer as an input when performing a bit-by-bit write operation as a control data for enabling a register in which the mask data is latched. A bit-by-bit write control apparatus of a synchronous memory device that controls bit-by-bit write by mask data input through a data input buffer and a mask loading control signal loading the register into a register to implement the same. A first register for setting the mask data to the first level at the first level, a second register for setting the mask data to the second level at initial power-up, mask data input through the data input buffer, and mask loading as a control signal A first controlled by a control signal to switch the output of the first register A second switching unit which is controlled by a switching unit, mask data input through a data input buffer, a mask loading control signal which is a control signal, and switches the output of the first register, the first switching unit and the second switching unit And a selective output section for selectively outputting the negative output by the bit-by-bit write control signal.

Description

Bit-by-bit write control circuit of synchronous memory device

The present invention relates to an apparatus for latching mask data in a load mask register (LMR) to perform a bit-by-bit write operation (WPB) used in a synchronous graphics RAM.

In general, the bit-by-bit recording operation is frequently used for pixel-by-pixel access in synchronous graphic RAM or video RAM, which includes selecting a corresponding bit among bytes or words as mask data. And writing the data to the bit selected by the mask. The log mask register is a configuration for selection by this mask.

1 is a conventional bit-by-bit write control circuit diagram, and FIG. 2 is an operation timing diagram.

Referring to the operation timing diagram illustrated in FIG. 2, in the conventional bit-by-bit write operation, FIG. 4 in which the mask data (if low) of the data input buffer DIN_BUFF is operated in the cycle 301 of FIG. 3. The node of node 1 106 becomes high when node 103 is latched low by the 1mr 104 signal of < RTI ID = 0.0 > and < / RTI > the signal wpb 105, which is also generated in cycle 301, is enabled for bit-by-bit writing. When the recording data written in the recording cycle 302 is ignored and nw 109, which is a recording signal generated in the cycle 302, is enabled, the recording is performed as q 107 and q_b 108 are not activated. No action is taken.

Then, after the write operation is finished, the precharge command 303 is input to disable the wpb signal 105, so that the state of the node 1 106 is able to accept the input of the data input buffer DIN_BUFF again. Go back.

In the cycle 304, even when the WPB operation occurs, the mask data in the data input buffer is high, so that the node 103 is latched high during the operation of the 1mr signal 104, and thus, regardless of the wpb signal 105, the node 1 ( 106 goes low to receive the write data input from the cycle 305. q 107 and q_b 108 are activated and can perform a write operation together with the nw signal 109 which is also generated in the cycle 305.

The LCR register 407 is used in the block write mode, which is a special mode of the graphics RAM, and replaces the role of the DQ input from the input buffer during the write operation and is not related to the present invention. Conventionally, as described above, the mask data for the WPB operation may be generated by being latched in one LMR register.

Accordingly, an object of the present invention is to implement a bit-by-bit write operation by using mask data input to the input buffer when performing a bit-by-bit write operation as an input of control data for enabling a register in which the mask data is latched. It is to provide a star recording control circuit.

1 is a conventional bit-by-bit write control circuit diagram.

2 is an operation timing diagram of FIG. 1.

3 is a bit-by-bit write control circuit diagram according to an embodiment of the present invention.

4 is an operation timing diagram of FIG. 3.

* Description of the symbols for the main parts of the drawings *

21: First register 22: Second register

23: first switching unit 24: second switching unit

25: Selective output unit

In accordance with another aspect of the present invention, a bit-by-bit write control apparatus of a synchronous memory for controlling bit-by-bit write by mask data input through a data input buffer and a mask loading control signal for loading the register into a register is used. A first register 21 for setting mask data to a first level when power is applied; A second register 22 for setting the mask data to the second level when the initial power is applied; A first switching unit 23 controlled by mask data input through a data input buffer and a mask loading control signal serving as a control signal to switch the output of the first register; A second switching unit 24 controlled by mask data input through a data input buffer and a mask loading control signal serving as a control signal to switch the output of the first register; And a selection output section 25 for selectively outputting the outputs of the first switching section and the second switching section by the bit-by-bit write control signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a bit-by-bit write control circuit diagram according to an embodiment of the present invention, and FIG. 4 is an operation timing diagram.

The present invention performs the same operation while transforming the mask data input from the data input buffer in the WPB cycle to control only two registers latched high and low. In other words, the existing mask data register is one to two. In addition, in the WPB cycle 301, the mask data is not inputted from the data input buffer, but the mask data is latched to the node 202 high and the node 203 low when the voltage is applied by the Wrup signal 209. .

In this state, when the mask data of the WPB cycle 301 and the data input buffer is input low, only the node 205 together with the 1mr signal 104 has a pulse phase. The mask data DQ of the data input buffer makes the node 208 high and the node 207 low, thereby making the phase of node 1 high as the wpb signal generated by the cycle 301 is enabled. Since the data input at 302 cannot be accepted and q 107 and q_b 108 cannot be activated, even if nw 109 (write operation signal) is enabled, the write operation does not occur. When the precharge command 303 is input, the wpb signal 105 is disabled, and thus the contents of the data input buffer can be accepted regardless of the nodes 207 and 206 of the node 1.

In the cycle 304, even though the wpb command occurs, the mask data of the data input buffer is high, so that only the node 204 together with the 1mr signal 104 has the pulse phase and the mask data that is the high of the node 202 is node 207. Node 208 is latched high as node 208 goes low. Then, regardless of the signal of the wpb signal 105 and the node 206, the phase of the node 1 goes low, so that q 107 and q_b 108 are activated during the write input of the data input buffer in the write cycle 305, and again. The write operation can be performed with the write signals nw and 109 enabled in the cycle 305.

As described above, according to the bit-by-bit write control circuit of the present invention, when a bit-by-bit write operation is performed, the mask data input to the input buffer is received as an input to perform a bit-by-bit write operation. There is an effect that can be used as control data for enabling.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit-by-bit write control circuit of a synchronous memory device, and in particular, receives mask data input to an input buffer when performing a write per bit operation (hereinafter, referred to as 'WPB'). And a bit-by-bit write control circuit implemented to perform a WPB operation as control data for enabling a mask data latched register.

Claims (1)

In the bit-by-bit write control device of a synchronous memory device for controlling the bit-by-bit write by the mask data input through the data input buffer and the mask loading control signal for loading it into a register, A first register for setting the mask data to the first level when the initial power is applied; A second register which sets the mask data to the second level when the initial power is applied; A first switching unit which is controlled by mask data input through a data input buffer and a mask loading control signal which is a control signal and switches the output of the first register; A second switching unit which is controlled by mask data input through a data input buffer and a mask loading control signal which is a control signal and switches the output of the first register; And a selection output section for selectively outputting outputs of the first switching section and the second switching section by the bit-by-bit write control signal.