KR19990002379A - Discharge maintenance control method for driving PDP-TV. - Google Patents

Abstract

The present invention relates to a PDP-TV system, and relates to signal processing for PDP gradation processing. For efficient PDP gradation processing, one frame is divided into a plurality of subfields, and in one subfield, an entire screen erasing (Erasing mode, first step), data writing and scanning (second step), and discharge maintenance are performed. (Discharge Sustain mode, step 3) is repeatedly performed.

The operation of the first and second processes is fixed, but the discharge sustaining section of the third step is used to generate a repetitive waveform by varying the discharge sustaining interval by the weight of each digital data for gradation processing. Note is a variable section. For efficient control of the discharge sustain operation, which is a variable section, in the present invention, a count signal p-vari of a variable discharge sustain section and a count signal c-vari capable of counting a repeating unit for a repetitive operation during the section are provided. By using a signal, a method for efficiently controlling the variable characteristics of the discharge sustaining section is proposed.

Description

Discharge Maintenance Control Method for Driving PDP-TV

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PDP-TV system, and more particularly, to a PDP gradation processing method for displaying an image on a plasma panel. In particular, the present invention relates to a PDP-TV system. The present invention relates to a signal processing method of a discharge holding section.

The driving method of the PDP, which is a flat panel display, is different from the driving method of a general CRT. In particular, in the method of the gradation processing, the CRT adopts a method in which the electron gun sequentially scans the pixels one by one, and the gradation processing is composed of a simple driving circuit driven by an analog method, and the driving speed is several tens of nanoseconds (㎱). It is very fast, but it is very difficult to implement the driving of millions of pixels by one pixel when the number of pixels increases to millions such as HDTV. However, in the case of the PDP, a matrix driving method using a strong nonlinearity of gas discharge is used instead of scanning by one pixel. Nonlinearity is a characteristic of gas discharge. Since the gas discharge phenomenon is caused by ionization through the ionization process of the gas, the discharge occurs only when a voltage higher than the discharge voltage at which the ionization reaction can occur sufficiently is applied. Is a characteristic of gas discharge in which no discharge occurs.

PDPs are generally driven by a series of pulses with a constant voltage, and gradation display is implemented by digital rather than analog.

In a driving method for grayscale processing of a PDP, it is common to repeatedly read Even line data after reading one line of Odd line data for one field of image data stored in a memory. In this case, one field is divided into a plurality of subfields (256 gray levels-8 subfields), and image data corresponding to each subfield is read in order and provided to the data interface unit. The driving method of one subfield is performed in the following driving order.

As the operation mode for erasing discharge, in case of AC PDP, the discharge is formed at low voltage in the period of neutralizing the subordinate charge so that the wall charge is not sufficiently formed or the erase charge pulse having short pulse width is applied to the normal state of the wall charge. Remove wall charges by preventing them from reaching. That is, in order to erase the wall charge remaining in the selected (discharged) pixel after the discharge sustain of the previous subfield, the wall charge is written to all the pixels for a short time which is not visible, and then all the pixels. Erasing mode, which initializes the PDP by erasing all remaining wall charges, and writes the data on a line-by-line basis through the data write electrode while shifting the scan pulse to the line scan electrode. The data writing and scan mode necessary for the initial discharge formation to selectively form the wall charge in the pixel to be made, and the storage function characteristics of the gas discharge are applied to the sustain pulse having a lower voltage than the selection pulse. In the discharge sustain operation (Discharge sustain) in which the discharge is maintained, the driving method of one subfield as described above, The signal processing states of the entire screen erasing section and the data writing and scanning section are fixed unchanged for each subfield. However, since the discharge sustaining section corresponds to the image display section, it functions differently for each subfield according to the length of the input data. That is, the discharge maintenance section is a variable section that gives a repetitive waveform by varying the discharge maintenance section by the weight of each digital data for gradation processing.

In the related art, the signal processing of the variable discharge sustaining section is controlled depending on the main clock used in the entire screen erasing and data writing and scanning sections, which are the fixed section, and thus the signal processing is not smooth and noise is generated. there was.

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art as described above, and has been invented to solve the problem. In order to efficiently control the signal processing of the discharge sustaining section in driving one subfield, The signal of the basic counter that counts is called P-Vari, and the count signal that can count the repeating unit for the repetitive operation during that period is C-Vari, and the variable discharge maintenance section using the two count signals described above. It is an object of the present invention to provide a method for controlling signal processing of a signal.

1 is an overall configuration diagram of a PDP-TV system

FIG. 2 is a detailed block diagram of a memory unit as a main part of FIG. 1;

3 is a driving explanatory diagram of one subfield of the present invention;

4 is an explanatory view of a discharge maintenance control method which is a variable section of the present invention;

* Explanation of symbols on the main parts of the drawings *

1-AV part 2-ADC part

3-memory section 4-data interface section

5-Timing Controller 6-Address Drive IC

7-Hold / Scan Drive IC 8-High Voltage Drive Circuit

9-AC / DC switcher 10-Complex video signal processor

20-Digital Data Processing Unit 30-PDP Driver

40-data rearranger 50-address generator

60-Control Clock Generator 100-Full Screen Clearance Area

200-Writing and scanning section 300-Discharge holding section

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The AC type PDP-TV system has a configuration schematically shown in FIG. The composite video signal received through the antenna is analog-processed by the audio-video (AV) unit 1 of the analog signal processing unit 10 and digitalized by constant data in the analog-to-digital conveter (ADC) unit 2. The image data is driven through the memory unit 3 and the data interface unit 4 of the digital data processing unit 20 in the form of a data stream conforming to the PDP gradation processing characteristics. To the IC 6.

In addition, the timing control unit 5 of the PDP driver 30 and the high voltage driver circuit unit 8 of the PDP driver 30 output a high voltage control pulse required by the holding / scanning driving IC 7 to convert the AC / DC. The unit 9 generates and supplies all the DC voltages required by the entire system using the AC power as an input. The above configuration will be described in more detail for each block.

The AV unit 1 receives the NTSC composite signal, separates the analog R, G, and B signals from the horizontal and vertical synchronization signals, and obtains an APL (Average Picture Level) corresponding to the average value of the luminance signal (Y). It supplies to (2). This APL is used to improve the brightness of PDP-TV systems. NTSC composite video signal is interlaced, and one frame is composed of two fields of Odd / Even, horizontal synchronous signal is about 15.73KHZ and vertical synchronous signal is about 60Hz. The audio signal separated from the composite video signal is output through the audio amplifier directly to the speaker.

The ADC unit 2 receives analog R, G, and B signals as inputs, converts them into digital data, and outputs the digital data to the memory unit 3. In this case, the digital data has a converted shape to improve the brightness of the PDP-TV system. Video data. The ADC section 2 is divided into an amplifier section, a clock generation section, a sampling area setting section, and a data mapping section. The AMP unit amplifies the analog R, G, B, and APL signals to a signal level suitable for quantization, converts horizontal and vertical synchronization signals into a constant phase, and outputs the same.

The clock generator must use a clock that is synchronized with the input synchronization signal. To this end, the clock generator generates clocks using phase locked loops (PLLs). The PLL is oscillated by the LF (Loop Filter), which outputs the control voltage of PD (Phase Detector), VCXO (Voltage Controlled Crystal Oscillstor), which compares the phase of the input synchronous signal with the phase of the variable pulse output from the loop. A VCXO and a PC (Programmable Counter) for dividing the output of the VCXO and outputting a phase comparison pulse to output a clock synchronized with the input synchronous signal. If the clock synchronized to the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed.

The sampling area is set to the vertical position and the horizontal position. The vertical position section is a pulse for setting only the line with the image information among the input signals, and the horizontal position section is a pulse for setting only the time with the image information among the lines set to the vertical position. The vertical position section and the horizontal position section are the standards for sampling. A total of 480 lines are selected, 240 lines each in the Odd / Even field. The horizontal position section should be the time for which at least 853 sampling clocks (if spec is set to 853) can exist for each selected line.

The data mapping unit maps the R, G, and B data output from the A / D converter into data corresponding to the brightness characteristics of the PDP. In other words, by arranging several vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the R, G, B data output from the A / D converter is 1: 1 mapped to improve R, G, B. It is provided to the memory unit 3 in the form of data.

In the memory unit 3, for the PDP gradation processing, it is necessary to reconstruct the video data of one field into a plurality of subfields, and then rearrange from the most significant bit MSB to the least significant bit LSB. In addition, since the image data input by the interlaced scanning method is converted to the progressive scanning method and displayed, an area for storing one frame of image data is required.

2 is a block diagram of the memory unit 3 that performs the above functions. That is, the memory unit 3 can be largely divided into a data rearrangement unit 40 and an address generation unit 50. In addition, the memory unit 3 includes a control clock generator 60, two frame memories A, B, and a data selector.

The data rearrangement unit 40 is composed of shift registers A, B, D-FF MUX. (D flip-flop and multiplexer), and three-state buffers A, B, and the ADC unit 2 in parallel (MSB to LSB). The provided image data is rearranged so as to store bits having the same weight in one address of the frame memory. While the first shift register loads eight samples of image data, in the second shift register, eight samples of image data previously loaded are the least significant bit (LSB, 8) from the most significant bit (MSB, 8 Bits). Bits) are output while sequentially shifting.

In order to continuously rearrange the video data provided by the ADC unit 2, two first and second shift registers are provided, and they alternately load and shift. The D-FF MUX selects the same weighted data (Recordered Data) output in the shift mode and supplies it to the tri-state buffer.

In addition, two frame memories are provided for storing one piece of image data (853 x 3 (RGB) x 480 x 8 Bits x 10 Mbit), and they alternately perform write and read operations in units of frames. The video data can be stored and displayed continuously. Therefore, the three-state buffers A and B serve to connect the rearranged image data provided from the D-FF MUX to the frame memory in the write mode.

In the address generator 60, the image data inputted by the interlaced scanning method is converted into a sequential scanning method and displayed so that the order of write addressing and read addressing are different. That is, image data of one field stored in the memory is repeatedly read even line data after reading one line of Odd line data. Further, in the PDP gradation process, one field is divided into several subfields, and image data corresponding to each subfield must be read in turn and provided to the data interface unit 4, so that the reading order is structurally very different from the writing order. Will have Therefore, a write address generator and a read address generator according to the designed memory map configuration are required, and the address selector serves to provide a corresponding address according to each operation mode (write and read mode) of the frame memories A and B.

The control clock generator 60 inputs the vertical and horizontal synchronization signals H and Vsync and the main clock to generate and supply the write / read address clock and all other logic control pulses required to drive the memory unit 3. . The data selector selects and outputs the image data output in the read mode from the frame memories A and B to the data interface unit 4. The data interface unit 4 temporarily stores R, G and B data from the memory unit 3 and provides the data in the form of data required by the address driver IC 6. It is required to be arranged in accordance with the arrangement of the R, G, and B pixels output from the memory section 3 and supplied to the address driver IC 6, which is why the data interface section 4 is required. The display size is 853 × 3 (r, g, b) × 480, and the data interface unit 4 should temporarily store one line (853 × 3 = 2559 bits) of data. Since the output must be performed simultaneously, two lines of temporary storage (2559 x 2 = 5118 bits) are needed. That is, a total of 24 bits of data, 8 bits each of R, G, and B, are inputted from the memory unit 3 into the temporary storage area A in turn (107 times) (24 bits x 107 = 2598 bits), and the temporary storage area B at the same time interval. The previous one-line amount of data is output in the form of a data stream required by the address driver IC 6.

Such input / output operations occur alternately in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the operation is then reversed.

When outputting the temporarily stored image data to the address driver IC 6, the data interface unit 4 provides 1 bit of data and a total of 48 bits of image data to each driver IC in the form of a stream. When data is input to the driver IC in turn (75 times), when shifted in parallel, one line (48 bits x 75 = 3600 bits) of image data is loaded into the address driver IC. Since this process should be the same as the input mode operation time of other temporary storage areas, the input mode should be operated at twice the frequency of the output mode.

The high voltage driving circuit unit 8 combines the DC high voltage supplied from the AC / DC converter 9 according to the control pulses of various logic levels output from the timing controller unit 5 to maintain / scan the drive IC 7. Generate the necessary control pulses to drive the PDP. In addition, the data stream provided from the data interface unit 4 to the address driver IC 6 is also raised to an appropriate voltage level to enable selective writing on the panel.

As described above, the driving method for the PDP gradation process first divides one field (60 Hz) into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and then divides the image data corresponding to each subfield. Through the address driving IC 6, writing is performed in units of lines. In the subfield to which MSB data is written, the number of discharge sustain pulses is reduced in order from the LSB subfield, and gradation processing is performed in the total discharge sustain period according to a combination thereof.

In addition, the driving sequence of all subfields repeats operations of full screen writing and erasing, data writing, and discharge holding (screen display). This process is outlined as follows.

First, in the operation mode for erasing discharge, in case of AC PDP, the discharge is formed at a low voltage in the period of neutralizing the substation charge so that the wall charge is not sufficiently formed or the erase charge pulse having a short pulse width is applied so that the wall charge is normal. Remove wall charges by preventing them from reaching the state. In order to erase the wall charge remaining in the selected (discharged) pixel after discharge sustaining of the previous subfield, the wall charge is written to all the pixels for a short period of time which is not visible, and then all the pixels are discharged. Erasing mode operation that initializes the PDP by erasing all remaining wall charges.

Secondly, as a driving operation necessary for initial discharge formation, the Hening-NeXe and Ne + Xe penning mixtures generally used in the PDP apply a potential of 240 Volt to 280 Volt. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation. In practical applications, it is also called a selection operation because a wall charge is selectively formed on a pixel to be discharged by writing the data in line units through the data writing electrode while shifting the scanning pulse sequentially (1 to 480) to the line scanning electrode. A data writing and scanning operation,

Finally, the discharge operation is maintained by the sustain pulse having a voltage lower than the selection pulse by using the memory function characteristic of gas discharge. In the case of AC PDP, the memory function effect by wall charge and the self priming effect are used in case of DC PDP. In the case of the memory type driving method which can separate the selection operation and the holding operation by using the memory function, in the case of high gradation display for realizing a high quality display device, the PDP can operate without deterioration of luminance even for a large display device. It provides a driving method. In practice of the discharge sustain operation, a sustain pulse is alternately applied between the discharge sustain driver electrode and the line scan electrode to start and sustain the discharge of the pixel on which the wall charge is formed. At this time, the unwritten pixel is affected by the written peripheral pixels, which may cause an error discharge. Therefore, a small erase is performed every time the sustain pulse is applied to ensure accurate discharge. The AC / DC converter 9 uses AC power (220V, 60Hz) as input to generate and supply the high voltage required to combine the electrode driving pulses and the DC voltage required by each part constituting the PDP-TV system. do.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the present invention with respect to the grayscale processing of the PDP-TV system will be described in detail. As described above, in the driving method of one subfield, the signal processing states of the entire screen erasing section and the data writing and scanning section are fixed without changing according to each subfield, and the discharge holding section is an image. Since it corresponds to the display section, it can be seen that the subfields operate differently according to the length of the input data. That is, the discharge maintenance section is a variable section that gives a repetitive waveform by varying the discharge maintenance section by the weight of each digital data for gradation processing. If the count of the variable section is controlled with one fixed count signal, signal processing is not smooth.

3 illustrates driving of one subfield of the present invention. That is, in the subfield operation control method of the present invention, in the method of driving one subfield for PDP gray scale processing, the wall charge remaining by erasing all pixels to erase the wall charge remaining after the discharge holding of the previous subfield is erased. A first process (100) of initializing the PDP by erasing the PDP, a second process (200) of writing data, and writing and scanning data to sequentially scan the scan pulses to the electrodes of the line scan and discharge sustain driver; And a third step (300) of applying a sustain pulse to the discharge holding driver of the PDP to initiate and maintain the discharge of the pixel on which the wall charges are formed. The third process 300 is repeated for the first count signal P-Vari for counting a variable discharge sustaining interval and for the repeated operation for the repetitive operation during the above interval. A variable discharge holding operation of the third process is controlled by using two signals of the second count signal C-Vari capable of counting a unit.

4 is a view for explaining the operation of the discharge holding interval of the present invention using the two count signals (P-Vari, C-Vari) described above. The first count signal P-Vari, which is a variable section count signal of the discharge sustain period, uses a 15-bit counter of 2 MHz clock, and the second count signal C-Vari uses a 6-bit counter (FF1 to FF6). I use it. When the C-Vari count of the second counter signal is 40, the first count signal P-Vari and the second count signal C-Vari are inputted to the AND gate to reset the 6bits counter. It is characterized by controlling the drive of the variable discharge holding section.

The signal processing of the variable discharge holding section is controlled depending on the main clock used in the above-mentioned fixed screen full screen erasing and data writing and scanning sections, so that the signal processing is not smooth and is not suitable for driving the variable section. In the PDP gradation process, the present invention relates to a signal P-Vari of a basic counter that counts a variable section of the discharge sustain section in order to efficiently control the signal processing of the discharge sustain section in the driving of one subfield. The signal processing of the variable discharge holding section is controlled by using two count signals of the count signal C-Vari which can count the repeating units for the repetitive operation during the period, and thus the signal processing of the variable section is accurate. It is effective to control efficiently.

Claims (3)

1. A method of driving one subfield for PDP gradation processing, the method comprising: erasing all the pixels to erase the wall charges remaining after the discharge of the previous subfield is erased, thereby erasing the remaining wall charges; 100), a second process 200 of writing data and writing and scanning data to sequentially scan the scan pulses to the electrodes of the line scan and discharge sustain driver, and the sustain pulse to the discharge sustain driver of the PDP. In the gradation processing method of the PDP-TV system comprising a third step (300) of applying and initiating and maintaining the discharge of the pixel is formed by the wall charge, The third process 300 may count the first count signal P-Vari for counting a variable discharge sustain period and a repeating unit for the repeated operation for the repetitive operation during the above period. A discharge maintenance control method for driving a PDP-TV, characterized in that for controlling the driving of the variable discharge maintenance interval using two signals of the second count signal (C-Vari). The method of claim 1, wherein the first count signal P-Vari, which is a variable section count signal of the discharge sustain period, uses a 15-bit basic counter of 2 MHz clock, and the second count signal C-Vari is 6 bits (FF1). A discharge maintenance control method for driving a PDP-TV, characterized by using a FF6) counter. The method of claim 2, wherein the first count signal P-Vari and the second count signal C-Vari are inputted to an AND gate when the C-Vari count of the second counter signal is 40. Discharge maintenance control method for driving a PDP-TV, characterized in that to reset the 6bits counter.